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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.34 2002/09/08 16:31:49 mohor
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// Async reset for WB_ACK_O removed (when core was in reset, it was
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// impossible to access BDs).
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// RxPointers and TxPointers names changed to be more descriptive.
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// TxUnderRun synchronized.
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//
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// Revision 1.33 2002/09/04 18:47:57 mohor
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// Revision 1.33 2002/09/04 18:47:57 mohor
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// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
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// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
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// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
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// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
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// was not used OK.
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// was not used OK.
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//
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//
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Line 199... |
// Rx Status
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// Rx Status
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InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
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InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
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ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
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ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
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// Tx Status
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// Tx Status
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RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost,
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RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
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reg1, reg2, reg3, reg4
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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output [31:0] reg1, reg2, reg3, reg4;
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// WISHBONE common
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// WISHBONE common
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input WB_CLK_I; // WISHBONE clock
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input WB_CLK_I; // WISHBONE clock
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input [31:0] WB_DAT_I; // WISHBONE data input
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input [31:0] WB_DAT_I; // WISHBONE data input
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output [31:0] WB_DAT_O; // WISHBONE data output
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output [31:0] WB_DAT_O; // WISHBONE data output
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Line 2189... |
// bit 3 od rx je ReceivedPacketTooBig
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// bit 3 od rx je ReceivedPacketTooBig
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// bit 2 od rx je ShortFrame
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// bit 2 od rx je ShortFrame
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// bit 1 od rx je LatchedCrcError
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// bit 1 od rx je LatchedCrcError
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// bit 0 od rx je RxLateCollision
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// bit 0 od rx je RxLateCollision
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assign reg1 = {RxPointerMSB[31:2], 2'h0}; /* 0x58 */
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assign reg2 = { /* 0x5c */
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RxStatusWriteLatched, // 31
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RxStatusWrite_rck, // 30
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RxEn_needed, // 29
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StartRxBDRead, // 28
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RxStatusWrite, // 27
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1'b1, //RxAbortLatched, // 26
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RxBDRead, // 25
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RxBDReady, // 24
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ShiftEnded, // 23
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RxPointerRead, // 23
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LastByteIn, // 21
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ShiftWillEnd, // 20
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2'h0, RxByteCnt[1:0], // 19:16
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2'h0, RxPointerLSB_rst[1:0], // 15:12
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RxBDAddress[7:0], // 11:4
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4'h0 // 3:0
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};
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assign reg3 = { /* 0x60 */
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ShiftEndedSync_c2, // 31
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RxAbortSyncb1, // 30
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RxAbortSyncb2, // 31
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RxAbortSync1, // 30
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RxAbortSync2, // 29
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1'b0, //LoadStatusBlocked, // 28
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LoadRxStatus, // 27
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1'b0, //LoadStatusBlocked, // 26
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RxOverrun, // 25
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RxAbort, // 24
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RxValid, // 23
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RxEndFrm, // 22
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RxEnableWindow, // 21
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StartShiftWillEnd, // 20
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ShiftWillEnd, // 19
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ShiftEnded_rck, // 18
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SetWriteRxDataToFifo, // 17
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WriteRxDataToFifo, // 16
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WriteRxDataToFifoSync3, // 15
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WriteRxDataToFifoSync2, // 14
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WriteRxDataToFifoSync1, // 13
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WriteRxDataToFifo_wb, // 12
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LatchedRxStartFrm, // 11
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RxStartFrm, // 10
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SyncRxStartFrm, // 9
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SyncRxStartFrm_q, // 8
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SyncRxStartFrm_q2, // 7
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RxBufferEmpty, // 6
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RxBufferFull, // 5
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rxfifo_cnt[4:0] // 4:0
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};
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assign reg4 = { /* 0x64 */
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WriteRxDataToMemory, // 4
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ShiftEndedSync1, // 3
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ShiftEndedSync2, // 2
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ShiftEndedSync3, // 1
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ShiftEndedSync_c1 // 0
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};
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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