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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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//
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// Revision 1.3 2002/01/23 10:28:16 mohor
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// Revision 1.3 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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// Link in the header changed.
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//
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//
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// Revision 1.2 2001/10/19 08:43:51 mohor
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// Revision 1.2 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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Line 79... |
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module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
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module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
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RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
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RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
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TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
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TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
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TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
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TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
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LoadRxStatus, SetPauseTimer
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RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input TxAbortIn;
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input TxAbortIn;
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input TxStartFrmOut;
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input TxStartFrmOut;
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input ReceivedLengthOK;
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input ReceivedLengthOK;
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input ReceivedPacketGood;
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input ReceivedPacketGood;
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input TxUsedDataOutDetected;
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input TxUsedDataOutDetected;
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input LoadRxStatus;
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input RxStatusWriteLatched_sync2;
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input r_PassAll;
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output Pause;
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output Pause;
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output ReceivedPauseFrm;
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output ReceivedPauseFrm;
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output AddressOK;
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output AddressOK;
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output SetPauseTimer;
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output SetPauseTimer;
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reg Pause;
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reg Pause;
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reg AddressOK; // Multicast or unicast address detected
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reg AddressOK; // Multicast or unicast address detected
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reg TypeLengthOK; // Type/Length field contains 0x8808
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reg TypeLengthOK; // Type/Length field contains 0x8808
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reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
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reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
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reg OpCodeOK; // PAUSE opcode detected (0x0001)
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reg OpCodeOK; // PAUSE opcode detected (0x0001)
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always @ (posedge MRxClk or posedge RxReset )
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always @ (posedge MRxClk or posedge RxReset )
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begin
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begin
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if(RxReset)
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if(RxReset)
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OpCodeOK <= #Tp 1'b0;
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OpCodeOK <= #Tp 1'b0;
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else
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else
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if(RxStartFrm)
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if(ByteCntEq16)
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OpCodeOK <= #Tp 1'b0;
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OpCodeOK <= #Tp 1'b0;
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else
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else
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begin
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begin
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if(DetectionWindow & ByteCntEq14)
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if(DetectionWindow & ByteCntEq14)
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OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
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OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
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Line 425... |
always @ (posedge MRxClk or posedge RxReset)
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always @ (posedge MRxClk or posedge RxReset)
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begin
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begin
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if(RxReset)
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if(RxReset)
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ReceivedPauseFrm <=#Tp 1'b0;
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ReceivedPauseFrm <=#Tp 1'b0;
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else
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else
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if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
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ReceivedPauseFrm <=#Tp 1'b0;
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else
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if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
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if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
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ReceivedPauseFrm <=#Tp 1'b1;
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ReceivedPauseFrm <=#Tp 1'b1;
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else
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if(RxStartFrm)
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ReceivedPauseFrm <=#Tp 1'b0;
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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