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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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entity BoothDatapath is
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entity BoothDatapath is
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generic(
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size: integer := 4
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);
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port(
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port(
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clock :in std_logic;
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clock :in std_logic;
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reset :in std_logic;
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reset :in std_logic;
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load :in std_logic;
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load :in std_logic;
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shift :in std_logic;
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shift :in std_logic;
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X : in std_logic_vector;
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X : in std_logic_vector(size-1 downto 0);
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Y : in std_logic_vector;
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Y : in std_logic_vector(size-1 downto 0);
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P : out std_logic_vector);
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P : out std_logic_vector(2*size-1 downto 0));
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end BoothDatapath;
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end BoothDatapath;
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architecture Behavioral of BoothDatapath is
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architecture Behavioral of BoothDatapath is
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component Regeister is
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component Regeister is
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generic (
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size: integer := 4
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);
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port(
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port(
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clock :in std_logic;
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clock :in std_logic;
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enable :in std_logic;
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enable :in std_logic;
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reset :in std_logic;
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reset :in std_logic;
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din :in std_logic_vector;
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din :in std_logic_vector(size-1 downto 0);
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dout :out std_logic_vector);
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dout :out std_logic_vector(size-1 downto 0));
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end component;
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end component;
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component LeftShiftReg is
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component LeftShiftReg is
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generic(
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size : integer:= 4
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);
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port(
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port(
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clock :in std_logic;
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clock :in std_logic;
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enable :in std_logic;
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enable :in std_logic;
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shift :in std_logic;
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shift :in std_logic;
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din :in std_logic_vector;
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din :in std_logic_vector(size-1 downto 0);
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dout :out std_logic_vector);
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dout :out std_logic_vector(size-1 downto 0));
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end component;
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end component;
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component RightShiftReg is
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component RightShiftReg is
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generic(
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size : integer := 4
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);
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port(
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port(
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clock : in std_logic;
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clock : in std_logic;
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enable : in std_logic;
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enable : in std_logic;
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shift : in std_logic;
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shift : in std_logic;
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din : in std_logic_vector;
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din :in std_logic_vector(size-1 downto 0);
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dout : out std_logic_vector(1 downto 0));
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dout : out std_logic_vector(1 downto 0));
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end component;
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end component;
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component BoothEncoder is
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component BoothEncoder is
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port(
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port(
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input1 : in std_logic;
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input1 : in std_logic;
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product : out std_logic
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product : out std_logic
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);
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);
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end component;
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end component;
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component Alu is
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component Alu is
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generic(
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size : integer:= 4
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);
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port(
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port(
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A : in std_logic_vector;
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A : in std_logic_vector(size-1 downto 0);
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B : in std_logic_vector;
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B : in std_logic_vector(size-1 downto 0);
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op : in std_logic;
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op : in std_logic;
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S : out std_logic_vector);
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S : out std_logic_vector(size-1 downto 0));
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end component;
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end component;
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component Ander is
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component Ander is
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generic(
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size : integer:= 4
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);
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port(
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port(
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input1 : in std_logic;
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input1 : in std_logic;
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input2 : in std_logic_vector;
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input2 : in std_logic_vector(size-1 downto 0);
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result : out std_logic_vector);
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result : out std_logic_vector(size-1 downto 0));
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end component;
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end component;
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signal sign_extended_x,andout,alu_out,p_out,X_reg_dout: std_logic_vector(2*X'length -1 downto 0);
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signal sign_extended_x,andout,alu_out,p_out,X_reg_dout: std_logic_vector(2*X'length -1 downto 0);
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signal lessTwoBits : std_logic_vector(1 downto 0);
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signal lessTwoBits : std_logic_vector(1 downto 0);
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signal operator,product : std_logic;
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signal operator,product : std_logic;
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signal Y_concat_zero : std_logic_vector(y'length downto 0);
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signal Y_concat_zero : std_logic_vector(y'length downto 0);
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input0=>lessTwoBits(0),
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input0=>lessTwoBits(0),
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operator => operator,
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operator => operator,
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product => product);
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product => product);
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Y_REG : RightShiftReg
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Y_REG : RightShiftReg
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generic map(size => size+1)
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port map(
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port map(
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clock => clock,
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clock => clock,
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enable => load,
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enable => load,
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shift =>shift,
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shift =>shift,
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din => Y_concat_zero,
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din => Y_concat_zero,
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dout => lessTwoBits);
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dout => lessTwoBits);
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X_REG : LeftShiftReg
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X_REG : LeftShiftReg
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generic map(size => 2*size)
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port map(
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port map(
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clock => clock,
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clock => clock,
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enable => load,
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enable => load,
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shift => shift,
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shift => shift,
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din => sign_extended_x,
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din => sign_extended_x,
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dout => X_reg_dout);
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dout => X_reg_dout);
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ANDing : Ander
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ANDing : Ander
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generic map(size => 2*size)
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port map(
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port map(
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input1 => product,
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input1 => product,
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input2 => X_reg_dout,
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input2 => X_reg_dout,
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result => AndOut);
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result => AndOut);
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Add_Sub : ALU
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Add_Sub : ALU
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generic map(size => 2*size)
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port map(
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port map(
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A => P_out,
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A => P_out,
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B => AndOut,
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B => AndOut,
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op => operator,
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op => operator,
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S => ALU_Out);
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S => ALU_Out);
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P_REG : Regeister
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P_REG : Regeister
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generic map(size => 2*size)
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port map(
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port map(
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clock => clock,
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clock => clock,
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enable => shift,
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enable => shift,
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reset => reset,
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reset => reset,
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din => ALU_Out,
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din => ALU_Out,
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