Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2003/10/02 18:54:35 simons
|
|
// GPIO signals muxed with other peripherals, higland_board fixed.
|
|
//
|
|
// Revision 1.1.1.1 2003/06/24 09:09:23 simons
|
|
// This files were moved here from toplevel folder.
|
|
//
|
|
// Revision 1.1.1.1 2003/06/11 18:51:13 simons
|
|
// Initial import.
|
|
//
|
|
// Revision 1.5 2002/11/11 21:36:28 lampret
|
|
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
|
|
//
|
// Revision 1.4 2002/05/06 18:25:31 lampret
|
// Revision 1.4 2002/05/06 18:25:31 lampret
|
// negedge flops are enabled by default.
|
// negedge flops are enabled by default.
|
//
|
//
|
// Revision 1.3 2001/12/25 17:12:35 lampret
|
// Revision 1.3 2001/12/25 17:12:35 lampret
|
// Added RGPIO_INTS.
|
// Added RGPIO_INTS.
|
Line 77... |
Line 89... |
// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are
|
// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are
|
// required, use several instances of GPIO IP core.
|
// required, use several instances of GPIO IP core.
|
//
|
//
|
// Default is 16.
|
// Default is 16.
|
//
|
//
|
`define GPIO_IOS 16
|
`define GPIO_IOS 31
|
|
|
|
|
//
|
//
|
// Undefine this one if you don't want to remove GPIO block from your design
|
// Undefine this one if you don't want to remove GPIO block from your design
|
// but you also don't need it. When it is undefined, all GPIO ports still
|
// but you also don't need it. When it is undefined, all GPIO ports still
|
// remain valid and the core can be synthesized however internally there is
|
// remain valid and the core can be synthesized however internally there is
|
Line 159... |
Line 172... |
// not defined, err_o is asserted whenever 8- or 16-bit access is made.
|
// not defined, err_o is asserted whenever 8- or 16-bit access is made.
|
// Undefine it if you need to save some area.
|
// Undefine it if you need to save some area.
|
//
|
//
|
// By default it is defined.
|
// By default it is defined.
|
//
|
//
|
`define GPIO_STRICT_32BIT_ACCESS
|
//`define GPIO_STRICT_32BIT_ACCESS
|
|
//
|
|
`ifndef GPIO_STRICT_32BIT_ACCESS
|
|
// added by gorand :
|
|
// if GPIO_STRICT_32BIT_ACCESS is not defined,
|
|
// depending on number of gpio I/O lines, the following are defined :
|
|
// if the number of I/O lines is in range 1-8, GPIO_WB_BYTES1 is defined,
|
|
// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined,
|
|
// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined,
|
|
// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined,
|
|
|
|
`define GPIO_WB_BYTES4
|
|
`endif
|
|
|
//
|
//
|
// WISHBONE address bits used for full decoding of GPIO registers.
|
// WISHBONE address bits used for full decoding of GPIO registers.
|
//
|
//
|
`define GPIO_ADDRHH 6
|
`define GPIO_ADDRHH 6
|