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-------------------------------------------------------------------------------
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-- WISHBONE DATASHEET
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-- WISHBONE SoC Architecture Specification, Revision B.3
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--
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-- General Description : graphical LCD interface for KS0108b controllers
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--
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-- Supported Cycles : SLAVE, READ/WRITE
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--
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-- Data Port Size : 8-bit
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-- Data Port Granularity : 8-bit
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-- Data Port Max Operand Size : 8-bit
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-- Data Transfer Ordering : Big endian and/or little endian
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-- Data Transfer Sequence : Undefined
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--
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-- Supported Signal List
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-- Signal Name WISHBONE Equiv
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-- ACK_O ACK_O
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-- CLK_I CLK_I
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-- DAT_I(7 downto 0) DAT_I()
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-- DAT_O(7 downto 0) DAT_O()
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-- RST_I RST_I
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-- STB_I STB_I
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-- WE_I WE_I
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-- D/I_F TGD(0)
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-- CS1 TGD(1)
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-- CS2 TGD(2)
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity graphical_lcd is
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port (
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-- LCD interface
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E : out std_logic; -- enable signal
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R_W : out std_logic; -- Read High / Write Low
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CS1 : out std_logic; -- CS1
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CS2 : out std_logic; -- CS2
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D_I : out std_logic; -- data high / instruction low
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DB : inout std_logic_vector(7 downto 0); -- data byte
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-- Wishbone interface
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CLK_I : in std_logic; -- The Sytem Clock
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RST_I : in std_logic; -- Async. Reset
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DAT_I : in std_logic_vector(7 downto 0);
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DAT_O : out std_logic_vector(7 downto 0);
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ACK_O : out std_logic;
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STB_I : in std_logic;
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WE_I : in std_logic;
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TGD_I : in std_logic_vector(2 downto 0));
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end graphical_lcd;
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-------------------------------------------------------------------------------
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-- ARCHITECTURE
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-------------------------------------------------------------------------------
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architecture ks0108b of graphical_lcd is
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type state is (IDLE, WR_SETUP, WR_HOLD, RD_SETUP, RD_HOLD, ACK);
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signal DB_en : std_logic := '0'; -- enable the DB lines
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signal cur_state : state := idle; -- current state
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signal data_in : std_logic_vector(7 downto 0) := "XXXXXXXX";
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signal data_out : std_logic_vector(7 downto 0) := "XXXXXXXX";
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signal e_cnt : std_logic_vector(7 downto 0);
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signal e_int : std_logic;
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signal e_en : std_logic;
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begin -- behavioral
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-----------------------------------------------------------------------------
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-- WISHBONE STUFF
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-----------------------------------------------------------------------------
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DAT_O <= data_out;
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ACK_O <= '1' when (cur_state = ACK) else
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'0';
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wishbone_dat_in: process (CLK_I, RST_I)
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begin -- process wishbone_dat_in
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if RST_I = '1' then -- asynchronous reset
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data_in <= "00000000";
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elsif CLK_I'event and CLK_I = '1' then -- rising clock edge
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if (STB_I = '1') and (WE_I = '1') then
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data_in <= DAT_I;
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end if;
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else
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data_in <= data_in;
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end if;
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end process wishbone_dat_in;
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-----------------------------------------------------------------------------
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-- LCD STUFF
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-----------------------------------------------------------------------------
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E <= e_int;
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D_I <= TGD_I(0);
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CS1 <= TGD_I(1);
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CS2 <= TGD_I(2);
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R_W <= '0' when (cur_state = WR_SETUP) or (cur_state = WR_HOLD) else
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'1' when (cur_state = RD_SETUP) or (cur_state = RD_HOLD) else
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'1';
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e_en <= '1' when (cur_state = WR_SETUP) or (cur_state = WR_HOLD) else
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'1' when (cur_state = RD_SETUP) or (cur_state = RD_HOLD) else
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'0';
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DB <= data_in when (cur_state = WR_SETUP) or (cur_state = WR_HOLD) else
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"ZZZZZZZZ";
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data_out <= DB when (e_int'event) and (e_int = '0') else
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data_out;
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-- purpose: creates the enable signal which is at least a 500ns period clock
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e_gen: process (CLK_I, RST_I, e_en)
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begin -- process e_gen
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if (RST_I = '1') or (e_en = '0') then
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e_cnt <= "00000000";
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e_int <= '0';
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elsif CLK_I'event and CLK_I = '1' then
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e_cnt <= e_cnt + 1;
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if (e_cnt = X"19") then
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e_cnt <= "00000000";
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e_int <= not e_int;
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end if;
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end if;
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end process e_gen;
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state_machine: process (CLK_I, RST_I)
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begin -- process state_machine
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if RST_I = '1' then
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cur_state <= idle;
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elsif CLK_I'event and CLK_I = '1' then
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case cur_state is
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when IDLE =>
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if (STB_I = '1') then
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if (WE_I = '1') then
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cur_state <= WR_SETUP;
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else
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cur_state <= RD_SETUP;
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end if;
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else
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cur_state <= IDLE;
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end if;
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when WR_SETUP =>
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if (e_int = '1') then
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cur_state <= WR_HOLD;
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else
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cur_state <= WR_SETUP;
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end if;
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when WR_HOLD =>
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if (e_int = '0') and (e_cnt = X"03") then
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cur_state <= ACK;
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else
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cur_state <= WR_HOLD;
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end if;
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when RD_SETUP =>
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if (e_int = '1') then
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cur_state <= RD_HOLD;
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else
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cur_state <= RD_SETUP;
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end if;
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when RD_HOLD =>
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if (e_int = '0') and (e_cnt = X"03") then
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cur_state <= ACK;
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else
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cur_state <= RD_HOLD;
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end if;
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when ACK =>
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if (STB_I = '0') then
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cur_state <= IDLE;
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end if;
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when others => null;
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end case;
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end if;
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end process state_machine;
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end ks0108b;
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