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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-------------------------------------------------------------------------------
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entity graphical_lcd_tb is
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end graphical_lcd_tb;
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-------------------------------------------------------------------------------
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architecture testbench of graphical_lcd_tb is
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component graphical_lcd
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port (
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E : out std_logic;
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R_W : out std_logic;
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CS1 : out std_logic;
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CS2 : out std_logic;
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D_I : out std_logic;
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DB : inout std_logic_vector(7 downto 0);
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CLK_I : in std_logic;
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RST_I : in std_logic;
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DAT_I : in std_logic_vector(7 downto 0);
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DAT_O : out std_logic_vector;
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ACK_O : out std_logic;
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STB_I : in std_logic;
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WE_I : in std_logic;
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TGD_I : in std_logic_vector(2 downto 0));
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end component;
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signal E_i : std_logic;
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signal R_W_i : std_logic;
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signal CS1_i : std_logic;
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signal CS2_i : std_logic;
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signal D_I_i : std_logic;
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signal DB_i : std_logic_vector(7 downto 0);
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signal CLK_I_i : std_logic;
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signal RST_I_i : std_logic;
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signal DAT_I_i : std_logic_vector(7 downto 0);
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signal DAT_O_i : std_logic_vector(7 downto 0);
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signal ACK_O_i : std_logic;
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signal STB_I_i : std_logic;
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signal WE_I_i : std_logic;
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signal TGD_I_i : std_logic_vector(2 downto 0);
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constant clock_period : delay_length := 20 ns;
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begin -- testbench
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-- Unit under test
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UUT: graphical_lcd
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port map (
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E => E_i,
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R_W => R_W_i,
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CS1 => CS1_i,
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CS2 => CS2_i,
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D_I => D_I_i,
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DB => DB_i,
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CLK_I => CLK_I_i,
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RST_I => RST_I_i,
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DAT_I => DAT_I_i,
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DAT_O => DAT_O_i,
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ACK_O => ACK_O_i,
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STB_I => STB_I_i,
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WE_I => WE_I_i,
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TGD_I => TGD_I_i);
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-- Simulate fake data reads
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DB_i <= "ZZZZZZZZ" when R_W_i = '0' else
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"00001111";
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-- Reset driver
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RST_I_i <= '1', '0' after 2.5 * clock_period;
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-- Generate the testbench clock
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clk_gen: process
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begin -- process clk_gen
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CLK_I_i <= '0';
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wait for clock_period/2;
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loop
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CLK_I_i <= '1';
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wait for clock_period/2;
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CLK_I_i <= '0';
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wait for clock_period/2;
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end loop; -- clock_period/2;
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end process clk_gen;
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stimulus: process
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begin -- process stimulus
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wait until RST_I_i = '0';
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wait until CLK_I_i = '1';
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-- Turn the display on
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DAT_I_i <= "00111111";
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TGD_I_i <= "000";
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WE_I_i <= '1';
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wait until CLK_I_i = '1';
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STB_I_i <= '1';
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wait until ACK_O_i = '1';
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wait until CLK_I_i = '1';
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STB_I_i <= '0';
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-- Read until the busy is gone
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wait until CLK_I_i = '1';
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TGD_I_i <= "100";
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WE_I_i <= '0';
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wait until CLK_I_i = '1';
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STB_I_i <= '1';
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wait until ACK_O_i = '1';
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wait until CLK_I_i = '1';
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STB_I_i <= '0';
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-- Send some data
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wait until CLK_I_i = '1';
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DAT_I_i <= "10101100";
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TGD_I_i <= "011";
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WE_I_i <= '1';
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wait until CLK_I_i = '1';
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STB_I_i <= '1';
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wait until ACK_O_i = '1';
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wait until CLK_I_i = '1';
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STB_I_i <= '0';
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wait;
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end process stimulus;
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end testbench;
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