| Line 46... |
Line 46... |
input dist_compl_add,
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input dist_compl_add,
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input any_left_shift_on, right_shift_on, left_shift_on, mult_div_left_shift,
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input any_left_shift_on, right_shift_on, left_shift_on, mult_div_left_shift,
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input sig_digit_on, hc_add_5, mult_on, acc_true_add_gate,
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input sig_digit_on, hc_add_5, mult_on, acc_true_add_gate,
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|
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output tlu_on, early_dist_zero_entry, early_dist_zero_control,
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output tlu_on, early_dist_zero_entry, early_dist_zero_control,
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output reg prog_ped_regen_latch, prog_to_acc_add, prog_add,
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output reg prog_to_acc_add, prog_add,
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output prog_add_d0,
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output prog_add_d0,
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output prog_ped_regen,
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output prog_ped_regen,
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output [0:9] special_digit,
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output [0:9] special_digit,
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output tlu_band_change, dist_blank_gate
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output tlu_band_change, dist_blank_gate, sel_stor_add_gate,
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ontime_dist_add_gate, upper_lower_check
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);
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);
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Distributor zero entry and control gates
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// Distributor zero entry and control gates
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//
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//
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| Line 156... |
Line 157... |
// [124:75] TLU program regeneration control latch 1194 (Fig. 86b). Off with
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// [124:75] TLU program regeneration control latch 1194 (Fig. 86b). Off with
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// same conditions which turn TLU program add latch on. On with the next WP.
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// same conditions which turn TLU program add latch on. On with the next WP.
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// When off, interrupts program register regeneration by blocking the path
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// When off, interrupts program register regeneration by blocking the path
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// between program on time latch outputs and pedistal lines.
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// between program on time latch outputs and pedistal lines.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg prog_ped_regen_latch;
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assign prog_ped_regen = prog_ped_regen_latch; // & ~ap;
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assign prog_ped_regen = prog_ped_regen_latch; // & ~ap;
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|
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always @(posedge bp)
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always @(posedge bp)
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if (rst) begin
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if (rst) begin
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prog_ped_regen_latch <= 0;
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prog_ped_regen_latch <= 0;
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end else if (~prog_add_on_p) begin
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end else if (prog_add_on_p) begin
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prog_ped_regen_latch <= 0;
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prog_ped_regen_latch <= 0;
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end else if (dx) begin
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end else if (dx) begin
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prog_ped_regen_latch <= 1;
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prog_ped_regen_latch <= 1;
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end;
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end;
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| Line 237... |
Line 239... |
| (tlu_carry_d4 & w1)
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| (tlu_carry_d4 & w1)
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| (d5_tlu_carry_no_w0 & s0)
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| (d5_tlu_carry_no_w0 & s0)
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| (d5_tlu_carry_w0 & s1)
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| (d5_tlu_carry_w0 & s1)
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| prog_to_acc_add
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| prog_to_acc_add
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| (acc_minus_sign & compl_adj)
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| (acc_minus_sign & compl_adj)
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| (quot_digit_on & edxl)
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| (quot_digit_on & dxl)
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| (edxl & dist_compl_add)
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| (dxl & dist_compl_add)
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| (~add_1 & any_left_shift_on & ~edxl);
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| (~add_1 & any_left_shift_on & ~dxl);
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wire add_1 = (tlu_carry_d4 & w2)
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wire add_1 = (tlu_carry_d4 & w2)
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| (d5_tlu_carry_no_w0 & s1)
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| (d5_tlu_carry_no_w0 & s1)
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| (d5_tlu_carry_w0 & s2)
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| (d5_tlu_carry_w0 & s2)
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| (edxl & (right_shift_on | left_shift_on | mult_div_left_shift))
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| (dxl & (right_shift_on | left_shift_on | mult_div_left_shift))
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| (dist_compl_add & quot_digit_on & ed0l)
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| (dist_compl_add & quot_digit_on & d0l)
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| sig_digit_on;
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| sig_digit_on;
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wire add_2 = (tlu_carry_d4 & w3)
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wire add_2 = (tlu_carry_d4 & w3)
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| (d5_tlu_carry_no_w0 & s2)
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| (d5_tlu_carry_no_w0 & s2)
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| (d5_tlu_carry_w0 & s3);
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| (d5_tlu_carry_w0 & s3);
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wire add_3 = (tlu_carry_d4 & w4)
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wire add_3 = (tlu_carry_d4 & w4)
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| Line 256... |
Line 258... |
| (d5_tlu_carry_w0 & s4);
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| (d5_tlu_carry_w0 & s4);
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wire add_4 = (tlu_carry_d4 & w5)
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wire add_4 = (tlu_carry_d4 & w5)
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| (d5_tlu_carry_no_w0 & s4);
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| (d5_tlu_carry_no_w0 & s4);
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wire add_5 = (tlu_band_change & d5)
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wire add_5 = (tlu_band_change & d5)
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| (tlu_carry_d4 & w6)
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| (tlu_carry_d4 & w6)
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| (edxl & hc_add_5);
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| (dxl & hc_add_5);
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wire add_6 = (tlu_carry_d4 & w7);
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wire add_6 = (tlu_carry_d4 & w7);
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wire add_7 = (tlu_carry_d4 & w8);
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wire add_7 = (tlu_carry_d4 & w8);
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wire add_8 = (tlu_carry_d4 & w9);
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wire add_8 = (tlu_carry_d4 & w9);
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wire add_9 = (tlu_carry_d4 & w0)
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wire add_9 = (tlu_carry_d4 & w0)
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| (d10u & mult_on & acc_true_add_gate);
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| (d10u & mult_on & acc_true_add_gate);
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| Line 307... |
Line 309... |
// a negative S4, W8, and 9 gate to provide the TLU selected storage add gate
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// a negative S4, W8, and 9 gate to provide the TLU selected storage add gate
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// from the output of cathode follower 1035 and TLU on time distributor add
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// from the output of cathode follower 1035 and TLU on time distributor add
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// gate from cathode follower 1036 for D1 through D10 of each word of the band
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// gate from cathode follower 1036 for D1 through D10 of each word of the band
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// except words 48 and 49.
|
// except words 48 and 49.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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|
assign sel_stor_add_gate = 1'b0;
|
|
assign ontime_dist_add_gate = 1'b0;
|
|
assign upper_lower_check = 1'b0;
|
|
|
endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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