URL
https://opencores.org/ocsvn/klc32/klc32/trunk
[/] [klc32/] [trunk/] [rtl/] [verilog/] [RTS.v] - Diff between revs 2 and 12
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| Rev 2 |
Rev 12 |
| Line 38... |
Line 38... |
else
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else
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usp <= usp + 32'd4 + ir[21:6];
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usp <= usp + 32'd4 + ir[21:6];
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pc <= {dat_i[31:2],2'b00}+{ir[25:22],2'b00};
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pc <= {dat_i[31:2],2'b00}+{ir[25:22],2'b00};
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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else if (err_i) begin
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'b0000;
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vector <= `BUS_ERR_VECTOR;
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state <= TRAP;
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end
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