Line 12... |
Line 12... |
-- This will be work in process or replaced whatever
|
-- This will be work in process or replaced whatever
|
-- project file is needed to control other modules.
|
-- project file is needed to control other modules.
|
--
|
--
|
-- *************************************************************
|
-- *************************************************************
|
-- Distributed under the GNU Lesser General Public License. *
|
-- Distributed under the GNU Lesser General Public License. *
|
-- This can be obtained from “www.gnu.org”. *
|
-- This can be obtained from www.gnu.org. *
|
-- *************************************************************
|
-- *************************************************************
|
-- This program is free software: you can redistribute it and/or modify
|
-- This program is free software: you can redistribute it and/or modify
|
-- it under the terms of the GNU General Public License as published by
|
-- it under the terms of the GNU General Public License as published by
|
-- the Free Software Foundation, either version 3 of the License, or
|
-- the Free Software Foundation, either version 3 of the License, or
|
-- (at your option) any later version.
|
-- (at your option) any later version.
|
Line 48... |
Line 48... |
-- u1101 : out std_logic;
|
-- u1101 : out std_logic;
|
-- u801 : out std_logic;
|
-- u801 : out std_logic;
|
-- u701 : out std_logic;
|
-- u701 : out std_logic;
|
u601 : out std_logic;
|
u601 : out std_logic;
|
rst_pin : in std_logic;
|
rst_pin : in std_logic;
|
irq_pin : in std_logic;
|
-- irq_pin : in std_logic;
|
nmi_pin : in std_logic;
|
-- nmi_pin : in std_logic;
|
RX_pin : in std_logic;
|
RX_pin : in std_logic;
|
-- PG_pin : in std_logic;
|
-- PG_pin : in std_logic;
|
TX_pin : out std_logic;
|
TX_pin : out std_logic;
|
Pwr_on_pin : out std_logic
|
Pwr_on_pin : out std_logic
|
);
|
);
|
Line 136... |
Line 136... |
signal add : unsigned(15 downto 0);
|
signal add : unsigned(15 downto 0);
|
signal proc_rd_dat, rom_dat, ram_dat, data_wr : unsigned(7 downto 0);
|
signal proc_rd_dat, rom_dat, ram_dat, data_wr : unsigned(7 downto 0);
|
signal rx_dat : unsigned(7 downto 0);
|
signal rx_dat : unsigned(7 downto 0);
|
signal proc_write : std_logic;
|
signal proc_write : std_logic;
|
signal one, RX_rdy, csw_usart, csr_usart, tx_rdy : std_logic;
|
signal one, RX_rdy, csw_usart, csr_usart, tx_rdy : std_logic;
|
-- signal cycle_mark : std_logic
|
|
signal rst_bar : std_logic;
|
signal rst_bar : std_logic;
|
signal ram_write : std_logic;
|
signal ram_write : std_logic;
|
|
|
--signal clk : std_logic;
|
|
--signal clk_pin : std_logic;
|
|
signal counter : unsigned(3 downto 0);
|
signal counter : unsigned(3 downto 0);
|
|
|
|
signal nmi_pin, irq_pin : std_logic;
|
|
|
-- I/O ports
|
-- I/O ports
|
|
|
constant led_port : unsigned (15 downto 0) := x"4007";
|
constant led_port : unsigned (15 downto 0) := x"4007";
|
constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output
|
constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output
|
constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here
|
constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here
|
constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting
|
constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting
|
|
|
|
constant Kirq : unsigned (15 downto 0) := X"4002"; --interrpt testing only
|
|
constant Knmi : unsigned (15 downto 0) := x"4003";
|
|
|
begin
|
begin
|
|
|
U1 : P65C02 port map(
|
U1 : P65C02 port map(
|
reset => rst_pin,
|
reset => rst_pin,
|
Clock => clk_pin,
|
Clock => clk_pin,
|
Line 207... |
Line 209... |
-- Reset => rst_bar,
|
-- Reset => rst_bar,
|
-- Clock => clk_pin,
|
-- Clock => clk_pin,
|
-- WE => ram_write,
|
-- WE => ram_write,
|
-- address(9 downto 0) => std_logic_vector(Address(9 downto 0)),
|
-- address(9 downto 0) => std_logic_vector(Address(9 downto 0)),
|
-- Data => std_logic_vector(data_wr),
|
-- Data => std_logic_vector(data_wr),
|
-- unsigned(Q) => ram_dat, ClockEn => one);
|
-- unsigned(Q) => ram_dat
|
|
-- ClockEn => one);
|
|
|
one <= '1';
|
one <= '1';
|
rst_bar <= not rst_pin;
|
rst_bar <= not rst_pin;
|
one <= '1';
|
|
|
ram_write <= proc_write and not address(15) and not address(14);
|
|
|
|
--one <= '1';
|
--u601 <= cycle_mark;
|
--u601 <= cycle_mark;
|
|
|
|
|
|
|
mux_add : process(rst_pin, clk_pin)
|
mux_add : process(rst_pin, clk_pin)
|
Line 225... |
Line 231... |
elsif rising_edge(clk_pin) then
|
elsif rising_edge(clk_pin) then
|
add <= address;
|
add <= address;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
ram_address : process (proc_write, address(15 downto 14))
|
--ram_address : process (proc_write, address(15 downto 14))
|
begin
|
--begin
|
if proc_write = '1' and address(15 downto 14) = "00" then
|
-- if proc_write = '1' and address(15 downto 14) = "00" then
|
ram_write <= '1';
|
-- ram_write <= '1';
|
else
|
-- else
|
ram_write <= '0';
|
-- ram_write <= '0';
|
end if;
|
-- end if;
|
end process;
|
--end process;
|
|
|
|
|
|
|
|
|
-- ===================================================================
|
-- ===================================================================
|
Line 273... |
Line 279... |
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
|
|
relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin)
|
--relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin)
|
begin
|
--begin
|
if rst_pin = '0' then
|
--if rst_pin = '0' then
|
Pwr_on_pin <= '0';
|
-- Pwr_on_pin <= '0';
|
elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then
|
-- elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then
|
Pwr_on_pin <= data_wr(7);
|
-- Pwr_on_pin <= data_wr(7);
|
end if;
|
--end if;
|
end process;
|
--end process;
|
|
|
|
--irq : process (rst_pin, proc_write, address, data_wr(0), clk_pin)
|
|
--begin
|
|
--if rst_pin = '0' then
|
|
-- irq_pin <= '1';
|
|
-- elsif rising_edge(clk_pin) then
|
|
-- if address = Kirq and proc_write = '1' then
|
|
-- irq_pin <= data_wr(0); --set and hold bit 0
|
|
-- end if;
|
|
--end if;
|
|
--end process;
|
|
|
|
--nmi : process (rst_pin, proc_write, address, data_wr(0), clk_pin)
|
|
--begin
|
|
--if rst_pin = '0' then
|
|
-- nmi_pin <= '1';
|
|
-- elsif rising_edge(clk_pin) then
|
|
--
|
|
-- if address = Knmi and proc_write = '1' then
|
|
-- nmi_pin <= data_wr(0); --set and hold bit 0
|
|
-- end if;
|
|
--end if;
|
|
--end process;
|
|
|
end structure;
|
end structure;
|
|
|
No newline at end of file
|
No newline at end of file
|