| Line 81... |
Line 81... |
signal ramwe_d4 : STD_LOGIC;
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signal ramwe_d4 : STD_LOGIC;
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signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d5 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d6 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal wmemsel_d1 : STD_LOGIC;
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signal wmemsel_d1 : STD_LOGIC;
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signal wmemsel_d2 : STD_LOGIC;
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signal wmemsel_d2 : STD_LOGIC;
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signal wmemsel_d3 : STD_LOGIC;
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signal wmemsel_d3 : STD_LOGIC;
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signal wmemsel_d4 : STD_LOGIC;
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signal wmemsel_d4 : STD_LOGIC;
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signal wmemsel_d5 : STD_LOGIC;
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signal wmemsel_d6 : STD_LOGIC;
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signal romedatao_d1 : T_ROM1DATAO;
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signal romedatao_d1 : T_ROM1DATAO;
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signal romodatao_d1 : T_ROM1DATAO;
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signal romodatao_d1 : T_ROM1DATAO;
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signal romedatao_d2 : T_ROM1DATAO;
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signal romedatao_d2 : T_ROM1DATAO;
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signal romodatao_d2 : T_ROM1DATAO;
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signal romodatao_d2 : T_ROM1DATAO;
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signal romedatao_d3 : T_ROM1DATAO;
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signal romedatao_d3 : T_ROM1DATAO;
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Line 100... |
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
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signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
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signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
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signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
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signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
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signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
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signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
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signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
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signal fpr_out : STD_LOGIC_VECTOR(DA_W-12-1 downto 0);
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component FinitePrecRndNrst is
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generic
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(
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C_IN_SZ : natural := 37;
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C_OUT_SZ : natural := 16;
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C_FRAC_SZ : natural := 15
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);
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port (
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CLK : in std_logic;
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RST : in std_logic;
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datain : in STD_LOGIC_VECTOR(C_IN_SZ-1 downto 0);
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dataval : in std_logic;
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dataout : out STD_LOGIC_VECTOR(C_OUT_SZ-1 downto 0);
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clip_inc : out std_logic;
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dval_out : out std_logic
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);
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end component;
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begin
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begin
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ramwaddro <= ramwaddro_d4;
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ramwaddro <= ramwaddro_d6;
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ramwe <= ramwe_d4;
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--ramwe <= ramwe_d4;
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ramdatai <= dcto_4(DA_W-1 downto 12);
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--ramdatai <= dcto_4(DA_W-1 downto 12);
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wmemsel <= wmemsel_d4;
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wmemsel <= wmemsel_d4;
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odv <= ramwe_d4;
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dcto <= STD_LOGIC_VECTOR(RESIZE(SIGNED(fpr_out),12));
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ramdatai <= fpr_out;
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U_FinitePrecRndNrst : FinitePrecRndNrst
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generic map(
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C_IN_SZ => DA_W,
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C_OUT_SZ => DA_W-12,
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C_FRAC_SZ => 12
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)
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port map(
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CLK => clk,
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RST => rst,
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datain => dcto_4,
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dataval => ramwe_d4,
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dataout => fpr_out,
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clip_inc => open,
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dval_out => ramwe
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);
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process(clk,rst)
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process(clk,rst)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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inpcnt_reg <= (others => '0');
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inpcnt_reg <= (others => '0');
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latchbuf_reg <= (others => (others => '0'));
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latchbuf_reg <= (others => (others => '0'));
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| Line 222... |
Line 270... |
ramwe_d4 <= ramwe_d3;
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ramwe_d4 <= ramwe_d3;
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ramwaddro_d1 <= ramwaddro_s;
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ramwaddro_d1 <= ramwaddro_s;
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ramwaddro_d2 <= ramwaddro_d1;
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ramwaddro_d2 <= ramwaddro_d1;
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ramwaddro_d3 <= ramwaddro_d2;
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ramwaddro_d3 <= ramwaddro_d2;
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ramwaddro_d4 <= ramwaddro_d3;
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ramwaddro_d4 <= ramwaddro_d3;
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ramwaddro_d5 <= ramwaddro_d4;
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ramwaddro_d6 <= ramwaddro_d5;
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wmemsel_d1 <= wmemsel_reg;
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wmemsel_d1 <= wmemsel_reg;
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wmemsel_d2 <= wmemsel_d1;
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wmemsel_d2 <= wmemsel_d1;
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wmemsel_d3 <= wmemsel_d2;
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wmemsel_d3 <= wmemsel_d2;
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wmemsel_d4 <= wmemsel_d3;
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wmemsel_d4 <= wmemsel_d3;
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wmemsel_d5 <= wmemsel_d4;
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wmemsel_d6 <= wmemsel_d5;
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if even_not_odd = '0' then
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if even_not_odd = '0' then
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dcto_1 <= STD_LOGIC_VECTOR(RESIZE
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dcto_1 <= STD_LOGIC_VECTOR(RESIZE
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(RESIZE(SIGNED(romedatao(0)),DA_W) +
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(RESIZE(SIGNED(romedatao(0)),DA_W) +
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(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
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(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
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