Line 53... |
Line 53... |
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entity operand_ram is
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entity operand_ram is
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port( -- write_operand_ack voorzien?
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port( -- write_operand_ack voorzien?
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-- global ports
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-- global ports
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clk : in std_logic;
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collision : out std_logic;
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collision : out std_logic;
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-- bus side connections (32-bit serial)
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-- bus side connections (32-bit serial)
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bus_clk : in std_logic;
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operand_addr : in std_logic_vector(5 downto 0);
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operand_addr : in std_logic_vector(5 downto 0);
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operand_in : in std_logic_vector(31 downto 0);
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operand_in : in std_logic_vector(31 downto 0);
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operand_in_sel : in std_logic_vector(1 downto 0);
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operand_in_sel : in std_logic_vector(1 downto 0);
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result_out : out std_logic_vector(31 downto 0);
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result_out : out std_logic_vector(31 downto 0);
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write_operand : in std_logic;
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write_operand : in std_logic;
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-- multiplier side connections (1536 bit parallel)
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-- multiplier side connections (1536 bit parallel)
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core_clk : in std_logic;
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result_dest_op : in std_logic_vector(1 downto 0);
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result_dest_op : in std_logic_vector(1 downto 0);
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operand_out : out std_logic_vector(1535 downto 0);
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operand_out : out std_logic_vector(1535 downto 0);
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operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
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operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
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write_result : in std_logic;
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write_result : in std_logic;
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result_in : in std_logic_vector(1535 downto 0)
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result_in : in std_logic_vector(1535 downto 0)
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Line 80... |
signal part_enable : std_logic_vector(3 downto 0);
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signal part_enable : std_logic_vector(3 downto 0);
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signal wea : std_logic_vector(3 downto 0);
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signal wea : std_logic_vector(3 downto 0);
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signal write_operand_i : std_logic;
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signal write_operand_i : std_logic;
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-- port b signals
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-- port b signals
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signal addrb : std_logic_vector(5 downto 0);
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signal addrb : std_logic_vector(1 downto 0);
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signal web : std_logic_vector(0 downto 0);
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signal web : std_logic_vector(0 downto 0);
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signal doutb0 : std_logic_vector(31 downto 0);
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signal douta0 : std_logic_vector(31 downto 0);
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signal doutb1 : std_logic_vector(31 downto 0);
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signal douta1 : std_logic_vector(31 downto 0);
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signal doutb2 : std_logic_vector(31 downto 0);
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signal douta2 : std_logic_vector(31 downto 0);
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begin
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begin
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-- WARNING: Very Important!
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-- WARNING: Very Important!
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-- wea & web signals must never be high at the same time !!
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-- wea & web signals must never be high at the same time !!
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Line 98... |
collision <= write_operand and write_result;
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collision <= write_operand and write_result;
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-- the dual port ram has a depth of 4 (each layer contains an operand)
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-- the dual port ram has a depth of 4 (each layer contains an operand)
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-- result is always stored in position 3
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-- result is always stored in position 3
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-- doutb is always result
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-- doutb is always result
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with write_operand_i select
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with write_result select
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addra <= operand_in_sel & operand_addr(3 downto 0) when '1',
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addrb <= result_dest_op when '1',
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operand_out_sel & "0000" when others;
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operand_out_sel when others;
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with operand_addr(5 downto 4) select
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with operand_addr(5 downto 4) select
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part_enable <= "0001" when "00",
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part_enable <= "0001" when "00",
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"0010" when "01",
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"0010" when "01",
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"0100" when "10",
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"0100" when "10",
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"1000" when others;
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"1000" when others;
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with write_operand_i select
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with write_operand select
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wea <= part_enable when '1',
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wea <= part_enable when '1',
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"0000" when others;
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"0000" when others;
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-- we can only read back from the result (stored in result_dest_op)
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addra <= operand_in_sel & operand_addr(3 downto 0);
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addrb <= result_dest_op & operand_addr(3 downto 0);
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with operand_addr(5 downto 4) select
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with operand_addr(5 downto 4) select
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result_out <= doutb0 when "00",
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result_out <= douta0 when "00",
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doutb1 when "01",
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douta1 when "01",
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doutb2 when others;
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douta2 when others;
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-- 3 instances of a dual port ram to store the parts of the operand
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-- 3 instances of a dual port ram to store the parts of the operand
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op_0 : operand_dp
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op_0 : operand_dp
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port map (
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port map (
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clka => clk,
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clka => bus_clk,
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wea => wea(0 downto 0),
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wea => wea(0 downto 0),
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addra => addra,
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addra => addra,
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dina => operand_in,
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dina => operand_in,
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douta => operand_out(511 downto 0),
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douta => douta0,
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clkb => clk,
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clkb => core_clk,
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web => web,
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web => web,
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addrb => addrb,
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addrb => addrb,
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dinb => result_in(511 downto 0),
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dinb => result_in(511 downto 0),
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doutb => doutb0
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doutb => operand_out(511 downto 0)
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);
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);
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op_1 : operand_dp
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op_1 : operand_dp
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port map (
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port map (
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clka => clk,
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clka => bus_clk,
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wea => wea(1 downto 1),
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wea => wea(1 downto 1),
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addra => addra,
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addra => addra,
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dina => operand_in,
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dina => operand_in,
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douta => operand_out(1023 downto 512),
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douta => douta1,
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clkb => clk,
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clkb => core_clk,
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web => web,
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web => web,
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addrb => addrb,
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addrb => addrb,
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dinb => result_in(1023 downto 512),
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dinb => result_in(1023 downto 512),
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doutb => doutb1
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doutb => operand_out(1023 downto 512)
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);
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);
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op_2 : operand_dp
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op_2 : operand_dp
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port map (
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port map (
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clka => clk,
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clka => bus_clk,
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wea => wea(2 downto 2),
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wea => wea(2 downto 2),
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addra => addra,
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addra => addra,
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dina => operand_in,
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dina => operand_in,
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douta => operand_out(1535 downto 1024),
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douta => douta2,
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clkb => clk,
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clkb => core_clk,
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web => web,
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web => web,
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addrb => addrb,
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addrb => addrb,
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dinb => result_in(1535 downto 1024),
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dinb => result_in(1535 downto 1024),
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doutb => doutb2
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doutb => operand_out(1535 downto 1024)
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);
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);
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end Behavioral;
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end Behavioral;
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No newline at end of file
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