| Line 94... |
Line 94... |
reg r_pipe;
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reg r_pipe;
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`endif
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`endif
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wire [4:0] w_op;
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wire [4:0] w_op;
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wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
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wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop,
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w_mpy;
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wire [4:0] w_dcdR, w_dcdB, w_dcdA;
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wire [4:0] w_dcdR, w_dcdB, w_dcdA;
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wire w_dcdR_pc, w_dcdR_cc;
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wire w_dcdR_pc, w_dcdR_cc;
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wire w_dcdA_pc, w_dcdA_cc;
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wire w_dcdA_pc, w_dcdA_cc;
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wire w_dcdB_pc, w_dcdB_cc;
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wire w_dcdB_pc, w_dcdB_cc;
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wire [3:0] w_cond;
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wire [3:0] w_cond;
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wire w_wF, w_dcdM, w_dcdDV, w_dcdFP;
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wire w_wF, w_dcdM, w_dcdDV, w_dcdFP, w_sto;
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wire w_wR, w_rA, w_rB, w_wR_n;
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wire w_wR, w_rA, w_rB, w_wR_n;
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wire w_ljmp, w_ljmp_dly;
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wire w_ljmp, w_ljmp_dly;
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wire [31:0] iword;
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wire [31:0] iword;
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| Line 131... |
Line 132... |
assign w_mov = (w_op == 5'h0f);
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assign w_mov = (w_op == 5'h0f);
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assign w_ldi = (w_op[4:1] == 4'hb);
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assign w_ldi = (w_op[4:1] == 4'hb);
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assign w_brev = (w_op == 5'hc);
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assign w_brev = (w_op == 5'hc);
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assign w_cmptst = (w_op[4:1] == 4'h8);
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assign w_cmptst = (w_op[4:1] == 4'h8);
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assign w_ldilo = (w_op[4:0] == 5'h9);
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assign w_ldilo = (w_op[4:0] == 5'h9);
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assign w_mpy = ((w_op[4:1]==4'h5)||(w_op[4:0]==5'h08));
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assign w_ALU = (~w_op[4]);
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assign w_ALU = (~w_op[4]);
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// 4 LUTs
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// 4 LUTs
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//
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//
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// Two parts to the result register: the register set, given for
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// Two parts to the result register: the register set, given for
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// moves in i_word[18] but only for the supervisor, and the other
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// moves in iword[18] but only for the supervisor, and the other
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// four bits encoded in the instruction.
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// four bits encoded in the instruction.
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//
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//
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`ifdef OPT_NO_USERMODE
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assign w_dcdR = { 1'b0, iword[30:27] };
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`else
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assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
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assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
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iword[30:27] };
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iword[30:27] };
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`endif
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// 2 LUTs
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// 2 LUTs
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//
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//
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// If the result register is either CC or PC, and this would otherwise
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// If the result register is either CC or PC, and this would otherwise
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// be a floating point instruction with floating point opcode of 0,
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// be a floating point instruction with floating point opcode of 0,
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// then this is a NOOP.
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// then this is a NOOP.
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assign w_noop = (w_op[4:0] == 5'h18)&&(
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assign w_noop = (w_op[4:0] == 5'h18)&&(
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((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
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((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
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||(IMPLEMENT_FPU==0));
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||(IMPLEMENT_FPU==0));
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`ifdef OPT_NO_USERMODE
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assign w_dcdB = { 1'b0, iword[17:14] };
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`else
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// 4 LUTs
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// 4 LUTs
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assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
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assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
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iword[17:14] };
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iword[17:14] };
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`endif
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// 0 LUTs
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// 0 LUTs
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assign w_dcdA = w_dcdR;
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assign w_dcdA = w_dcdR;
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// 2 LUTs, 1 delay each
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// 2 LUTs, 1 delay each
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assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
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assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
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| Line 178... |
Line 188... |
1'b0,iword[20:19]}
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1'b0,iword[20:19]}
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: { (iword[21:19]==3'h0), iword[21:19] };
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: { (iword[21:19]==3'h0), iword[21:19] };
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// 1 LUT
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// 1 LUT
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assign w_dcdM = (w_op[4:1] == 4'h9);
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assign w_dcdM = (w_op[4:1] == 4'h9);
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assign w_sto = (w_dcdM)&&(w_op[0]);
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// 1 LUT
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// 1 LUT
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assign w_dcdDV = (w_op[4:1] == 4'ha);
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assign w_dcdDV = (w_op[4:1] == 4'ha);
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// 1 LUT
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// 1 LUT
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assign w_dcdFP = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7);
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assign w_dcdFP = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7);
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// 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before)
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// 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before)
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| Line 189... |
Line 200... |
assign w_rA = (w_dcdFP)
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assign w_rA = (w_dcdFP)
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// Divide's read A
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// Divide's read A
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||(w_dcdDV)
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||(w_dcdDV)
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// ALU read's A, unless it's a MOV to A
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// ALU read's A, unless it's a MOV to A
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// This includes LDIHI/LDILO
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// This includes LDIHI/LDILO
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||((~w_op[4])&&(w_op[3:0]!=4'hf))
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||((~w_op[4])&&(w_op[3:0]!=4'hf)&&(!w_brev))
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// STO's read A
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// STO's read A
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||((w_dcdM)&&(w_op[0]))
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||((w_dcdM)&&(w_op[0]))
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// Test/compares
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// Test/compares
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||(w_op[4:1]== 4'h8);
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||(w_cmptst);
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// 1 LUTs -- do we read a register for operand B? Specifically, do
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// 1 LUTs -- do we read a register for operand B? Specifically, do
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// we need to stall if the register is not (yet) ready?
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// we need to stall if the register is not (yet) ready?
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assign w_rB = (w_mov)||((iword[18])&&(~w_ldi));
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assign w_rB = (w_mov)||((iword[18])&&(~w_ldi));
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// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
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// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
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assign w_wR_n = ((w_dcdM)&&(w_op[0]))
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assign w_wR_n = (w_sto)||(w_cmptst)
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||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
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||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7));
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||(w_cmptst);
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assign w_wR = ~w_wR_n;
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assign w_wR = ~w_wR_n;
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//
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//
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// 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits)
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// 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits)
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//
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//
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// This'd be 4 LUTs, save that we have the carve out for NOOPs
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// This'd be 4 LUTs, save that we have the carve out for NOOPs
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| Line 277... |
Line 287... |
`ifdef OPT_VLIW
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`ifdef OPT_VLIW
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o_illegal <= (i_illegal);
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o_illegal <= (i_illegal);
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`else
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`else
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o_illegal <= ((i_illegal) || (i_instruction[31]));
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o_illegal <= ((i_illegal) || (i_instruction[31]));
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`endif
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`endif
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if ((IMPLEMENT_MPY==0)&&((w_op[4:1]==4'h5)||(w_op[4:0]==5'h08)))
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if ((IMPLEMENT_MPY==0)&&(w_mpy))
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o_illegal <= 1'b1;
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o_illegal <= 1'b1;
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if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
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if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
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o_illegal <= 1'b1;
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o_illegal <= 1'b1;
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else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
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else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
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| Line 423... |
Line 433... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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begin
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begin
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if (r_ljmp)
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if (r_ljmp)
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r_branch_pc <= iword[(AW-1):0];
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r_branch_pc <= iword[(AW-1):0];
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else if (w_op[4:1] == 4'hb) // LDI
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else if (w_ldi) // LDI
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r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]};
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r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]};
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else // Add x,PC
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else // Add x,PC
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r_branch_pc <= i_pc
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r_branch_pc <= i_pc
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+ {{(AW-17){iword[17]}},iword[16:0]}
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+ {{(AW-17){iword[17]}},iword[16:0]}
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+ {{(AW-1){1'b0}},1'b1};
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+ {{(AW-1){1'b0}},1'b1};
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