| Line 48... |
Line 48... |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr,
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr,
|
i_wb_data, o_wb_ack, o_wb_stall, o_wb_data,
|
i_wb_data, o_wb_ack, o_wb_stall, o_wb_data,
|
// Cross-board I/O
|
// Cross-board I/O
|
i_rtc_ppd, i_buserr, i_other_ints, o_bus_int, o_board_ints);
|
i_rtc_ppd, i_buserr, i_other_ints, o_bus_int, o_board_ints);
|
parameter AUXUART_SETUP = 30'd1736, // 115200 baud from 200MHz clk
|
parameter AUXUART_SETUP = 30'd1736, // 115200 baud from 200MHz clk
|
GPSUART_SETUP = 30'd20833; // 9600 baud from 200MHz clk
|
GPSUART_SETUP = 30'd20833, // 9600 baud from 200MHz clk
|
|
EXTRACLOCK = 1; // Do we need an extra clock to process?
|
input i_clk;
|
input i_clk;
|
// Board level I/O
|
// Board level I/O
|
input [3:0] i_sw;
|
input [3:0] i_sw;
|
input [3:0] i_btn;
|
input [3:0] i_btn;
|
output wire [3:0] o_led;
|
output wire [3:0] o_led;
|
| Line 92... |
Line 93... |
// in the design
|
// in the design
|
input wire [8:0] i_other_ints;
|
input wire [8:0] i_other_ints;
|
output wire o_bus_int;
|
output wire o_bus_int;
|
output wire [5:0] o_board_ints; // Button and switch interrupts
|
output wire [5:0] o_board_ints; // Button and switch interrupts
|
|
|
|
wire [31:0] w_wb_data;
|
|
wire [4:0] w_wb_addr;
|
|
wire w_wb_stb;
|
|
|
|
generate
|
|
if (EXTRACLOCK == 0)
|
|
begin
|
|
assign w_wb_data = i_wb_data;
|
|
assign w_wb_addr = i_wb_addr;
|
|
assign w_wb_stb = (i_wb_stb)&&(i_wb_we);
|
|
end else begin
|
reg last_wb_stb;
|
reg last_wb_stb;
|
reg [4:0] last_wb_addr;
|
reg [4:0] last_wb_addr;
|
reg [31:0] last_wb_data;
|
reg [31:0] last_wb_data;
|
initial last_wb_stb = 1'b0;
|
initial last_wb_stb = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 103... |
Line 115... |
last_wb_addr <= i_wb_addr;
|
last_wb_addr <= i_wb_addr;
|
last_wb_data <= i_wb_data;
|
last_wb_data <= i_wb_data;
|
last_wb_stb <= (i_wb_stb)&&(i_wb_we);
|
last_wb_stb <= (i_wb_stb)&&(i_wb_we);
|
end
|
end
|
|
|
|
assign w_wb_data = last_wb_data;
|
|
assign w_wb_addr = last_wb_addr;
|
|
assign w_wb_stb = last_wb_stb;
|
|
end endgenerate
|
|
|
wire [31:0] pic_data;
|
wire [31:0] pic_data;
|
reg sw_int, btn_int;
|
reg sw_int, btn_int;
|
wire pps_int, rtc_int, netrx_int, nettx_int,
|
wire pps_int, rtc_int, netrx_int, nettx_int,
|
auxrx_int, auxtx_int, gpio_int, flash_int, scop_int,
|
auxrx_int, auxtx_int, gpio_int, flash_int, scop_int,
|
gpsrx_int, sd_int, oled_int, zip_int;
|
gpsrx_int, sd_int, oled_int, zip_int;
|
| Line 116... |
Line 133... |
|
|
//
|
//
|
// The BUS Interrupt controller
|
// The BUS Interrupt controller
|
//
|
//
|
icontrol #(15) buspic(i_clk, 1'b0,
|
icontrol #(15) buspic(i_clk, 1'b0,
|
(last_wb_stb)&&(last_wb_addr==5'h1),
|
(w_wb_stb)&&(w_wb_addr==5'h1),
|
i_wb_data, pic_data,
|
i_wb_data, pic_data,
|
{ zip_int, oled_int, sd_int,
|
{ zip_int, oled_int, sd_int,
|
gpsrx_int, scop_int, flash_int, gpio_int,
|
gpsrx_int, scop_int, flash_int, gpio_int,
|
auxtx_int, auxrx_int, nettx_int, netrx_int,
|
auxtx_int, auxrx_int, nettx_int, netrx_int,
|
rtc_int, pps_int, sw_int, btn_int },
|
rtc_int, pps_int, sw_int, btn_int },
|
| Line 150... |
Line 167... |
r_sw <= i_sw;
|
r_sw <= i_sw;
|
swnow <= r_sw;
|
swnow <= r_sw;
|
swlast<= swnow;
|
swlast<= swnow;
|
sw_int <= |((swnow^swlast)|swcfg);
|
sw_int <= |((swnow^swlast)|swcfg);
|
|
|
if ((last_wb_stb)&&(last_wb_addr == 5'h4))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h4))
|
swcfg <= ((last_wb_data[3:0])&(last_wb_data[11:8]))
|
swcfg <= ((w_wb_data[3:0])&(w_wb_data[11:8]))
|
|((~last_wb_data[3:0])&(swcfg));
|
|((~w_wb_data[3:0])&(swcfg));
|
|
|
r_btn <= i_btn;
|
r_btn <= i_btn;
|
btnnow <= r_btn;
|
btnnow <= r_btn;
|
btn_int <= |(btnnow&btncfg);
|
btn_int <= |(btnnow&btncfg);
|
if ((last_wb_stb)&&(last_wb_addr == 5'h4))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h4))
|
begin
|
begin
|
btncfg <= ((last_wb_data[7:4])&(last_wb_data[15:12]))
|
btncfg <= ((w_wb_data[7:4])&(w_wb_data[15:12]))
|
|((~last_wb_data[7:4])&(btncfg));
|
|((~w_wb_data[7:4])&(btncfg));
|
btnstate<= (btnnow)|((btnstate)&(~last_wb_data[7:4]));
|
btnstate<= (btnnow)|((btnstate)&(~w_wb_data[7:4]));
|
end else
|
end else
|
btnstate <= (btnstate)|(btnnow);
|
btnstate <= (btnstate)|(btnnow);
|
end
|
end
|
assign w_btnsw = { 8'h00, btnnow, 4'h0, btncfg, swcfg, btnstate, swnow };
|
assign w_btnsw = { 8'h00, btnnow, 4'h0, btncfg, swcfg, btnstate, swnow };
|
|
|
//
|
//
|
// LEDCTRL
|
// LEDCTRL
|
//
|
//
|
reg [3:0] r_leds;
|
reg [3:0] r_leds;
|
wire [31:0] w_ledreg;
|
wire [31:0] w_ledreg;
|
reg last_cyc;
|
|
always @(posedge i_clk)
|
|
last_cyc <= i_wb_cyc;
|
|
initial r_leds = 4'h0;
|
initial r_leds = 4'h0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h5))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h5))
|
r_leds <= ((last_wb_data[7:4])&(last_wb_data[3:0]))
|
r_leds <= ((w_wb_data[7:4])&(w_wb_data[3:0]))
|
|((~last_wb_data[7:4])&(r_leds));
|
|((~w_wb_data[7:4])&(r_leds));
|
assign o_led = r_leds;
|
assign o_led = r_leds;
|
assign w_ledreg = { 28'h0, r_leds };
|
assign w_ledreg = { 28'h0, r_leds };
|
|
|
//
|
//
|
// GPIO
|
// GPIO
|
| Line 200... |
Line 214... |
//
|
//
|
// Set us up for 4Mbaud, 8 data bits, no stop bits.
|
// Set us up for 4Mbaud, 8 data bits, no stop bits.
|
reg [29:0] aux_setup;
|
reg [29:0] aux_setup;
|
initial aux_setup = AUXUART_SETUP;
|
initial aux_setup = AUXUART_SETUP;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h6))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h6))
|
aux_setup[29:0] <= last_wb_data[29:0];
|
aux_setup[29:0] <= w_wb_data[29:0];
|
|
|
//
|
//
|
// GPSSETUP
|
// GPSSETUP
|
//
|
//
|
// Set us up for 9600 kbaud, 8 data bits, no stop bits.
|
// Set us up for 9600 kbaud, 8 data bits, no stop bits.
|
reg [29:0] gps_setup;
|
reg [29:0] gps_setup;
|
initial gps_setup = GPSUART_SETUP;
|
initial gps_setup = GPSUART_SETUP;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h7))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h7))
|
gps_setup[29:0] <= last_wb_data[29:0];
|
gps_setup[29:0] <= w_wb_data[29:0];
|
|
|
//
|
//
|
// CLR LEDs
|
// CLR LEDs
|
//
|
//
|
|
|
| Line 224... |
Line 238... |
reg [8:0] r_clr_led0_r, r_clr_led0_g, r_clr_led0_b;
|
reg [8:0] r_clr_led0_r, r_clr_led0_g, r_clr_led0_b;
|
initial r_clr_led0_r = 9'h003; // Color LED on the far right
|
initial r_clr_led0_r = 9'h003; // Color LED on the far right
|
initial r_clr_led0_g = 9'h000;
|
initial r_clr_led0_g = 9'h000;
|
initial r_clr_led0_b = 9'h000;
|
initial r_clr_led0_b = 9'h000;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h8))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h8))
|
begin
|
begin
|
r_clr_led0_r <= { last_wb_data[26], last_wb_data[23:16] };
|
r_clr_led0_r <= { w_wb_data[26], w_wb_data[23:16] };
|
r_clr_led0_g <= { last_wb_data[25], last_wb_data[15: 8] };
|
r_clr_led0_g <= { w_wb_data[25], w_wb_data[15: 8] };
|
r_clr_led0_b <= { last_wb_data[24], last_wb_data[ 7: 0] };
|
r_clr_led0_b <= { w_wb_data[24], w_wb_data[ 7: 0] };
|
end
|
end
|
assign w_clr_led0 = { 5'h0,
|
assign w_clr_led0 = { 5'h0,
|
r_clr_led0_r[8], r_clr_led0_g[8], r_clr_led0_b[8],
|
r_clr_led0_r[8], r_clr_led0_g[8], r_clr_led0_b[8],
|
r_clr_led0_r[7:0], r_clr_led0_g[7:0], r_clr_led0_b[7:0]
|
r_clr_led0_r[7:0], r_clr_led0_g[7:0], r_clr_led0_b[7:0]
|
};
|
};
|
| Line 246... |
Line 260... |
reg [8:0] r_clr_led1_r, r_clr_led1_g, r_clr_led1_b;
|
reg [8:0] r_clr_led1_r, r_clr_led1_g, r_clr_led1_b;
|
initial r_clr_led1_r = 9'h007;
|
initial r_clr_led1_r = 9'h007;
|
initial r_clr_led1_g = 9'h000;
|
initial r_clr_led1_g = 9'h000;
|
initial r_clr_led1_b = 9'h000;
|
initial r_clr_led1_b = 9'h000;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h9))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h9))
|
begin
|
begin
|
r_clr_led1_r <= { last_wb_data[26], last_wb_data[23:16] };
|
r_clr_led1_r <= { w_wb_data[26], w_wb_data[23:16] };
|
r_clr_led1_g <= { last_wb_data[25], last_wb_data[15: 8] };
|
r_clr_led1_g <= { w_wb_data[25], w_wb_data[15: 8] };
|
r_clr_led1_b <= { last_wb_data[24], last_wb_data[ 7: 0] };
|
r_clr_led1_b <= { w_wb_data[24], w_wb_data[ 7: 0] };
|
end
|
end
|
assign w_clr_led1 = { 5'h0,
|
assign w_clr_led1 = { 5'h0,
|
r_clr_led1_r[8], r_clr_led1_g[8], r_clr_led1_b[8],
|
r_clr_led1_r[8], r_clr_led1_g[8], r_clr_led1_b[8],
|
r_clr_led1_r[7:0], r_clr_led1_g[7:0], r_clr_led1_b[7:0]
|
r_clr_led1_r[7:0], r_clr_led1_g[7:0], r_clr_led1_b[7:0]
|
};
|
};
|
| Line 267... |
Line 281... |
reg [8:0] r_clr_led2_r, r_clr_led2_g, r_clr_led2_b;
|
reg [8:0] r_clr_led2_r, r_clr_led2_g, r_clr_led2_b;
|
initial r_clr_led2_r = 9'h00f;
|
initial r_clr_led2_r = 9'h00f;
|
initial r_clr_led2_g = 9'h000;
|
initial r_clr_led2_g = 9'h000;
|
initial r_clr_led2_b = 9'h000;
|
initial r_clr_led2_b = 9'h000;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'ha))
|
if ((w_wb_stb)&&(w_wb_addr == 5'ha))
|
begin
|
begin
|
r_clr_led2_r <= { last_wb_data[26], last_wb_data[23:16] };
|
r_clr_led2_r <= { w_wb_data[26], w_wb_data[23:16] };
|
r_clr_led2_g <= { last_wb_data[25], last_wb_data[15: 8] };
|
r_clr_led2_g <= { w_wb_data[25], w_wb_data[15: 8] };
|
r_clr_led2_b <= { last_wb_data[24], last_wb_data[ 7: 0] };
|
r_clr_led2_b <= { w_wb_data[24], w_wb_data[ 7: 0] };
|
end
|
end
|
assign w_clr_led2 = { 5'h0,
|
assign w_clr_led2 = { 5'h0,
|
r_clr_led2_r[8], r_clr_led2_g[8], r_clr_led2_b[8],
|
r_clr_led2_r[8], r_clr_led2_g[8], r_clr_led2_b[8],
|
r_clr_led2_r[7:0], r_clr_led2_g[7:0], r_clr_led2_b[7:0]
|
r_clr_led2_r[7:0], r_clr_led2_g[7:0], r_clr_led2_b[7:0]
|
};
|
};
|
| Line 288... |
Line 302... |
reg [8:0] r_clr_led3_r, r_clr_led3_g, r_clr_led3_b;
|
reg [8:0] r_clr_led3_r, r_clr_led3_g, r_clr_led3_b;
|
initial r_clr_led3_r = 9'h01f; // LED is on far left
|
initial r_clr_led3_r = 9'h01f; // LED is on far left
|
initial r_clr_led3_g = 9'h000;
|
initial r_clr_led3_g = 9'h000;
|
initial r_clr_led3_b = 9'h000;
|
initial r_clr_led3_b = 9'h000;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'hb))
|
if ((w_wb_stb)&&(w_wb_addr == 5'hb))
|
begin
|
begin
|
r_clr_led3_r <= { last_wb_data[26], last_wb_data[23:16] };
|
r_clr_led3_r <= { w_wb_data[26], w_wb_data[23:16] };
|
r_clr_led3_g <= { last_wb_data[25], last_wb_data[15: 8] };
|
r_clr_led3_g <= { w_wb_data[25], w_wb_data[15: 8] };
|
r_clr_led3_b <= { last_wb_data[24], last_wb_data[ 7: 0] };
|
r_clr_led3_b <= { w_wb_data[24], w_wb_data[ 7: 0] };
|
end
|
end
|
assign w_clr_led3 = { 5'h0,
|
assign w_clr_led3 = { 5'h0,
|
r_clr_led3_r[8], r_clr_led3_g[8], r_clr_led3_b[8],
|
r_clr_led3_r[8], r_clr_led3_g[8], r_clr_led3_b[8],
|
r_clr_led3_r[7:0], r_clr_led3_g[7:0], r_clr_led3_b[7:0]
|
r_clr_led3_r[7:0], r_clr_led3_g[7:0], r_clr_led3_b[7:0]
|
};
|
};
|
| Line 311... |
Line 325... |
wire [31:0] date_data;
|
wire [31:0] date_data;
|
`define GET_DATE
|
`define GET_DATE
|
`ifdef GET_DATE
|
`ifdef GET_DATE
|
wire date_ack, date_stall;
|
wire date_ack, date_stall;
|
rtcdate thedate(i_clk, i_rtc_ppd,
|
rtcdate thedate(i_clk, i_rtc_ppd,
|
i_wb_cyc, last_wb_stb, (last_wb_addr==5'hc), last_wb_data,
|
i_wb_cyc, w_wb_stb, (w_wb_addr==5'hc), w_wb_data,
|
date_ack, date_stall, date_data);
|
date_ack, date_stall, date_data);
|
`else
|
`else
|
assign date_data = 32'h20160000;
|
assign date_data = 32'h20160000;
|
`endif
|
`endif
|
|
|
| Line 344... |
Line 358... |
r_auxrx_data[ 9] <= auxrx_perr;
|
r_auxrx_data[ 9] <= auxrx_perr;
|
r_auxrx_data[7:0]<= rx_data_aux_port;
|
r_auxrx_data[7:0]<= rx_data_aux_port;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h0e))||(auxrx_stb))
|
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h0e))||(auxrx_stb))
|
r_auxrx_data[8] <= auxrx_stb;
|
r_auxrx_data[8] <= !auxrx_stb;
|
assign o_aux_cts = auxrx_stb;
|
assign o_aux_cts = auxrx_stb;
|
assign auxrx_data = { 20'h00, r_auxrx_data };
|
assign auxrx_data = { 20'h00, r_auxrx_data };
|
assign auxrx_int = r_auxrx_data[8];
|
assign auxrx_int = r_auxrx_data[8];
|
|
|
//
|
//
|
| Line 360... |
Line 374... |
wire [31:0] auxtx_data;
|
wire [31:0] auxtx_data;
|
txuart auxtx(i_clk, 1'b0, aux_setup,
|
txuart auxtx(i_clk, 1'b0, aux_setup,
|
r_auxtx_break, r_auxtx_stb, r_auxtx_data,
|
r_auxtx_break, r_auxtx_stb, r_auxtx_data,
|
o_aux_tx, auxtx_busy);
|
o_aux_tx, auxtx_busy);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h0f))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h0f))
|
begin
|
begin
|
r_auxtx_stb <= 1'b1;
|
r_auxtx_stb <= (!r_auxtx_break)&&(!w_wb_data[9]);
|
r_auxtx_data <= last_wb_data[7:0];
|
r_auxtx_data <= w_wb_data[7:0];
|
r_auxtx_break<= last_wb_data[9];
|
r_auxtx_break<= w_wb_data[9];
|
end else if (~auxtx_busy)
|
end else if (~auxtx_busy)
|
begin
|
begin
|
r_auxtx_stb <= 1'b0;
|
r_auxtx_stb <= 1'b0;
|
r_auxtx_data <= 8'h0;
|
r_auxtx_data <= 8'h0;
|
end
|
end
|
| Line 414... |
Line 428... |
wire [31:0] gpstx_data;
|
wire [31:0] gpstx_data;
|
txuart gpstx(i_clk, 1'b0, gps_setup,
|
txuart gpstx(i_clk, 1'b0, gps_setup,
|
r_gpstx_break, r_gpstx_stb, r_gpstx_data,
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r_gpstx_break, r_gpstx_stb, r_gpstx_data,
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o_gps_tx, gpstx_busy);
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o_gps_tx, gpstx_busy);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((last_wb_stb)&&(last_wb_addr == 5'h11))
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if ((w_wb_stb)&&(w_wb_addr == 5'h11))
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begin
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begin
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r_gpstx_stb <= 1'b1;
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r_gpstx_stb <= 1'b1;
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r_gpstx_data <= last_wb_data[7:0];
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r_gpstx_data <= w_wb_data[7:0];
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r_gpstx_break<= last_wb_data[9];
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r_gpstx_break<= w_wb_data[9];
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end else if (~gpstx_busy)
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end else if (~gpstx_busy)
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begin
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begin
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r_gpstx_stb <= 1'b0;
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r_gpstx_stb <= 1'b0;
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r_gpstx_data <= 8'h0;
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r_gpstx_data <= 8'h0;
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end
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end
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