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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_sfr.v] - Diff between revs 107 and 111

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Rev 107 Rev 111
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 106 $
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
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    per_addr,                     // Peripheral address
    per_addr,                     // Peripheral address
    per_din,                      // Peripheral data input
    per_din,                      // Peripheral data input
    per_en,                       // Peripheral enable (high active)
    per_en,                       // Peripheral enable (high active)
    per_we,                       // Peripheral write enable (high active)
    per_we,                       // Peripheral write enable (high active)
    por,                          // Power-on reset
    por,                          // Power-on reset
    puc,                          // Main system reset
    puc_rst,                      // Main system reset
    wdtifg_clr,                   // Clear Watchdog-timer interrupt flag
    wdtifg_clr,                   // Clear Watchdog-timer interrupt flag
    wdtifg_set,                   // Set Watchdog-timer interrupt flag
    wdtifg_set,                   // Set Watchdog-timer interrupt flag
    wdtpw_error,                  // Watchdog-timer password error
    wdtpw_error,                  // Watchdog-timer password error
    wdttmsel                      // Watchdog-timer mode select
    wdttmsel                      // Watchdog-timer mode select
);
);
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// INPUTs
// INPUTs
//=========
//=========
input               mclk;         // Main system clock
input               mclk;         // Main system clock
input               nmi_acc;      // Non-Maskable interrupt request accepted
input               nmi_acc;      // Non-Maskable interrupt request accepted
input         [7:0] per_addr;     // Peripheral address
input        [13:0] per_addr;     // Peripheral address
input        [15:0] per_din;      // Peripheral data input
input        [15:0] per_din;      // Peripheral data input
input               per_en;       // Peripheral enable (high active)
input               per_en;       // Peripheral enable (high active)
input         [1:0] per_we;       // Peripheral write enable (high active)
input         [1:0] per_we;       // Peripheral write enable (high active)
input               por;          // Power-on reset
input               por;          // Power-on reset
input               puc;          // Main system reset
input               puc_rst;      // Main system reset
input               wdtifg_clr;   // Clear Watchdog-timer interrupt flag
input               wdtifg_clr;   // Clear Watchdog-timer interrupt flag
input               wdtifg_set;   // Set Watchdog-timer interrupt flag
input               wdtifg_set;   // Set Watchdog-timer interrupt flag
input               wdtpw_error;  // Watchdog-timer password error
input               wdtpw_error;  // Watchdog-timer password error
input               wdttmsel;     // Watchdog-timer mode select
input               wdttmsel;     // Watchdog-timer mode select
 
 
 
 
//=============================================================================
//=============================================================================
// 1)  PARAMETER DECLARATION
// 1)  PARAMETER DECLARATION
//=============================================================================
//=============================================================================
 
 
// Register addresses
// Register base address (must be aligned to decoder bit width)
parameter           IE1        = 9'h000;
parameter       [14:0] BASE_ADDR   = 15'h0000;
parameter           IFG1       = 9'h002;
 
 
// Decoder bit width (defines how many bits are considered for address decoding)
 
parameter              DEC_WD      =  2;
 
 
 
// Register addresses offset
 
parameter [DEC_WD-1:0] IE1         =  'h0,
 
                       IFG1        =  'h2;
 
 
 
// Register one-hot decoder utilities
 
parameter              DEC_SZ      =  2**DEC_WD;
 
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
 
 
// Register one-hot decoder
// Register one-hot decoder
parameter           IE1_D      = (256'h1 << (IE1  /2));
parameter [DEC_SZ-1:0] IE1_D       = (BASE_REG << IE1),
parameter           IFG1_D     = (256'h1 << (IFG1 /2));
                       IFG1_D      = (BASE_REG << IFG1);
 
 
 
 
//============================================================================
//============================================================================
// 2)  REGISTER DECODER
// 2)  REGISTER DECODER
//============================================================================
//============================================================================
 
 
 
// Local register selection
 
wire              reg_sel      =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
 
 
 
// Register local address
 
wire [DEC_WD-1:0] reg_addr     =  {1'b0, per_addr[DEC_WD-2:0]};
 
 
// Register address decode
// Register address decode
reg  [255:0]  reg_dec;
wire [DEC_SZ-1:0] reg_dec      = (IE1_D   &  {DEC_SZ{(reg_addr==(IE1  >>1))}})  |
always @(per_addr)
                                 (IFG1_D  &  {DEC_SZ{(reg_addr==(IFG1 >>1))}});
  case (per_addr)
 
    (IE1  /2):     reg_dec  =  IE1_D;
 
    (IFG1 /2):     reg_dec  =  IFG1_D;
 
    default  :     reg_dec  =  {256{1'b0}};
 
  endcase
 
 
 
// Read/Write probes
// Read/Write probes
wire         reg_lo_write =  per_we[0] & per_en;
wire              reg_lo_write =  per_we[0] & reg_sel;
wire         reg_hi_write =  per_we[1] & per_en;
wire              reg_hi_write =  per_we[1] & reg_sel;
wire         reg_read     = ~|per_we   & per_en;
wire              reg_read     = ~|per_we   & reg_sel;
 
 
// Read/Write vectors
// Read/Write vectors
wire [255:0] reg_hi_wr    = reg_dec & {256{reg_hi_write}};
wire [DEC_SZ-1:0] reg_hi_wr    = reg_dec & {DEC_SZ{reg_hi_write}};
wire [255:0] reg_lo_wr    = reg_dec & {256{reg_lo_write}};
wire [DEC_SZ-1:0] reg_lo_wr    = reg_dec & {DEC_SZ{reg_lo_write}};
wire [255:0] reg_rd       = reg_dec & {256{reg_read}};
wire [DEC_SZ-1:0] reg_rd       = reg_dec & {DEC_SZ{reg_read}};
 
 
 
 
//============================================================================
//============================================================================
// 3) REGISTERS
// 3) REGISTERS
//============================================================================
//============================================================================
 
 
// IE1 Register
// IE1 Register
//--------------
//--------------
wire [7:0] ie1;
wire [7:0] ie1;
wire       ie1_wr  = IE1[0] ? reg_hi_wr[IE1/2] : reg_lo_wr[IE1/2];
wire       ie1_wr  = IE1[0] ? reg_hi_wr[IE1] : reg_lo_wr[IE1];
wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8]    : per_din[7:0];
wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8]    : per_din[7:0];
 
 
reg        nmie;
reg        nmie;
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc_rst)
  if (puc)          nmie  <=  1'b0;
  if (puc_rst)      nmie  <=  1'b0;
  else if (nmi_acc) nmie  <=  1'b0;
  else if (nmi_acc) nmie  <=  1'b0;
  else if (ie1_wr)  nmie  <=  ie1_nxt[4];
  else if (ie1_wr)  nmie  <=  ie1_nxt[4];
 
 
reg        wdtie;
reg        wdtie;
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc_rst)
  if (puc)           wdtie <=  1'b0;
  if (puc_rst)      wdtie <=  1'b0;
  else if (ie1_wr)   wdtie <=  ie1_nxt[0];
  else if (ie1_wr)   wdtie <=  ie1_nxt[0];
 
 
assign  ie1 = {3'b000, nmie, 3'b000, wdtie};
assign  ie1 = {3'b000, nmie, 3'b000, wdtie};
 
 
 
 
// IFG1 Register
// IFG1 Register
//---------------
//---------------
wire [7:0] ifg1;
wire [7:0] ifg1;
wire       ifg1_wr  = IFG1[0] ? reg_hi_wr[IFG1/2] : reg_lo_wr[IFG1/2];
wire       ifg1_wr  = IFG1[0] ? reg_hi_wr[IFG1] : reg_lo_wr[IFG1];
wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8]     : per_din[7:0];
wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8]     : per_din[7:0];
 
 
reg        nmiifg;
reg        nmiifg;
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc_rst)
  if (puc)           nmiifg <=  1'b0;
  if (puc_rst)       nmiifg <=  1'b0;
  else if (nmi_acc)  nmiifg <=  1'b1;
  else if (nmi_acc)  nmiifg <=  1'b1;
  else if (ifg1_wr)  nmiifg <=  ifg1_nxt[4];
  else if (ifg1_wr)  nmiifg <=  ifg1_nxt[4];
 
 
reg        wdtifg;
reg        wdtifg;
always @ (posedge mclk or posedge por)
always @ (posedge mclk or posedge por)
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//============================================================================
//============================================================================
// 4) DATA OUTPUT GENERATION
// 4) DATA OUTPUT GENERATION
//============================================================================
//============================================================================
 
 
// Data output mux
// Data output mux
wire [15:0] ie1_rd   = {8'h00, (ie1  & {8{reg_rd[IE1/2]}})}  << (8 & {4{IE1[0]}});
wire [15:0] ie1_rd   = {8'h00, (ie1  & {8{reg_rd[IE1]}})}  << (8 & {4{IE1[0]}});
wire [15:0] ifg1_rd  = {8'h00, (ifg1 & {8{reg_rd[IFG1/2]}})} << (8 & {4{IFG1[0]}});
wire [15:0] ifg1_rd  = {8'h00, (ifg1 & {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}});
 
 
wire [15:0] per_dout =  ie1_rd   |
wire [15:0] per_dout =  ie1_rd   |
                        ifg1_rd;
                        ifg1_rd;
 
 
 
 

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