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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_watchdog.v] - Diff between revs 107 and 111

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Rev 107 Rev 111
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 106 $
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
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    nmie,                           // Non-maskable interrupt enable
    nmie,                           // Non-maskable interrupt enable
    per_addr,                       // Peripheral address
    per_addr,                       // Peripheral address
    per_din,                        // Peripheral data input
    per_din,                        // Peripheral data input
    per_en,                         // Peripheral enable (high active)
    per_en,                         // Peripheral enable (high active)
    per_we,                         // Peripheral write enable (high active)
    per_we,                         // Peripheral write enable (high active)
    puc,                            // Main system reset
    puc_rst,                        // Main system reset
    smclk_en,                       // SMCLK enable
    smclk_en,                       // SMCLK enable
    wdtie                           // Watchdog timer interrupt enable
    wdtie                           // Watchdog timer interrupt enable
);
);
 
 
// OUTPUTs
// OUTPUTs
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input               aclk_en;        // ACLK enable
input               aclk_en;        // ACLK enable
input               dbg_freeze;     // Freeze Watchdog counter
input               dbg_freeze;     // Freeze Watchdog counter
input               mclk;           // Main system clock
input               mclk;           // Main system clock
input               nmi;            // Non-maskable interrupt (asynchronous)
input               nmi;            // Non-maskable interrupt (asynchronous)
input               nmie;           // Non-maskable interrupt enable
input               nmie;           // Non-maskable interrupt enable
input         [7:0] per_addr;       // Peripheral address
input        [13:0] per_addr;       // Peripheral address
input        [15:0] per_din;        // Peripheral data input
input        [15:0] per_din;        // Peripheral data input
input               per_en;         // Peripheral enable (high active)
input               per_en;         // Peripheral enable (high active)
input         [1:0] per_we;         // Peripheral write enable (high active)
input         [1:0] per_we;         // Peripheral write enable (high active)
input               puc;            // Main system reset
input               puc_rst;        // Main system reset
input               smclk_en;       // SMCLK enable
input               smclk_en;       // SMCLK enable
input               wdtie;          // Watchdog timer interrupt enable
input               wdtie;          // Watchdog timer interrupt enable
 
 
 
 
//=============================================================================
//=============================================================================
// 1)  PARAMETER DECLARATION
// 1)  PARAMETER DECLARATION
//=============================================================================
//=============================================================================
 
 
// Register addresses
// Register base address (must be aligned to decoder bit width)
parameter           WDTCTL     = 9'h120;
parameter       [14:0] BASE_ADDR   = 15'h0120;
 
 
 
// Decoder bit width (defines how many bits are considered for address decoding)
 
parameter              DEC_WD      =  2;
 
 
 
// Register addresses offset
 
parameter [DEC_WD-1:0] WDTCTL      = 'h0;
 
 
 
// Register one-hot decoder utilities
 
parameter              DEC_SZ      =  2**DEC_WD;
 
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
 
 
// Register one-hot decoder
// Register one-hot decoder
parameter           WDTCTL_D   = (512'h1 << WDTCTL);
parameter [DEC_SZ-1:0] WDTCTL_D    = (BASE_REG << WDTCTL);
 
 
 
 
//============================================================================
//============================================================================
// 2)  REGISTER DECODER
// 2)  REGISTER DECODER
//============================================================================
//============================================================================
 
 
 
// Local register selection
 
wire              reg_sel   =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
 
 
 
// Register local address
 
wire [DEC_WD-1:0] reg_addr  =  {per_addr[DEC_WD-2:0], 1'b0};
 
 
// Register address decode
// Register address decode
reg  [511:0]  reg_dec;
wire [DEC_SZ-1:0] reg_dec   =  (WDTCTL_D & {DEC_SZ{(reg_addr==WDTCTL)}});
always @(per_addr)
 
  case ({per_addr,1'b0})
 
    WDTCTL :     reg_dec  =  WDTCTL_D;
 
    default:     reg_dec  =  {512{1'b0}};
 
  endcase
 
 
 
// Read/Write probes
// Read/Write probes
wire reg_write =  |per_we & per_en;
wire              reg_write =  |per_we & reg_sel;
wire reg_read  = ~|per_we & per_en;
wire              reg_read  = ~|per_we & reg_sel;
 
 
// Read/Write vectors
// Read/Write vectors
wire [511:0] reg_wr    = reg_dec & {512{reg_write}};
wire [DEC_SZ-1:0] reg_wr    = reg_dec & {DEC_SZ{reg_write}};
wire [511:0] reg_rd    = reg_dec & {512{reg_read}};
wire [DEC_SZ-1:0] reg_rd    = reg_dec & {DEC_SZ{reg_read}};
 
 
 
 
//============================================================================
//============================================================================
// 3) REGISTERS
// 3) REGISTERS
//============================================================================
//============================================================================
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reg  [7:0] wdtctl;
reg  [7:0] wdtctl;
 
 
wire       wdtctl_wr = reg_wr[WDTCTL];
wire       wdtctl_wr = reg_wr[WDTCTL];
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc_rst)
  if (puc)            wdtctl <=  8'h00;
  if (puc_rst)        wdtctl <=  8'h00;
  else if (wdtctl_wr) wdtctl <=  per_din[7:0] & 8'hd7;
  else if (wdtctl_wr) wdtctl <=  per_din[7:0] & 8'hd7;
 
 
wire       wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
wire       wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
wire       wdttmsel    = wdtctl[4];
wire       wdttmsel    = wdtctl[4];
 
 
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//=============================================================================
//=============================================================================
// 4)  NMI GENERATION
// 4)  NMI GENERATION
//=============================================================================
//=============================================================================
 
 
// Synchronization state
// Synchronization
reg [2:0] nmi_sync;
wire   nmi_s;
always @ (posedge mclk or posedge puc)
`ifdef SYNC_NMI
  if (puc)  nmi_sync <= 3'h0;
omsp_sync_cell sync_cell_nmi (
  else      nmi_sync <= {nmi_sync[1:0], nmi};
    .data_out (nmi_s),
 
    .clk      (mclk),
 
    .data_in  (nmi),
 
    .rst      (puc_rst)
 
);
 
`else
 
assign nmi_s = nmi;
 
`endif
 
 
 
// Delay
 
reg  nmi_dly;
 
always @ (posedge mclk or posedge puc_rst)
 
  if (puc_rst) nmi_dly <= 1'b0;
 
  else         nmi_dly <= nmi_s;
 
 
// Edge detection
// Edge detection
wire        nmi_re    = ~nmi_sync[2] &  nmi_sync[1] & nmie;
wire        nmi_re    = ~nmi_dly &  nmi_s & nmie;
wire        nmi_fe    =  nmi_sync[2] & ~nmi_sync[1] & nmie;
wire        nmi_fe    =  nmi_dly & ~nmi_s & nmie;
 
 
// NMI event
// NMI event
wire        nmi_evt   = wdtctl[6] ? nmi_fe : nmi_re;
wire        nmi_evt   = wdtctl[6] ? nmi_fe : nmi_re;
 
 
 
 
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//--------------------------
//--------------------------
reg [15:0] wdtcnt;
reg [15:0] wdtcnt;
 
 
wire       wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set;
wire       wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set;
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc_rst)
  if (puc)                                        wdtcnt <= 16'h0000;
  if (puc_rst)                                    wdtcnt <= 16'h0000;
  else if (wdtcnt_clr)                            wdtcnt <= 16'h0000;
  else if (wdtcnt_clr)                            wdtcnt <= 16'h0000;
  else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001;
  else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001;
 
 
 
 
// Interval selection mux
// Interval selection mux
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// Watchdog event detection
// Watchdog event detection
//-----------------------------
//-----------------------------
reg        wdtqn_dly;
reg        wdtqn_dly;
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc_rst)
  if (puc) wdtqn_dly <= 1'b0;
  if (puc_rst) wdtqn_dly <= 1'b0;
  else     wdtqn_dly <= wdtqn;
  else     wdtqn_dly <= wdtqn;
 
 
wire       wdtifg_set =  (~wdtqn_dly & wdtqn) | wdtpw_error;
wire       wdtifg_set =  (~wdtqn_dly & wdtqn) | wdtpw_error;
 
 
 
 

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