| Line 80... |
Line 80... |
vid_ram_dout_rdy_nxt_i, // Video-RAM data output ready during next cycle
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vid_ram_dout_rdy_nxt_i, // Video-RAM data output ready during next cycle
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refresh_active_i, // Display refresh on going
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refresh_active_i, // Display refresh on going
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refresh_data_request_i, // Display refresh new data request
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refresh_data_request_i, // Display refresh new data request
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refresh_frame_base_addr_i, // Refresh frame base address
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refresh_frame_base_addr_i, // Refresh frame base address
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refresh_lut_select_i // Refresh LUT bank selection
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hw_lut_palette_sel_i, // Hardware LUT palette configuration
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hw_lut_bgcolor_i, // Hardware LUT background-color selection
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hw_lut_fgcolor_i, // Hardware LUT foreground-color selection
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sw_lut_enable_i, // Refresh LUT-RAM enable
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sw_lut_bank_select_i // Refresh LUT-RAM bank selection
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [15:0] refresh_data_o; // Display refresh data
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output [15:0] refresh_data_o; // Display refresh data
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| Line 121... |
Line 126... |
input vid_ram_dout_rdy_nxt_i; // Video-RAM data output ready during next cycle
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input vid_ram_dout_rdy_nxt_i; // Video-RAM data output ready during next cycle
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input refresh_active_i; // Display refresh on going
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input refresh_active_i; // Display refresh on going
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input refresh_data_request_i; // Display refresh new data request
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input refresh_data_request_i; // Display refresh new data request
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input [`APIX_MSB:0] refresh_frame_base_addr_i; // Refresh frame base address
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input [`APIX_MSB:0] refresh_frame_base_addr_i; // Refresh frame base address
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input [1:0] refresh_lut_select_i; // Refresh LUT bank selection
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input [2:0] hw_lut_palette_sel_i; // Hardware LUT palette configuration
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input [3:0] hw_lut_bgcolor_i; // Hardware LUT background-color selection
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input [3:0] hw_lut_fgcolor_i; // Hardware LUT foreground-color selection
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input sw_lut_enable_i; // Refresh LUT-RAM enable
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input sw_lut_bank_select_i; // Refresh LUT-RAM bank selection
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//=============================================================================
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//=============================================================================
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// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
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// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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| Line 203... |
Line 213... |
.lut_ram_dout_rdy_nxt_i ( lut_ram_dout_rdy_nxt_i ), // LUT-RAM data output ready during next cycle
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.lut_ram_dout_rdy_nxt_i ( lut_ram_dout_rdy_nxt_i ), // LUT-RAM data output ready during next cycle
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`endif
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`endif
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.refresh_active_i ( refresh_active_i ), // Display refresh on going
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.refresh_active_i ( refresh_active_i ), // Display refresh on going
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.refresh_data_request_i ( refresh_data_request_i ), // Request for next refresh data
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.refresh_data_request_i ( refresh_data_request_i ), // Request for next refresh data
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.refresh_lut_select_i ( refresh_lut_select_i ) // Refresh LUT bank selection
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|
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.hw_lut_palette_sel_i ( hw_lut_palette_sel_i ), // Hardware LUT palette configuration
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.hw_lut_bgcolor_i ( hw_lut_bgcolor_i ), // Hardware LUT background-color selection
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.hw_lut_fgcolor_i ( hw_lut_fgcolor_i ), // Hardware LUT foreground-color selection
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.sw_lut_enable_i ( sw_lut_enable_i ), // Refresh LUT-RAM enable
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.sw_lut_bank_select_i ( sw_lut_bank_select_i ) // Refresh LUT-RAM bank selection
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);
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);
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endmodule // ogfx_backend
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endmodule // ogfx_backend
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|
