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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Diff between revs 10 and 141

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////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_genpc.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Major update: 
 
// Structure reordered and bugs fixed. 
 
//
 
// Revision 1.10  2004/06/08 18:17:36  lampret
 
// Non-functional changes. Coding style fixes.
 
//
// Revision 1.9  2004/04/05 08:29:57  lampret
// Revision 1.9  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
// Merged branch_qmem into main tree.
//
//
// Revision 1.7.4.3  2003/12/17 13:43:38  simons
// Revision 1.7.4.3  2003/12/17 13:43:38  simons
// Exception prefix configuration changed.
// Exception prefix configuration changed.
Line 112... Line 119...
        // External i/f to IC
        // External i/f to IC
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
        icpu_rty_i, icpu_adr_i,
        icpu_rty_i, icpu_adr_i,
 
 
        // Internal i/f
        // Internal i/f
        branch_op, except_type, except_prefix,
        pre_branch_op, branch_op, except_type, except_prefix,
        branch_addrofs, lr_restor, flag, taken, except_start,
        id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
        binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        flag, flagforw, ex_branch_taken, except_start,
        genpc_freeze, genpc_stop_prefetch, no_more_dslot
        epcr, spr_dat_i, spr_pc_we, genpc_refetch,
 
        genpc_freeze, no_more_dslot
);
);
 
 
//
//
// I/O
// I/O
//
//
Line 141... Line 149...
input   [31:0]                   icpu_adr_i;
input   [31:0]                   icpu_adr_i;
 
 
//
//
// Internal i/f
// Internal i/f
//
//
 
input   [`OR1200_BRANCHOP_WIDTH-1:0]    pre_branch_op;
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input                                   except_prefix;
input                                   except_prefix;
input   [31:2]                  branch_addrofs;
input   [31:2]                  id_branch_addrtarget;
input   [31:0]                   lr_restor;
input   [31:2]                  ex_branch_addrtarget;
 
input   [31:0]                   muxed_b;
 
input   [31:0]                   operand_b;
input                           flag;
input                           flag;
output                          taken;
input                           flagforw;
 
output                          ex_branch_taken;
input                           except_start;
input                           except_start;
input   [31:2]                  binsn_addr;
 
input   [31:0]                   epcr;
input   [31:0]                   epcr;
input   [31:0]                   spr_dat_i;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input                           spr_pc_we;
input                           genpc_refetch;
input                           genpc_refetch;
input                           genpc_stop_prefetch;
 
input                           genpc_freeze;
input                           genpc_freeze;
input                           no_more_dslot;
input                           no_more_dslot;
 
 
//
//
// Internal wires and regs
// Internal wires and regs
//
//
 
reg     [31:2]                  pcreg_default;
 
wire    [31:0]                   pcreg_boot;
 
reg                             pcreg_select;
reg     [31:2]                  pcreg;
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
reg     [31:0]                   pc;
reg                             taken;  /* Set to in case of jump or taken branch */
reg                             ex_branch_taken;        /* Set to in case of jump or taken branch */
reg                             genpc_refetch_r;
reg                             genpc_refetch_r;
 
 
//
//
// Address of insn to be fecthed
// Address of insn to be fecthed
//
//
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 
 
 
//
//
// Control access to IC subsystem
// Control access to IC subsystem
//
//
// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));
assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
 
//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
 
//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
 
assign icpu_sel_o = 4'b1111;
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
assign icpu_tag_o = `OR1200_ITAG_NI;
 
 
//
//
// genpc_freeze_r
// genpc_freeze_r
Line 196... Line 205...
                genpc_refetch_r <= #1 1'b0;
                genpc_refetch_r <= #1 1'b0;
 
 
//
//
// Async calculation of new PC value. This value is used for addressing the IC.
// Async calculation of new PC value. This value is used for addressing the IC.
//
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
        or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
        or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                        pc = {pcreg + 30'd1, 2'b0};
                        pc = {pcreg + 30'd1, 2'b0};
                        taken = 1'b0;
                        ex_branch_taken = 1'b0;
                end
                end
                {2'b00, `OR1200_BRANCHOP_J}: begin
                {2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
`ifdef OR1200_VERBOSE
// synopsys translate_off
// synopsys translate_off
                        $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
                        $display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
// synopsys translate_on
// synopsys translate_on
`endif
`endif
                        pc = {branch_addrofs, 2'b0};
                        pc = {ex_branch_addrtarget, 2'b00};
                        taken = 1'b1;
                        ex_branch_taken = 1'b1;
                end
                end
                {2'b00, `OR1200_BRANCHOP_JR}: begin
                {2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
`ifdef OR1200_VERBOSE
// synopsys translate_off
// synopsys translate_off
                        $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
                        $display("%t: BRANCHOP_JR: pc <= operand_b %h", $time, operand_b);
// synopsys translate_on
// synopsys translate_on
`endif
`endif
                        pc = lr_restor;
                        pc = operand_b;
                        taken = 1'b1;
                        ex_branch_taken = 1'b1;
                end
 
                {2'b00, `OR1200_BRANCHOP_BAL}: begin
 
`ifdef OR1200_VERBOSE
 
// synopsys translate_off
 
                        $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
 
// synopsys translate_on
 
`endif
 
                        pc = {binsn_addr + branch_addrofs, 2'b0};
 
                        taken = 1'b1;
 
                end
                end
                {2'b00, `OR1200_BRANCHOP_BF}:
                {2'b00, `OR1200_BRANCHOP_BF}:
                        if (flag) begin
                        if (flag) begin
`ifdef OR1200_VERBOSE
`ifdef OR1200_VERBOSE
// synopsys translate_off
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
                                $display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
// synopsys translate_on
// synopsys translate_on
`endif
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                pc = {ex_branch_addrtarget, 2'b00};
                                taken = 1'b1;
                                ex_branch_taken = 1'b1;
                        end
                        end
                        else begin
                        else begin
`ifdef OR1200_VERBOSE
`ifdef OR1200_VERBOSE
// synopsys translate_off
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: not taken", $time);
                                $display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
// synopsys translate_on
`endif
`endif
                                pc = {pcreg + 30'd1, 2'b0};
                                pc = {pcreg + 30'd1, 2'b0};
                                taken = 1'b0;
                                ex_branch_taken = 1'b0;
                        end
                        end
                {2'b00, `OR1200_BRANCHOP_BNF}:
                {2'b00, `OR1200_BRANCHOP_BNF}:
                        if (flag) begin
                        if (flag) begin
                                pc = {pcreg + 30'd1, 2'b0};
 
`ifdef OR1200_VERBOSE
`ifdef OR1200_VERBOSE
// synopsys translate_off
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: not taken", $time);
                                $display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
// synopsys translate_on
`endif
`endif
                                taken = 1'b0;
                                pc = {pcreg + 30'd1, 2'b0};
 
                                ex_branch_taken = 1'b0;
                        end
                        end
                        else begin
                        else begin
`ifdef OR1200_VERBOSE
`ifdef OR1200_VERBOSE
// synopsys translate_off
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
                                $display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
// synopsys translate_on
// synopsys translate_on
`endif
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                pc = {ex_branch_addrtarget, 2'b00};
                                taken = 1'b1;
                                ex_branch_taken = 1'b1;
                        end
                        end
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
`ifdef OR1200_VERBOSE
// synopsys translate_off
// synopsys translate_off
                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
// synopsys translate_on
`endif
`endif
                        pc = epcr;
                        pc = epcr;
                        taken = 1'b1;
                        ex_branch_taken = 1'b1;
                end
                end
                {2'b01, 3'bxxx}: begin
                {2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
`ifdef OR1200_VERBOSE
// synopsys translate_off
// synopsys translate_off
                        $display("Starting exception: %h.", except_type);
                        $display("Starting exception: %h.", except_type);
// synopsys translate_on
// synopsys translate_on
`endif
`endif
                        pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
                        pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
                        taken = 1'b1;
                        ex_branch_taken = 1'b1;
                end
                end
                default: begin
                default: begin
`ifdef OR1200_VERBOSE
`ifdef OR1200_VERBOSE
// synopsys translate_off
// synopsys translate_off
                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
// synopsys translate_on
`endif
`endif
                        pc = spr_dat_i;
                        pc = spr_dat_i;
                        taken = 1'b0;
                        ex_branch_taken = 1'b0;
                end
                end
        endcase
        endcase
end
end
 
 
//
//
// PC register
// PC register
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        // default value 
//              pcreg <= #1 30'd63;
        if (rst) begin
                pcreg <= #1 ({(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
           //pcreg_default <= #1 30'd63;
        else if (spr_pc_we)
           pcreg_default <= #1 /*30'd63 */ `OR1200_BOOT_PCREG_DEFAULT; // jb
                pcreg <= #1 spr_dat_i[31:2];
           pcreg_select <= #1 1'b1;             // select async. value due to reset state
        else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
        end
//      else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
        // selected value (different from default) is written into FF after reset state
                pcreg <= #1 pc[31:2];
        else if (pcreg_select) begin
 
                pcreg_default <= #1 pcreg_boot[31:2];   // dynamic value can only be assigned to FF out of reset! 
 
                pcreg_select <= #1 1'b0;                // select FF value 
 
        end
 
        else if (spr_pc_we) begin
 
                pcreg_default <= #1 spr_dat_i[31:2];
 
        end
 
        else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) begin
 
                pcreg_default <= #1 pc[31:2];
 
        end
 
 
 
// select async. value for pcreg after reset - PC jumps to the address selected after boot! 
 
//assign  pcreg_boot = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1;
 
   assign  pcreg_boot = `OR1200_BOOT_ADR; // changed JB
 
 
 
always @(pcreg_boot or pcreg_default or pcreg_select)
 
    if (pcreg_select)
 
        pcreg = pcreg_boot[31:2];       // async. value is selected due to reset state 
 
    else
 
        pcreg = pcreg_default ;         // FF value is selected 2nd clock after reset state 
 
 
endmodule
endmodule
 
 
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