URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rfram_generic.v] - Diff between revs 258 and 358

Rev 258	Rev 358
Line 152...	Line 152...
`endfunction // get_gpr`	`endfunction // get_gpr`

`//`	`//`
`// Write port`	`// Write port`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst) begin`	if (rst == `OR1200_RST_VALUE) begin
`mem <= {512'h0, 512'h0};`	`mem <= {512'h0, 512'h0};`
`end`	`end`
`else if (ce_w & we_w)`	`else if (ce_w & we_w)`
`case (addr_w) // synopsys parallel_case`	`case (addr_w) // synopsys parallel_case`
`5'd01: mem[321+31:321] <= di_w;`	`5'd01: mem[321+31:321] <= di_w;`
Line 198...	Line 198...
`endcase`	`endcase`

`//`	`//`
`// Read port A`	`// Read port A`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst) begin`	if (rst == `OR1200_RST_VALUE) begin
`intaddr_a <= 5'h00;`	`intaddr_a <= 5'h00;`
`end`	`end`
`else if (ce_a)`	`else if (ce_a)`
`intaddr_a <= addr_a;`	`intaddr_a <= addr_a;`

Line 247...	Line 247...
`endcase`	`endcase`

`//`	`//`
`// Read port B`	`// Read port B`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst) begin`	if (rst == `OR1200_RST_VALUE) begin
`intaddr_b <= 5'h00;`	`intaddr_b <= 5'h00;`
`end`	`end`
`else if (ce_b)`	`else if (ce_b)`
`intaddr_b <= addr_b;`	`intaddr_b <= addr_b;`