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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 354 and 360

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//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
///                                                               //// 
////  ORPSoC Testbench                                            ////
 
/// ORPSoC testbench                                              ////
 
////                                                              ////
 
///                                                               ////
 
////  Description                                                 ////
 
/// Instantiate ORPSoC, monitors, provide stimulus                ////
 
////  ORPSoC Testbench file                                       ////
 
///                                                               ////
 
////                                                              ////
 
/// Julius Baxter, julius@opencores.org                           ////
 
////  To Do:                                                      ////
 
///                                                               ////
 
////                                                              ////
 
 
 
////                                                              ////
 
 
 
////  Author(s):                                                  ////
 
 
 
////      - jb, jb@orsoc.se                                       ////
 
 
 
////                                                              ////
 
 
 
////                                                              ////
 
 
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
 
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
 
////                                                              ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
//// the original copyright notice and the associated disclaimer. ////
Line 37... Line 31... 
//// Public License along with this source; if not, download it   ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
 
 
 
 
`include "timescale.v"
 
`include "orpsoc-defines.v"
 
`include "orpsoc_testbench_defines.v"
 
`include "orpsoc-testbench-defines.v"
 
 
 
`include "test-defines.v"
 
module orpsoc_testbench();
 
 
 
 
 
 
 
 
 
`include "timescale.v"
 
 
 
 
 
   reg clk;
 
module orpsoc_testbench;
 
   reg rst;
 
 
 
 
 
 
 
   // Setup global clock. Period defined in orpsoc_testbench_defines.v
 
   reg clk = 0;
 
   initial
 
   reg rst_n = 1; // Active LOW
 
     begin
 
 
 
        clk <= 0;
 
 
 
        rst <= 1;
 
 
 
     end
 
 
 
 
 
 
 
   always
 
   always
 
     begin
 
     #((`BOARD_CLOCK_PERIOD_NS)/2) clk <= ~clk;
 
        #((`CLOCK_PERIOD)/2) clk <= ~clk;
 
 
 
     end
 
 
 
 
 
 
 
   // Assert rst and then bring it low again
 
   // Reset, ACTIVE LOW
 
   initial
 
   initial
 
     begin
 
     begin
 
        repeat (2) @(negedge clk);
 
        #1;
 
        rst <= 0;
 
        repeat (32) @(negedge clk)
 
        repeat (16) @(negedge clk);
 
          rst_n <= 1;
 
        rst <= 1;
 
        repeat (32) @(negedge clk)
 
 
 
          rst_n <= 0;
 
 
 
        repeat (32) @(negedge clk)
 
 
 
          rst_n <= 1;
 
     end
 
     end
 
 
 
 
 
 
 
`include "orpsoc-params.v"
 
 
 
 
 
   // Wires for the dut
 
`ifdef JTAG_DEBUG
 
   wire spi_sd_sclk_o;
 
   wire                      tdo_pad_o;
 
   wire spi_sd_ss_o;
 
   wire                      tck_pad_i;
 
   wire spi_sd_miso_i;
 
   wire                      tms_pad_i;
 
   wire spi_sd_mosi_o;
 
   wire                      tdi_pad_i;
 
`ifdef USE_SDRAM
 
`endif
 
   wire [15:0] mem_dat_io;
 
`ifdef UART0
 
   wire [12:0] mem_adr_o;
 
   wire                      uart0_stx_pad_o;
 
   wire [1:0]  mem_dqm_o;
 
   wire                      uart0_srx_pad_i;
 
   wire [1:0]  mem_ba_o;
 
`endif
 
   wire        mem_cs_o;
 
 
 
   wire        mem_ras_o;
 
 
 
   wire        mem_cas_o;
 
 
 
   wire        mem_we_o;
 
 
 
   wire        mem_cke_o;
 
 
 
   wire        spi_flash_sclk_o;
 
 
 
   wire        spi_flash_ss_o;
 
 
 
   wire        spi_flash_miso_i;
 
 
 
   wire        spi_flash_mosi_o;
 
 
 
   wire        spi_flash_w_n_o;
 
 
 
   wire        spi_flash_hold_n_o;
 
 
 
`endif //  `ifdef USE_SDRAM
 
 
 
 
 
 
 
`ifdef USE_ETHERNET
 
 
 
   wire [1:1]  eth_sync_o;
 
 
 
   wire [1:1] eth_tx_o;
 
 
 
   wire [1:1] eth_rx_i;
 
 
 
   wire       eth_clk_i;
 
 
 
   wire [1:1] eth_md_io;
 
 
 
   wire [1:1] eth_mdc_o;
 
 
 
`endif
 
 
 
 
 
 
 
   wire       spi1_mosi_o;
 
 
 
   wire       spi1_miso_i;
 
 
 
   wire       spi1_ss_o;
 
 
 
   wire       spi1_sclk_o;
 
 
 
   wire [8-1:0] gpio_a_io;
 
 
 
   wire         uart0_srx_i;
 
 
 
   wire         uart0_stx_o;
 
 
 
   wire         dbg_tdi_i;
 
 
 
   wire         dbg_tck_i;
 
 
 
   wire         dbg_tms_i;
 
 
 
   wire         dbg_tdo_o;
 
 
 
   wire         rst_i;
 
 
 
   wire         rst_o;
 
 
 
   wire         clk_i;
 
 
 
 
 
 
 
 
 
 
 
   assign clk_i = clk;
 
 
 
   assign rst_i = rst;
 
 
 
 
 
 
 
   // Tie off some inputs   
 
 
   assign spi1_miso_i = 0;
 
 
 
   assign uart0_srx_i = 1;
 
 
 
 
 
 
 
 
 
 
 
   orpsoc_top dut
 
   orpsoc_top dut
 
     (
 
     (
 
      // Outputs
 
      .clk_pad_i                        (clk),
 
      .spi_sd_sclk_pad_o                        (spi_sd_sclk_o),
 
`ifdef JTAG_DEBUG
 
      .spi_sd_ss_pad_o                  (spi_sd_ss_o),
 
      .tms_pad_i                        (tms_pad_i),
 
      .spi_sd_mosi_pad_o                        (spi_sd_mosi_o),
 
      .tck_pad_i                        (tck_pad_i),
 
      .spi1_mosi_pad_o                  (spi1_mosi_o),
 
      .tdi_pad_i                        (tdi_pad_i),
 
      .spi1_ss_pad_o                    (spi1_ss_o),
 
      .tdo_pad_o                        (tdo_pad_o),
 
      .spi1_sclk_pad_o                  (spi1_sclk_o),
 
`endif
 
      .uart0_stx_pad_o                  (uart0_stx_o),
 
`ifdef UART0
 
      .dbg_tdo_pad_o                    (dbg_tdo_o),
 
      .uart0_stx_pad_o                  (uart0_stx_pad_o),
 
      .rst_pad_o                                (rst_o),
 
      .uart0_srx_pad_i                  (uart0_srx_pad_i),
 
      .gpio_a_pad_io                    (gpio_a_io[8-1:0]),
 
 
 
      // Inputs
 
 
 
      .spi_sd_miso_pad_i                        (spi_sd_miso_i),
 
 
 
      .spi1_miso_pad_i                  (spi1_miso_i),
 
 
 
      .uart0_srx_pad_i                  (uart0_srx_i),
 
 
 
      .dbg_tdi_pad_i                    (dbg_tdi_i),
 
 
 
      .dbg_tck_pad_i                    (dbg_tck_i),
 
 
 
      .dbg_tms_pad_i                    (dbg_tms_i),
 
 
 
`ifdef USE_ETHERNET
 
 
 
      // Ethernet ports
 
 
 
      .eth_md_pad_io                    (eth_md_io[1:1]),
 
 
 
      .eth_mdc_pad_o                    (eth_mdc_o[1:1]),
 
 
 
      .eth_sync_pad_o                   (eth_sync_o[1:1]),
 
 
 
      .eth_tx_pad_o                     (eth_tx_o[1:1]),
 
 
 
      .eth_rx_pad_i                     (eth_rx_i[1:1]),
 
 
 
      .eth_clk_pad_i                    (eth_clk_i),
 
 
 
`endif  //  `ifdef USE_ETHERNET      
 
 
      // SDRAM and flash memory ports
 
 
 
`ifdef USE_SDRAM
 
 
 
      .mem_dat_pad_io                   (mem_dat_io[15:0]),
 
 
 
      .mem_adr_pad_o                    (mem_adr_o[12:0]),
 
 
 
      .mem_dqm_pad_o                    (mem_dqm_o[1:0]),
 
 
 
      .mem_ba_pad_o                     (mem_ba_o[1:0]),
 
 
 
      .mem_cs_pad_o                     (mem_cs_o),
 
 
 
      .mem_ras_pad_o                    (mem_ras_o),
 
 
 
      .mem_cas_pad_o                    (mem_cas_o),
 
 
 
      .mem_we_pad_o                     (mem_we_o),
 
 
 
      .mem_cke_pad_o                    (mem_cke_o),
 
 
 
      .spi_flash_sclk_pad_o             (spi_flash_sclk_o),
 
 
 
      .spi_flash_ss_pad_o                       (spi_flash_ss_o),
 
 
 
      .spi_flash_mosi_pad_o             (spi_flash_mosi_o),
 
 
 
      .spi_flash_w_n_pad_o                      (spi_flash_w_n_o),
 
 
 
      .spi_flash_hold_n_pad_o           (spi_flash_hold_n_o),
 
 
 
      .spi_flash_miso_pad_i             (spi_flash_miso_i),
 
 
 
`endif
 
`endif
 
      .rst_pad_i                                (rst_i),
 
      .rst_n_pad_i                      (rst_n)
 
      .clk_pad_i                                (clk_i));
 
      );
 
 
 
 
 
`ifdef VPI_DEBUG_ENABLE
 
   //
 
   // Debugging interface
 
   // Instantiate OR1200 monitor
 
   vpi_debug_module vpi_dbg(
 
   //
 
                            .tms(dbg_tms_i),
 
   or1200_monitor monitor();
 
                            .tck(dbg_tck_i),
 
 
 
                            .tdi(dbg_tdi_i),
 
 
 
                            .tdo(dbg_tdo_o));
 
 
 
`else
 
 
 
   // If no VPI debugging, tie off JTAG inputs
 
 
 
   assign dbg_tdi_i = 1;
 
 
 
   assign dbg_tck_i = 0;
 
 
 
   assign dbg_tms_i = 1;
 
 
 
`endif
 
 
 
 
 
 
 
 
 
`ifndef SIM_QUIET
 
 
 
 `define CPU_ic_top or1200_ic_top
 
 
 
 `define CPU_dc_top or1200_dc_top
 
 
 
   wire ic_en = orpsoc_testbench.dut.or1200_top.or1200_ic_top.ic_en;
 
 
 
   always @(posedge ic_en)
 
 
 
     $display("Or1200 IC enabled at %t", $time);
 
 
 
 
 
 
 
   wire dc_en = orpsoc_testbench.dut.or1200_top.or1200_dc_top.dc_en;
 
 
 
   always @(posedge dc_en)
 
 
 
     $display("Or1200 DC enabled at %t", $time);
 
 
 
`endif
 
 
 
 
 
   // External memories, if enabled
 
 
 
`ifdef USE_SDRAM
 
 
 
   // SPI Flash
 
 
 
   AT26DFxxx spi_flash
 
 
 
     (
 
 
 
      // Outputs
 
 
 
      .SO                                       (spi_flash_miso_i),
 
 
 
      // Inputs
 
 
 
      .CSB                                      (spi_flash_ss_o),
 
 
 
      .SCK                                      (spi_flash_sclk_o),
 
 
 
      .SI                                       (spi_flash_mosi_o),
 
 
 
      .WPB                                      (spi_flash_w_n_o)
 
 
 
      //.HOLDB                          (spi_flash_hold_n_o)
 
 
 
      );
 
 
 
 
 
 
 
   // SDRAM
 
`ifdef JTAG_DEBUG
 
   mt48lc16m16a2 sdram
 
 `ifdef VPI_DEBUG
 
 
 
   // Debugging interface
 
 
 
   vpi_debug_module vpi_dbg
 
     (
 
     (
 
      // Inouts
 
      .tms(tms_pad_i),
 
      .Dq                                       (mem_dat_io),
 
      .tck(tck_pad_i),
 
      // Inputs
 
      .tdi(tdi_pad_i),
 
      .Addr                             (mem_adr_o),
 
      .tdo(tdo_pad_o)
 
      .Ba                                       (mem_ba_o),
 
      );
 
      .Clk                                      (clk_i),
 
 `else
 
      .Cke                                      (mem_cke_o),
 
   // If no VPI debugging, tie off JTAG inputs
 
      .Cs_n                             (mem_cs_o),
 
   assign tdi_pad_i = 1;
 
      .Ras_n                            (mem_ras_o),
 
   assign tck_pad_i = 0;
 
      .Cas_n                            (mem_cas_o),
 
   assign tms_pad_i = 1;
 
      .We_n                             (mem_we_o),
 
 `endif // !`ifdef VPI_DEBUG_ENABLE
 
      .Dqm                                      (mem_dqm_o));
 
`endif //  `ifdef JTAG_DEBUG
 
 
 
 
 
`endif // !`ifdef USE_SDRAM
 
 
 
 
 
 
 
`ifdef USE_ETHERNET
 
 
 
 
 
 
 
   reg          eth_clk;
 
 
 
   initial
 
   initial
 
     eth_clk <= 0;
 
     begin
 
 
 
`ifndef SIM_QUIET
 
   always
 
        $display("\n* Starting simulation of design RTL.\n* Test: %s\n",
 
     #(8/2) eth_clk <= ~eth_clk; // 125 Mhz clock
 
                 `TEST_NAME_STRING );
 
 
 
`endif
 
   assign eth_clk_i = eth_clk;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   wire [3:0]            ethphy_mii_tx_d;
 
`ifdef VCD
 
   wire                 ethphy_mii_tx_en;
 
 `ifdef VCD_DELAY
 
   wire                 ethphy_mii_tx_err;
 
        #(`VCD_DELAY);
 
   wire                 mcoll_o;
 
 `endif
 
   wire                 mcrs_o;
 
 
 
   wire                 md_io;
 
 
 
   wire                 mrx_clk_o;
 
 
 
   wire [3:0]            mrxd_o;
 
 
 
   wire                 mrxdv_o;
 
 
 
   wire                 mrxerr_o;
 
 
 
   wire                 mtx_clk_o;
 
 
 
   wire                 smii_rx;
 
 
 
   wire                 fast_ethernet, duplex, link;
 
 
 
 
 
 
 
   /* Converts SMII back to MII */
 
        // Delay by x insns
 
   smii_phy smii_phyend
 
 `ifdef VCD_DELAY_INSNS
 
     (
 
        #10; // Delay until after the value becomes valid
 
      // Outputs
 
        while (monitor.insns < `VCD_DELAY_INSNS)
 
      .smii_rx                          (eth_rx_i[1:1]), /* SMII RX */
 
          @(posedge clk);
 
      .ethphy_mii_tx_d                  (ethphy_mii_tx_d[3:0]), /* MII TX */
 
 
 
      .ethphy_mii_tx_en                 (ethphy_mii_tx_en),     /* MII TX */
 
 
 
      .ethphy_mii_tx_err                (ethphy_mii_tx_err),    /* MII TX */
 
 
 
      // Inputs
 
 
 
      .smii_tx                          (eth_tx_o[1:1]),        /* SMII TX */
 
 
 
      .smii_sync                        (eth_sync_o[1:1]),      /* SMII SYNC */
 
 
 
      .ethphy_mii_tx_clk                (mtx_clk_o),            /* MII TX */
 
 
 
 
 
 
 
      .ethphy_mii_rx_d                  (mrxd_o[3:0]), /* MII RX */
 
 
 
      .ethphy_mii_rx_dv                 (mrxdv_o),     /* MII RX */
 
 
 
      .ethphy_mii_rx_err                (mrxerr_o),    /* MII RX */
 
 
 
      .ethphy_mii_rx_clk                (mrx_clk_o),   /* MII RX */
 
 
 
 
 
 
 
      .ethphy_mii_mcoll                 (),
 
 
 
      .ethphy_mii_crs                   (mcrs_o),
 
 
 
      .fast_ethernet                    (fast_ethernet),
 
 
 
      .duplex                           (duplex),
 
 
 
      .link                             (link),
 
 
 
      .clk                              (eth_clk_i),
 
 
 
      .rst_n                            (rst_i));
 
 
 
 
 
 
 
`ifdef ENABLE_ETH_STIM
 
 
 
   /* Generates an RX packet */
 
 
 
 `include "eth_stim.v"
 
 
 
`endif
 
`endif
 
 
 
 
 
   eth_phy eth_phy0
 
 `ifdef SIMULATOR_MODELSIM
 
     (
 
        // Modelsim can GZip VCDs on the fly if given in the suffix
 
      // Outputs
 
  `define VCD_SUFFIX   ".vcd.gz"
 
      .mtx_clk_o                        (mtx_clk_o),
 
 `else
 
      .mrx_clk_o                        (mrx_clk_o),
 
  `define VCD_SUFFIX   ".vcd"
 
      .mrxd_o                           (mrxd_o[3:0]),
 
 `endif
 
      .mrxdv_o                          (mrxdv_o),
 
 
 
      .mrxerr_o                         (mrxerr_o),
 
 
 
      .mcoll_o                          (mcoll_o),
 
 
 
      .mcrs_o                           (mcrs_o),
 
 
 
      // Sideband outputs for smii converter --jb
 
 
 
      .link_o                             (link),
 
 
 
      .speed_o                            (fast_ethernet),
 
 
 
      .duplex_o                           (duplex),
 
 
 
      // Inouts
 
 
 
      .md_io                            (eth_md_io[1:1]),
 
 
 
      // Inputs
 
 
 
      .m_rst_n_i                        (rst_i),
 
 
 
      .mtxd_i                           (ethphy_mii_tx_d[3:0]),
 
 
 
      .mtxen_i                          (ethphy_mii_tx_en),
 
 
 
      .mtxerr_i                         (ethphy_mii_tx_err),
 
 
 
      .mdc_i                            (eth_mdc_o[1:1]));
 
 
 
 
 
 
 
`endif //  `ifdef USE_ETHERNET
 
`ifndef SIM_QUIET
 
 
 
        $display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 
 
 
`endif
 
 
 
        $dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 
 
 
 `ifndef VCD_DEPTH
 
 
 
  `define VCD_DEPTH 0
 
 
 
 `endif
 
 
 
        $dumpvars(`VCD_DEPTH);
 
 
 
`endif
 
 
 
 
 
 
 
   end // initial begin
 
 
 
 
 
initial
 
`ifdef END_TIME
 
  begin
 
   initial begin
 
     $display("\nStarting RTL simulation of %s test\n", `TEST_NAME_STRING);
 
      #(`END_TIME);
 
`ifdef USE_SDRAM
 
`ifndef SIM_QUIET
 
     $display("Using SDRAM - loading application from SPI flash memory\n");
 
      $display("* Finish simulation due to END_TIME being set at %t", $time);
 
 
 
`endif
 
 
 
      $finish;
 
 
 
   end
 
`endif
 
`endif
 
 
 
 
 
`ifdef VCD
 
`ifdef END_INSNS
 
     $display("VCD in %s\n", {`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
 
   initial begin
 
     $dumpfile({`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
 
      #10
 
     $dumpvars(0);
 
        while (monitor.insns < `END_INSNS)
 
 
 
          @(posedge clk);
 
 
 
 `ifndef SIM_QUIET
 
 
 
      $display("* Finish simulation due to END_INSNS count (%d) reached at %t",
 
 
 
               `END_INSNS, $time);
 
`endif
 
`endif
 
 
 
      $finish;
 
  end
 
  end
 
 
 
`endif
 
 
 
 
 
   // Instantiate the monitor
 
`ifdef UART0
 
   or1200_monitor monitor();
 
   //   
 
 
   // UART0 decoder
 
   // If we're using UART for printf output, include the
 
   //   
   // UART decoder
 
 
 
`ifdef UART_PRINTF
 
 
 
   uart_decoder
 
   uart_decoder
 
     #(
 
     #(
 
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
 
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
 
        )
 
        )
 
   uart0_decoder
 
   uart0_decoder
 
     (
 
     (
 
      .clk(clk),
 
      .clk(clk),
 
      .uart_tx(uart0_stx_o)
 
      .uart_tx(uart0_stx_pad_o)
 
 
 
      );
 
 
 
 
 
 
 
   // UART0 stimulus
 
 
 
   uart_stim
 
 
 
     #(
 
 
 
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
 
 
 
        )
 
 
 
   uart0_stim
 
 
 
     (
 
 
 
      .clk(clk),
 
 
 
      .uart_rx(uart0_srx_pad_i)
 
      );
 
      );
 
`endif
 
 
 
 
 
`endif //  `ifdef UART0
 
 
 
 
 
endmodule // orpsoc_testbench
 
endmodule // orpsoc_testbench
 
 
 
 
 
// Local Variables:
 
// Local Variables:
 
// verilog-library-files:("../../rtl/verilog/orpsoc_top.v")
 
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
 
// verilog-library-directories:("." "../../rtl/verilog")
 
// verilog-library-files:()
 
 
 
// verilog-library-extensions:(".v" ".h")
 
// End:
 
// End:
 
 
 
 
 
 No newline at end of file
 
 No newline at end of file
 
 
 
 
 
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