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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 962 and 977

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Rev 962 Rev 977
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.18  2002/08/15 06:04:11  lampret
 
// Fixed Xilinx trace buffer address. REported by Taylor Su.
 
//
// Revision 1.17  2002/08/12 05:31:44  lampret
// Revision 1.17  2002/08/12 05:31:44  lampret
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
//
//
// Revision 1.16  2002/07/14 22:17:17  lampret
// Revision 1.16  2002/07/14 22:17:17  lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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// undefine this macro.
// undefine this macro.
//
//
//`define OR1200_WB_RETRY 7
//`define OR1200_WB_RETRY 7
 
 
//
//
 
// Store buffer
 
//
 
// It will improve performance by "caching" CPU stores
 
// using store buffer. This is most important for function
 
// prologues because DC can only work in write though mode
 
// and all stores would have to complete external WB writes
 
// to memory.
 
// Store buffer is between DC and data BIU.
 
// All stores will be stored into store buffer and immediately
 
// completed by the CPU, even though actual external writes
 
// will be performed later. As a consequence store buffer masks
 
// all data bus errors related to stores (data bus errors
 
// related to loads are delivered normally).
 
// All pending CPU loads will wait until store buffer is empty to
 
// ensure strict memory model. Right now this is necessary because
 
// we don't make destinction between cached and cache inhibited
 
// address space, so we simply empty store buffer until loads
 
// can begin.
 
//
 
`define OR1200_SB_IMPLEMENTED
 
 
 
//
// Enable additional synthesis directives if using
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
// _Synopsys_ synthesis tool
//
//
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
 
 

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