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https://opencores.org/ocsvn/or1k/or1k/trunk
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Rev 428 |
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Line 126... |
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This section configures Instruction Memory Menangement Unit
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This section configures Instruction Memory Menangement Unit
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enabled = 0/1
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enabled = 0/1
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whether IMMU is enabled
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whether IMMU is enabled
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(NOTE: UPR bit is set)
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nsets =
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nsets =
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number of ITLB sets; must be power of two
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number of ITLB sets; must be power of two
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nways =
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nways =
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Line 148... |
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section immu
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section immu
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enabled = 0
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enabled = 0
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nsets = 32
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nsets = 32
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nways = 1
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nways = 1
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pagesize = 4096
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pagesize = 8192
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end
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end
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/* DMMU SECTION
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/* DMMU SECTION
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This section configures Data Memory Menangement Unit
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This section configures Data Memory Menangement Unit
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enabled = 0/1
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enabled = 0/1
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whether DMMU is enabled
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whether DMMU is enabled
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(NOTE: UPR bit is set)
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nsets =
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nsets =
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number of DTLB sets; must be power of two
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number of DTLB sets; must be power of two
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nways =
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nways =
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Line 179... |
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section dmmu
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section dmmu
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enabled = 0
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enabled = 0
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nsets = 32
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nsets = 32
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nways = 1
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nways = 1
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pagesize = 4096
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pagesize = 8192
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end
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/* IC SECTION
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This section configures Instruction Cache
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enabled = 0/1
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whether IC is enabled
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(NOTE: UPR bit is set)
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nsets =
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number of IC sets; must be power of two
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nways =
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number of IC ways
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blocksize =
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IC block size in bytes; must be power of two
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ustates =
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number of IC usage states (2, 3, 4 etc., max is 4)
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*/
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section ic
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enabled = 0
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nsets = 512
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nways = 1
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blocksize = 16
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end
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/* DC SECTION
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This section configures Data Cache
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enabled = 0/1
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whether DC is enabled
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(NOTE: UPR bit is set)
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nsets =
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number of DC sets; must be power of two
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nways =
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number of DC ways
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blocksize =
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DC block size in bytes; must be power of two
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ustates =
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number of DC usage states (2, 3, 4 etc., max is 4)
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*/
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section dc
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enabled = 0
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nsets = 512
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nways = 1
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blocksize = 16
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end
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end
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/* SIM SECTION
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/* SIM SECTION
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This section specifies how should sim behave.
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This section specifies how should sim behave.
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