| Line 1... |
Line 1... |
/* immu.c -- Instruction MMU simulation
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/* immu.c -- Instruction MMU simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is free software; you can redistribute it and/or modify
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This program is distributed in the hope that it will be useful, but WITHOUT
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it under the terms of the GNU General Public License as published by
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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the Free Software Foundation; either version 2 of the License, or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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(at your option) any later version.
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more details.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* IMMU model, perfectly functional. */
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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/* System includes */
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#include <inttypes.h>
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#include <stdlib.h>
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#endif
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#include "port.h"
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/* Package includes */
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#include "arch.h"
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#include "immu.h"
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#include "immu.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "opcode/or32.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "debug.h"
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#include "stats.h"
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#include "stats.h"
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#include "sprs.h"
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#include "except.h"
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#include "except.h"
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#include "sim-config.h"
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#include "spr-dump.h"
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#include "debug.h"
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#include "misc.h"
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#include "misc.h"
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#include "sim-cmd.h"
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DEFAULT_DEBUG_CHANNEL(immu);
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DEFAULT_DEBUG_CHANNEL(immu);
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struct immu *immu_state;
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struct immu *immu_state;
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/* Insn MMU */
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/* Insn MMU */
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static inline uorreg_t *immu_find_tlbmr(oraddr_t virtaddr,
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static uorreg_t *
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uorreg_t **itlbmr_lru,
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immu_find_tlbmr (oraddr_t virtaddr, uorreg_t ** itlbmr_lru, struct immu *immu)
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struct immu *immu)
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{
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{
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int set;
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int set;
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int i;
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int i;
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oraddr_t vpn;
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oraddr_t vpn;
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uorreg_t *itlbmr;
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uorreg_t *itlbmr;
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| Line 62... |
Line 64... |
itlbmr = &cpu_state.sprs[SPR_ITLBMR_BASE(0) + set];
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itlbmr = &cpu_state.sprs[SPR_ITLBMR_BASE(0) + set];
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*itlbmr_lru = itlbmr;
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*itlbmr_lru = itlbmr;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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/* FIXME: Should this be reversed? */
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/* FIXME: Should this be reversed? */
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for(i = immu->nways; i; i--, itlbmr += (128 * 2)) {
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for (i = immu->nways; i; i--, itlbmr += (128 * 2))
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{
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if(((*itlbmr & immu->vpn_mask) == vpn) && (*itlbmr & SPR_ITLBMR_V))
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if(((*itlbmr & immu->vpn_mask) == vpn) && (*itlbmr & SPR_ITLBMR_V))
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return itlbmr;
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return itlbmr;
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}
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}
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return NULL;
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return NULL;
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}
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}
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oraddr_t immu_translate(oraddr_t virtaddr)
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oraddr_t
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immu_translate (oraddr_t virtaddr)
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{
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{
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int i;
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int i;
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uorreg_t *itlbmr;
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uorreg_t *itlbmr;
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uorreg_t *itlbtr;
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uorreg_t *itlbtr;
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uorreg_t *itlbmr_lru;
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uorreg_t *itlbmr_lru;
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struct immu *immu = immu_state;
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struct immu *immu = immu_state;
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))
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{
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insn_ci = (virtaddr >= 0x80000000);
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insn_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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}
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itlbmr = immu_find_tlbmr(virtaddr, &itlbmr_lru, immu);
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itlbmr = immu_find_tlbmr(virtaddr, &itlbmr_lru, immu);
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if(itlbmr) { /* Yes, we did. */
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if (itlbmr)
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{ /* Yes, we did. */
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immu_stats.fetch_tlbhit++;
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immu_stats.fetch_tlbhit++;
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TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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itlbtr = itlbmr + 128;
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itlbtr = itlbmr + 128;
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/* Set LRUs */
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/* Set LRUs */
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for(i = 0; i < immu->nways; i++, itlbmr_lru += (128 * 2)) {
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for (i = 0; i < immu->nways; i++, itlbmr_lru += (128 * 2))
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{
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if(*itlbmr_lru & SPR_ITLBMR_LRU)
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if(*itlbmr_lru & SPR_ITLBMR_LRU)
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*itlbmr_lru = (*itlbmr_lru & ~SPR_ITLBMR_LRU) |
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*itlbmr_lru = (*itlbmr_lru & ~SPR_ITLBMR_LRU) |
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((*itlbmr_lru & SPR_ITLBMR_LRU) - 0x40);
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((*itlbmr_lru & SPR_ITLBMR_LRU) - 0x40);
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}
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}
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| Line 112... |
Line 119... |
insn_ci = *itlbtr & SPR_ITLBTR_CI;
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insn_ci = *itlbtr & SPR_ITLBTR_CI;
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runtime.sim.mem_cycles += immu->hitdelay;
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runtime.sim.mem_cycles += immu->hitdelay;
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/* Test for page fault */
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/* Test for page fault */
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
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{
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if (!(*itlbtr & SPR_ITLBTR_SXE))
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if (!(*itlbtr & SPR_ITLBTR_SXE))
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except_handle(EXCEPT_IPF, virtaddr);
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except_handle(EXCEPT_IPF, virtaddr);
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} else {
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}
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else
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{
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if (!(*itlbtr & SPR_ITLBTR_UXE))
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if (!(*itlbtr & SPR_ITLBTR_UXE))
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except_handle(EXCEPT_IPF, virtaddr);
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except_handle(EXCEPT_IPF, virtaddr);
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}
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}
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TRACE("Returning physical address %"PRIxADDR"\n",
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TRACE("Returning physical address %"PRIxADDR"\n",
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(*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->page_offset_mask));
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(*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->
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page_offset_mask));
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return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->page_offset_mask);
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return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->page_offset_mask);
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}
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}
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/* No, we didn't. */
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/* No, we didn't. */
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immu_stats.fetch_tlbmiss++;
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immu_stats.fetch_tlbmiss++;
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#if 0
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#if 0
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for (i = 0; i < immu->nways; i++)
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for (i = 0; i < immu->nways; i++)
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if (((cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_LRU) >> 6) < minlru)
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if (((cpu_state.sprs[SPR_ITLBMR_BASE (i) + set] & SPR_ITLBMR_LRU) >> 6) <
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minlru)
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minway = i;
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minway = i;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] &= ~SPR_ITLBMR_VPN;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] &= ~SPR_ITLBMR_VPN;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] |= vpn << 12;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] |= vpn << 12;
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for (i = 0; i < immu->nways; i++) {
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for (i = 0; i < immu->nways; i++)
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{
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uorreg_t lru = cpu_state.sprs[SPR_ITLBMR_BASE(i) + set];
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uorreg_t lru = cpu_state.sprs[SPR_ITLBMR_BASE(i) + set];
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if (lru & SPR_ITLBMR_LRU) {
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if (lru & SPR_ITLBMR_LRU)
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{
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lru = (lru & ~SPR_ITLBMR_LRU) | ((lru & SPR_ITLBMR_LRU) - 0x40);
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lru = (lru & ~SPR_ITLBMR_LRU) | ((lru & SPR_ITLBMR_LRU) - 0x40);
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cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] = lru;
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cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] = lru;
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}
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}
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}
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}
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] &= ~SPR_ITLBMR_LRU;
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] &= ~SPR_ITLBMR_LRU;
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| Line 169... |
Line 183... |
*
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*
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* RTRN: 0 - no IMMU, IMMU disabled or ITLB miss
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* RTRN: 0 - no IMMU, IMMU disabled or ITLB miss
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* else - appropriate PA (note it IMMU is not present
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* else - appropriate PA (note it IMMU is not present
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* PA === EA)
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* PA === EA)
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*/
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*/
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oraddr_t peek_into_itlb(oraddr_t virtaddr)
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oraddr_t
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peek_into_itlb (oraddr_t virtaddr)
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{
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{
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uorreg_t *itlbmr;
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uorreg_t *itlbmr;
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uorreg_t *itlbtr;
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uorreg_t *itlbtr;
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uorreg_t *itlbmr_lru;
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uorreg_t *itlbmr_lru;
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struct immu *immu = immu_state;
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struct immu *immu = immu_state;
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))
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{
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return(virtaddr);
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return(virtaddr);
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}
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}
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itlbmr = immu_find_tlbmr(virtaddr, &itlbmr_lru, immu);
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itlbmr = immu_find_tlbmr(virtaddr, &itlbmr_lru, immu);
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if(itlbmr) { /* Yes, we did. */
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if (itlbmr)
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{ /* Yes, we did. */
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itlbtr = itlbmr + 128;
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itlbtr = itlbmr + 128;
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/* Test for page fault */
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/* Test for page fault */
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
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if (!(*itlbtr & SPR_ITLBTR_SXE)) {
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{
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if (!(*itlbtr & SPR_ITLBTR_SXE))
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{
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/* no luck, giving up */
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/* no luck, giving up */
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return(0);
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return(0);
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}
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}
|
} else {
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}
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if (!(*itlbtr & SPR_ITLBTR_UXE)) {
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else
|
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{
|
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if (!(*itlbtr & SPR_ITLBTR_UXE))
|
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{
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/* no luck, giving up */
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/* no luck, giving up */
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return(0);
|
return(0);
|
}
|
}
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}
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}
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| Line 221... |
Line 243... |
- find lru way and entry and invoke ITLB miss exception handler
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- find lru way and entry and invoke ITLB miss exception handler
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- set 'lru' with immu->ustates - 1 and decrement 'lru' of other
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- set 'lru' with immu->ustates - 1 and decrement 'lru' of other
|
ways unless they have reached 0
|
ways unless they have reached 0
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*/
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*/
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static void itlb_status(void *dat)
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static void
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itlb_status (void *dat)
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{
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{
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struct immu *immu = dat;
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struct immu *immu = dat;
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int set;
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int set;
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int way;
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int way;
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int end_set = immu->nsets;
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int end_set = immu->nsets;
|
|
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))
|
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{
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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return;
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return;
|
}
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}
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|
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if (0 < end_set) PRINTF("\nIMMU: ");
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if (0 < end_set)
|
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PRINTF ("\nIMMU: ");
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/* Scan set(s) and way(s). */
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/* Scan set(s) and way(s). */
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for (set = 0; set < end_set; set++) {
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for (set = 0; set < end_set; set++)
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for (way = 0; way < immu->nways; way++) {
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{
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for (way = 0; way < immu->nways; way++)
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{
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PRINTF("%s\n", dump_spr(SPR_ITLBMR_BASE(way) + set,
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PRINTF("%s\n", dump_spr(SPR_ITLBMR_BASE(way) + set,
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set]));
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cpu_state.sprs[SPR_ITLBMR_BASE (way) +
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PRINTF("%s\n", dump_spr(SPR_ITLBTR_BASE(way) + set,
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set]));
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PRINTF ("%s\n",
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dump_spr (SPR_ITLBTR_BASE (way) + set,
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cpu_state.sprs[SPR_ITLBTR_BASE(way) + set]));
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cpu_state.sprs[SPR_ITLBTR_BASE(way) + set]));
|
}
|
}
|
}
|
}
|
if (0 < end_set) PRINTF("\n");
|
if (0 < end_set)
|
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PRINTF ("\n");
|
}
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}
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|
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/*---------------------------------------------------[ IMMU configuration ]---*/
|
/*---------------------------------------------------[ IMMU configuration ]---*/
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static void immu_enabled(union param_val val, void *dat)
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|
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/*---------------------------------------------------------------------------*/
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/*!Enable or disable the IMMU
|
|
|
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Set the corresponding field in the UPR
|
|
|
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@param[in] val The value to use
|
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@param[in] dat The config data structure */
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/*---------------------------------------------------------------------------*/
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static void
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immu_enabled (union param_val val, void *dat)
|
{
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{
|
struct immu *immu = dat;
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struct immu *immu = dat;
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|
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if(val.int_val)
|
if(val.int_val)
|
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{
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_IMP;
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_IMP;
|
|
}
|
else
|
else
|
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{
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;
|
|
}
|
|
|
immu->enabled = val.int_val;
|
immu->enabled = val.int_val;
|
}
|
}
|
|
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static void immu_nsets(union param_val val, void *dat)
|
|
|
/*---------------------------------------------------------------------------*/
|
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/*!Set the number of DMMU sets
|
|
|
|
Value must be a power of 2 <= 256. Ignore any other values with a
|
|
warning. Set the corresponding IMMU configuration flags.
|
|
|
|
@param[in] val The value to use
|
|
@param[in] dat The config data structure */
|
|
/*---------------------------------------------------------------------------*/
|
|
static void
|
|
immu_nsets (union param_val val,
|
|
void *dat)
|
{
|
{
|
struct immu *immu = dat;
|
struct immu *immu = dat;
|
|
|
if (is_power2(val.int_val) && val.int_val <= 256) {
|
if (is_power2 (val.int_val) && (val.int_val <= 128))
|
|
{
|
|
int set_bits = log2_int (val.int_val);
|
|
|
immu->nsets = val.int_val;
|
immu->nsets = val.int_val;
|
|
|
cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;
|
cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;
|
cpu_state.sprs[SPR_IMMUCFGR] |= log2_int(val.int_val) << 3;
|
cpu_state.sprs[SPR_IMMUCFGR] |= set_bits << SPR_IMMUCFGR_NTS_OFF;
|
}
|
}
|
else
|
else
|
CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
|
{
|
|
fprintf (stderr, "Warning IMMU nsets not a power of 2 <= 128: ignored\n");
|
}
|
}
|
|
} /* immu_nsets() */
|
|
|
static void immu_nways(union param_val val, void *dat)
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Set the number of IMMU ways
|
|
|
|
Value must be in the range 1-4. Ignore other values with a warning. Set
|
|
the corresponding IMMU configuration flags.
|
|
|
|
@param[in] val The value to use
|
|
@param[in] dat The config data structure */
|
|
/*---------------------------------------------------------------------------*/
|
|
static void
|
|
immu_nways (union param_val val,
|
|
void *dat)
|
{
|
{
|
struct immu *immu = dat;
|
struct immu *immu = dat;
|
|
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
if (val.int_val >= 1 && val.int_val <= 4)
|
|
{
|
|
int way_bits = val.int_val - 1;
|
|
|
immu->nways = val.int_val;
|
immu->nways = val.int_val;
|
|
|
cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;
|
cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;
|
cpu_state.sprs[SPR_IMMUCFGR] |= val.int_val - 1;
|
cpu_state.sprs[SPR_IMMUCFGR] |= way_bits << SPR_IMMUCFGR_NTW_OFF;
|
}
|
}
|
else
|
else
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
{
|
|
fprintf (stderr, "Warning IMMU nways not in range 1-4: ignored\n");
|
}
|
}
|
|
} /* immu_nways() */
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Set the IMMU page size
|
|
|
static void immu_pagesize(union param_val val, void *dat)
|
Value must be a power of 2. Ignore other values with a warning
|
|
|
|
@param[in] val The value to use
|
|
@param[in] dat The config data structure */
|
|
/*---------------------------------------------------------------------------*/
|
|
static void
|
|
immu_pagesize (union param_val val,
|
|
void *dat)
|
{
|
{
|
struct immu *immu = dat;
|
struct immu *immu = dat;
|
|
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
|
{
|
immu->pagesize = val.int_val;
|
immu->pagesize = val.int_val;
|
|
}
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
{
|
|
fprintf (stderr, "Warning IMMU page size must be power of 2: ignored\n");
|
}
|
}
|
|
} /* immu_pagesize() */
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Set the IMMU entry size
|
|
|
static void immu_entrysize(union param_val val, void *dat)
|
Value must be a power of 2. Ignore other values with a warning
|
|
|
|
@param[in] val The value to use
|
|
@param[in] dat The config data structure */
|
|
/*---------------------------------------------------------------------------*/
|
|
static void
|
|
immu_entrysize (union param_val val,
|
|
void *dat)
|
{
|
{
|
struct immu *immu = dat;
|
struct immu *immu = dat;
|
|
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
|
{
|
immu->entrysize = val.int_val;
|
immu->entrysize = val.int_val;
|
|
}
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
{
|
|
fprintf (stderr, "Warning IMMU entry size must be power of 2: ignored\n");
|
}
|
}
|
|
} /* immu_entrysize() */
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Set the number of IMMU usage states
|
|
|
static void immu_ustates(union param_val val, void *dat)
|
Value must be 2, 3 or 4. Ignore other values with a warning
|
|
|
|
@param[in] val The value to use
|
|
@param[in] dat The config data structure */
|
|
/*---------------------------------------------------------------------------*/
|
|
static void
|
|
immu_ustates (union param_val val,
|
|
void *dat)
|
{
|
{
|
struct immu *immu = dat;
|
struct immu *immu = dat;
|
|
|
if (val.int_val >= 2 && val.int_val <= 4)
|
if ((val.int_val >= 2) && (val.int_val <= 4))
|
|
{
|
immu->ustates = val.int_val;
|
immu->ustates = val.int_val;
|
|
}
|
else
|
else
|
CONFIG_ERROR("invalid USTATE.");
|
{
|
|
fprintf (stderr, "Warning number of IMMU usage states must be 2, 3 or 4:"
|
|
"ignored\n");
|
}
|
}
|
|
} /* immu_ustates() */
|
|
|
|
|
static void immu_missdelay(union param_val val, void *dat)
|
static void
|
|
immu_missdelay (union param_val val, void *dat)
|
{
|
{
|
struct immu *immu = dat;
|
struct immu *immu = dat;
|
|
|
immu->missdelay = val.int_val;
|
immu->missdelay = val.int_val;
|
}
|
}
|
|
|
static void immu_hitdelay(union param_val val, void *dat)
|
static void
|
|
immu_hitdelay (union param_val val, void *dat)
|
{
|
{
|
struct immu *immu = dat;
|
struct immu *immu = dat;
|
|
|
immu->hitdelay = val.int_val;
|
immu->hitdelay = val.int_val;
|
}
|
}
|
|
|
static void *immu_start_sec(void)
|
/*---------------------------------------------------------------------------*/
|
|
/*!Initialize a new DMMU configuration
|
|
|
|
ALL parameters are set explicitly to default values. */
|
|
/*---------------------------------------------------------------------------*/
|
|
static void *
|
|
immu_start_sec ()
|
{
|
{
|
struct immu *immu;
|
struct immu *immu;
|
|
int set_bits;
|
|
int way_bits;
|
|
|
if(!(immu = malloc(sizeof(struct immu)))) {
|
if (NULL == (immu = malloc (sizeof (struct immu))))
|
|
{
|
fprintf(stderr, "OOM\n");
|
fprintf(stderr, "OOM\n");
|
exit(1);
|
exit(1);
|
}
|
}
|
|
|
immu->enabled = 0;
|
immu->enabled = 0;
|
|
immu->nsets = 1;
|
|
immu->nways = 1;
|
|
immu->pagesize = 8192;
|
|
immu->entrysize = 1; /* Not currently used */
|
|
immu->ustates = 2;
|
immu->hitdelay = 1;
|
immu->hitdelay = 1;
|
immu->missdelay = 1;
|
immu->missdelay = 1;
|
immu->pagesize = 8192;
|
|
/* FIXME: Something sane */
|
|
immu->entrysize = 0;
|
|
|
|
immu_state = immu;
|
if (immu->enabled)
|
|
{
|
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_IMP;
|
|
}
|
|
else
|
|
{
|
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;
|
|
}
|
|
|
|
set_bits = log2_int (immu->nsets);
|
|
cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;
|
|
cpu_state.sprs[SPR_IMMUCFGR] |= set_bits << SPR_IMMUCFGR_NTS_OFF;
|
|
|
|
way_bits = immu->nways - 1;
|
|
cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;
|
|
cpu_state.sprs[SPR_IMMUCFGR] |= way_bits << SPR_IMMUCFGR_NTW_OFF;
|
|
|
|
immu_state = immu;
|
return immu;
|
return immu;
|
}
|
|
|
|
static void immu_end_sec(void *dat)
|
} /* immu_start_sec() */
|
|
|
|
|
|
static void
|
|
immu_end_sec (void *dat)
|
{
|
{
|
struct immu *immu = dat;
|
struct immu *immu = dat;
|
|
|
/* Precalculate some values for use during address translation */
|
/* Precalculate some values for use during address translation */
|
immu->pagesize_log2 = log2_int(immu->pagesize);
|
immu->pagesize_log2 = log2_int(immu->pagesize);
|
| Line 361... |
Line 521... |
immu->page_mask = ~immu->page_offset_mask;
|
immu->page_mask = ~immu->page_offset_mask;
|
immu->vpn_mask = ~((immu->pagesize * immu->nsets) - 1);
|
immu->vpn_mask = ~((immu->pagesize * immu->nsets) - 1);
|
immu->set_mask = immu->nsets - 1;
|
immu->set_mask = immu->nsets - 1;
|
immu->lru_reload = (immu->set_mask << 6) & SPR_ITLBMR_LRU;
|
immu->lru_reload = (immu->set_mask << 6) & SPR_ITLBMR_LRU;
|
|
|
if(immu->enabled) {
|
if (immu->enabled)
|
|
{
|
PRINTF("Insn MMU %dKB: %d ways, %d sets, entry size %d bytes\n",
|
PRINTF("Insn MMU %dKB: %d ways, %d sets, entry size %d bytes\n",
|
immu->nsets * immu->entrysize * immu->nways / 1024, immu->nways,
|
immu->nsets * immu->entrysize * immu->nways / 1024, immu->nways,
|
immu->nsets, immu->entrysize);
|
immu->nsets, immu->entrysize);
|
reg_sim_stat(itlb_status, immu);
|
reg_sim_stat(itlb_status, immu);
|
}
|
}
|
}
|
}
|
|
|
void reg_immu_sec(void)
|
void
|
|
reg_immu_sec (void)
|
{
|
{
|
struct config_section *sec = reg_config_sec("immu", immu_start_sec,
|
struct config_section *sec = reg_config_sec("immu", immu_start_sec,
|
immu_end_sec);
|
immu_end_sec);
|
|
|
reg_config_param(sec, "enabled", paramt_int, immu_enabled);
|
reg_config_param(sec, "enabled", paramt_int, immu_enabled);
|
