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https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [trunk/] [xess/] [xsv_fpga/] [README] - Diff between revs 759 and 773
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Rev 773 |
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- OpenRISC GNU Toolchain (ANSI C compiler GCC, debugger etc)
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- OpenRISC GNU Toolchain (ANSI C compiler GCC, debugger etc)
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Directory Structure
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Directory Structure
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+++++++++++++++++++
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+++++++++++++++++++
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bench: test bench (for simulation verification)
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orp_soc/bench: test bench (for simulation verification)
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doc: Some of the documentation (more on the OpenCores web)
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orp_soc/doc: Some of the documentation (more on the OpenCores web)
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rtl: Verilog sources of the XSV FPGA SoC
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orp_soc/rtl: Verilog sources of the XSV FPGA SoC
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sim: For running simulation
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orp_soc/sim: For running simulation
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sw: Software example (OR1K GNU toolchain is available from OpenCores web)
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orp_soc/sw: Software example (OR1K GNU toolchain is available from OpenCores web)
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syn: Synthesis scripts/constraints for FPGA and ASIC
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orp_soc/syn: Synthesis scripts/constraints for FPGA and ASIC
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exo: Download files for XSV800
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exo: Download files for XSV800
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Simulation
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Simulation
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++++++++++
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will use !).
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will use !).
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--
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--
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Damjan Lampret, Mar/2002
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Damjan Lampret, Mar/2002
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.2 2002/03/21 22:14:46 lampret
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Explained 10MHz. Fixed directory name.
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Revision 1.1.1.1 2002/03/21 20:47:47 lampret
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Revision 1.1.1.1 2002/03/21 20:47:47 lampret
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First import of the "new" XESS XSV environment.
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First import of the "new" XESS XSV environment.
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