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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_master32_sm.v] - Diff between revs 2 and 6
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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//
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//
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//
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// module includes pci master state machine and surrounding logic
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// module includes pci master state machine and surrounding logic
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`include "bus_commands.v"
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`include "bus_commands.v"
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`include "constants.v"
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`include "constants.v"
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`include "timescale.v"
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module PCI_MASTER32_SM
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module PCI_MASTER32_SM
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(
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(
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// system inputs
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// system inputs
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clk_in,
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clk_in,
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reset_in,
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reset_in,
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assign retry_out = timeout_termination || (~pci_stop_reg_in && ~pci_devsel_reg_in) ;
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assign retry_out = timeout_termination || (~pci_stop_reg_in && ~pci_devsel_reg_in) ;
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// AD output flip flops' clock enable
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// AD output flip flops' clock enable
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// new data is loaded to AD outputs whenever state machine is idle, bus was granted and bus is in idle state or
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// new data is loaded to AD outputs whenever state machine is idle, bus was granted and bus is in idle state or
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// when address phase is about to be finished
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// when address phase is about to be finished
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wire load_force = (sm_idle && u_have_pci_bus) || (sm_address && do_write) ;
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wire load_force = (sm_idle && u_have_pci_bus) || sm_address ;
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// next data loading is allowed when state machine is in transfer state and operation is a write
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// next data loading is allowed when state machine is in transfer state and operation is a write
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wire load_allow = sm_data_phases && do_write ;
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wire load_allow = sm_data_phases && do_write ;
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// actual loading during data phases is done by monitoring critical target response signals - separate module
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// actual loading during data phases is done by monitoring critical target response signals - separate module
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