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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Diff between revs 45 and 54
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//===================================================================================
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//===================================================================================
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// User-unchangeable testbench defines (constants)
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// User-unchangeable testbench defines (constants)
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//===================================================================================
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//===================================================================================
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// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
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// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
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`define Tsetup 0.5
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`define Tsetup 3
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`define Thold 0.5
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`define Thold 1
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// how many clock cycles should model wait for design's response - integer 32 bit value
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// how many clock cycles should model wait for design's response - integer 32 bit value
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`define WAIT_FOR_RESPONSE 6
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`define WAIT_FOR_RESPONSE 6
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// maximum number of transactions allowed in single call to block or cab transfer routines
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// maximum number of transactions allowed in single call to block or cab transfer routines
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