Line 103... |
Line 103... |
impl_opt(dont_run_fit)=0
|
impl_opt(dont_run_fit)=0
|
impl_opt(dont_run_bitgen)=1
|
impl_opt(dont_run_bitgen)=1
|
|
|
[HierarchyViewer]
|
[HierarchyViewer]
|
SortInfo=u
|
SortInfo=u
|
HierarchyInformation=ctrl_fifo64x37st|ctrl_fifo64x37st_a|0 stend_sp605_wishbone|stend_sp605_wishbone|0
|
HierarchyInformation=cl_s6pcie_m2|rtl|0 stend_sp605_wishbone|stend_sp605_wishbone|0
|
ShowHide=ShowTopLevel
|
ShowHide=ShowTopLevel
|
Selected=
|
Selected=
|
|
|
[DefineMacro]
|
[DefineMacro]
|
Global=
|
Global=
|
Line 152... |
Line 152... |
pcie_src\pcie_sim\dsport=1
|
pcie_src\pcie_sim\dsport=1
|
pcie_src\pcie_sim\sim=1
|
pcie_src\pcie_sim\sim=1
|
testbench=1
|
testbench=1
|
testbench\modelsim=1
|
testbench\modelsim=1
|
testbench\modelsim\zz_do=1
|
testbench\modelsim\zz_do=1
|
|
testbench\modelsim\required_tests=1
|
|
testbench\modelsim\required_tests\test0=1
|
|
testbench\modelsim\required_tests\test0\zz_do=1
|
|
testbench\ahdl=1
|
top=1
|
top=1
|
log=1
|
log=1
|
wishbone=1
|
wishbone=1
|
wishbone\block_test_check=1
|
wishbone\block_test_check=1
|
wishbone\block_test_generate=1
|
wishbone\block_test_generate=1
|
Line 173... |
Line 177... |
wishbone\testbecnh\dev_test_gen\sim=1
|
wishbone\testbecnh\dev_test_gen\sim=1
|
wishbone\testbecnh\dev_test_gen\sim\zz_do=1
|
wishbone\testbecnh\dev_test_gen\sim\zz_do=1
|
wishbone\testbecnh\dev_wb_cross=1
|
wishbone\testbecnh\dev_wb_cross=1
|
wishbone\testbecnh\dev_wb_cross\sim=1
|
wishbone\testbecnh\dev_wb_cross\sim=1
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
|
testbench\ahdl=1
|
|
testbench\modelsim\required_tests=1
|
|
testbench\modelsim\required_tests\test0=1
|
|
testbench\modelsim\required_tests\test0\zz_do=1
|
|
|
|
[Files]
|
[Files]
|
pcie_src\components\block_main/block_pe_main.vhd=-1
|
pcie_src\components\block_main/block_pe_main.vhd=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.ngc=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.ngc=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.vhd=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.vhd=-1
|
Line 317... |
Line 317... |
pcie_src\pcie_sim\dsport/xilinx_pcie_rport_m2.vhd=-1
|
pcie_src\pcie_sim\dsport/xilinx_pcie_rport_m2.vhd=-1
|
pcie_src\pcie_sim\sim/block_pkg.vhd=-1
|
pcie_src\pcie_sim\sim/block_pkg.vhd=-1
|
pcie_src\pcie_sim\sim/cmd_sim_pkg.vhd=-1
|
pcie_src\pcie_sim\sim/cmd_sim_pkg.vhd=-1
|
pcie_src\pcie_sim\sim/root_memory_pkg.vhd=-1
|
pcie_src\pcie_sim\sim/root_memory_pkg.vhd=-1
|
pcie_src\pcie_sim\sim/trd_pcie_pkg.vhd=-1
|
pcie_src\pcie_sim\sim/trd_pcie_pkg.vhd=-1
|
testbench/stend_sp605_wishbone.vhd=-1
|
|
testbench/test_pkg.vhd=-1
|
|
testbench/wb_block_pkg.vhd=-1
|
testbench/wb_block_pkg.vhd=-1
|
|
testbench/test_pkg.vhd=-1
|
|
testbench/stend_sp605_wishbone.vhd=-1
|
testbench\modelsim/delete.bat=-1
|
testbench\modelsim/delete.bat=-1
|
testbench\modelsim/start.bat=-1
|
testbench\modelsim/start.bat=-1
|
testbench\modelsim/wave.do=-1
|
testbench\modelsim/wave.do=-1
|
testbench\modelsim\zz_do/delete.do=-1
|
testbench\modelsim\zz_do/delete.do=-1
|
testbench\modelsim\zz_do/setup_sim.do=-1
|
testbench\modelsim\zz_do/setup_sim.do=-1
|
Line 333... |
Line 333... |
testbench\modelsim\required_tests\test0/read.me=-1
|
testbench\modelsim\required_tests\test0/read.me=-1
|
testbench\modelsim\required_tests\test0/start.bat=-1
|
testbench\modelsim\required_tests\test0/start.bat=-1
|
testbench\modelsim\required_tests\test0/wave.do=-1
|
testbench\modelsim\required_tests\test0/wave.do=-1
|
testbench\modelsim\required_tests\test0\zz_do/delete.do=-1
|
testbench\modelsim\required_tests\test0\zz_do/delete.do=-1
|
testbench\modelsim\required_tests\test0\zz_do/setup_sim.do=-1
|
testbench\modelsim\required_tests\test0\zz_do/setup_sim.do=-1
|
|
testbench\ahdl/test_gen.awf=-1
|
|
testbench\ahdl/pb_wishbone.awf=-1
|
|
testbench\ahdl/rx.awf=-1
|
|
testbench\ahdl/tx.awf=-1
|
top/sp605_lx45t_wishbone.ucf=-1
|
top/sp605_lx45t_wishbone.ucf=-1
|
top/sp605_lx45t_wishbone_sopc_wb.vhd=-1
|
top/sp605_lx45t_wishbone_sopc_wb.vhd=-1
|
top/sp605_lx45t_wishbone.vhd=-1
|
top/sp605_lx45t_wishbone.vhd=-1
|
log/..\..\test.log=-1
|
log/..\..\test.log=-1
|
wishbone\block_test_check/block_check_wb_pkg.vhd=-1
|
wishbone\block_test_check/block_check_wb_pkg.vhd=-1
|
Line 542... |
Line 546... |
.\src\pcie_src\pcie_sim\dsport\xilinx_pcie_rport_m2.vhd=VHDL Source Code
|
.\src\pcie_src\pcie_sim\dsport\xilinx_pcie_rport_m2.vhd=VHDL Source Code
|
.\src\pcie_src\pcie_sim\sim\block_pkg.vhd=VHDL Source Code
|
.\src\pcie_src\pcie_sim\sim\block_pkg.vhd=VHDL Source Code
|
.\src\pcie_src\pcie_sim\sim\cmd_sim_pkg.vhd=VHDL Source Code
|
.\src\pcie_src\pcie_sim\sim\cmd_sim_pkg.vhd=VHDL Source Code
|
.\src\pcie_src\pcie_sim\sim\root_memory_pkg.vhd=VHDL Source Code
|
.\src\pcie_src\pcie_sim\sim\root_memory_pkg.vhd=VHDL Source Code
|
.\src\pcie_src\pcie_sim\sim\trd_pcie_pkg.vhd=VHDL Source Code
|
.\src\pcie_src\pcie_sim\sim\trd_pcie_pkg.vhd=VHDL Source Code
|
.\src\testbench\stend_sp605_wishbone.vhd=VHDL Source Code
|
|
.\src\testbench\test_pkg.vhd=VHDL Source Code
|
|
.\src\testbench\wb_block_pkg.vhd=VHDL Source Code
|
.\src\testbench\wb_block_pkg.vhd=VHDL Source Code
|
|
.\src\testbench\test_pkg.vhd=VHDL Source Code
|
|
.\src\testbench\stend_sp605_wishbone.vhd=VHDL Source Code
|
.\src\testbench\modelsim\delete.bat=External File
|
.\src\testbench\modelsim\delete.bat=External File
|
.\src\testbench\modelsim\start.bat=External File
|
.\src\testbench\modelsim\start.bat=External File
|
.\src\testbench\modelsim\wave.do=Macro
|
.\src\testbench\modelsim\wave.do=Macro
|
.\src\testbench\modelsim\zz_do\delete.do=Macro
|
.\src\testbench\modelsim\zz_do\delete.do=Macro
|
.\src\testbench\modelsim\zz_do\setup_sim.do=Macro
|
.\src\testbench\modelsim\zz_do\setup_sim.do=Macro
|
Line 558... |
Line 562... |
.\src\testbench\modelsim\required_tests\test0\read.me=External File
|
.\src\testbench\modelsim\required_tests\test0\read.me=External File
|
.\src\testbench\modelsim\required_tests\test0\start.bat=External File
|
.\src\testbench\modelsim\required_tests\test0\start.bat=External File
|
.\src\testbench\modelsim\required_tests\test0\wave.do=Macro
|
.\src\testbench\modelsim\required_tests\test0\wave.do=Macro
|
.\src\testbench\modelsim\required_tests\test0\zz_do\delete.do=Macro
|
.\src\testbench\modelsim\required_tests\test0\zz_do\delete.do=Macro
|
.\src\testbench\modelsim\required_tests\test0\zz_do\setup_sim.do=Macro
|
.\src\testbench\modelsim\required_tests\test0\zz_do\setup_sim.do=Macro
|
|
.\src\testbench\ahdl\test_gen.awf=Waveform File
|
|
.\src\testbench\ahdl\pb_wishbone.awf=Waveform File
|
|
.\src\testbench\ahdl\rx.awf=Waveform File
|
|
.\src\testbench\ahdl\tx.awf=Waveform File
|
.\src\top\sp605_lx45t_wishbone.ucf=External File
|
.\src\top\sp605_lx45t_wishbone.ucf=External File
|
.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd=VHDL Source Code
|
.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd=VHDL Source Code
|
.\src\top\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
.\src\top\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
.\test.log=Text File
|
.\test.log=Text File
|
.\src\wishbone\block_test_check\block_check_wb_pkg.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\block_check_wb_pkg.vhd=VHDL Source Code
|
Line 627... |
Line 635... |
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_intf.sv=SystemVerilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_intf.sv=SystemVerilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_master.sv=SystemVerilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_master.sv=SystemVerilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_ram_slave.v=Verilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_ram_slave.v=Verilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\delete.do=Macro
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\delete.do=Macro
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\setup_sim.do=Macro
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\setup_sim.do=Macro
|
|
|