| Line 148... |
Line 148... |
// fix of 03/05/02. The fix of 03/05/02 correctly generated the
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// fix of 03/05/02. The fix of 03/05/02 correctly generated the
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// C bit for subtraction of zero, but unfortunately it introduced
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// C bit for subtraction of zero, but unfortunately it introduced
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// an error such that all subtraction results were off by 1.
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// an error such that all subtraction results were off by 1.
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// Obviously, this was unacceptable, and I think it has been fixed
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// Obviously, this was unacceptable, and I think it has been fixed
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// by the new signals "c_subtract_zero" and "c_dig_subtract_zero"
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// by the new signals "c_subtract_zero" and "c_dig_subtract_zero"
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// Update: 10/24/05 Added code patches to fix interrupt bug and status flag updates
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//
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// when using literal value of 0x03. These bugs were reported by
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// Update: 23 june 2014 (Stanislav Corboot)
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// an opencores.org user. Added three "disable_status_x" signals.
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//
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// Modified file still needs to be tested.
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// - Bug fixed: interrupt handler executed one and the same
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// Update: 06/29/13 This project is now CC-BY licensed. See risc16f84_license.txt
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// instruction twice - before interruption and after it.
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// for details.
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// - Bug fixed: incorrect behavior of the zero flag after LITERAL
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// instructions (xxxLW) if operand was equal 0x03 and if result
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// equal zero.
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// Example:
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// movlw 0x03
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// xorlw 0x03 -> WREG=0x00, ZF=0 - ERROR!
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// or
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// movlw 0xFD
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// addlw 0x03 -> WREG=0x00, ZF=0 - ERROR!
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// or
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// movlw 0x00
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// andlw 0x03 -> WREG=0x00, ZF=0 - ERROR!
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// etc.
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//
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//
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// Description
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// Description
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// This logic module implements a small RISC microcontroller, with functions
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// This logic module implements a small RISC microcontroller, with functions
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// and instruction set very similar to those of the Microchip 16F84 chip.
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// and instruction set very similar to those of the Microchip 16F84 chip.
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| Line 346... |
Line 358... |
reg writeram_node; // H if destination is RAM/Special registers
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reg writeram_node; // H if destination is RAM/Special registers
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reg c_subtract_zero; // High for special case of C bit, when subtracting zero
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reg c_subtract_zero; // High for special case of C bit, when subtracting zero
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reg c_dig_subtract_zero; // High for special case of C bit, when subtracting zero
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reg c_dig_subtract_zero; // High for special case of C bit, when subtracting zero
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wire next_exec_stall;
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wire next_exec_stall;
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// Three signals used to disable status flag updates. Fixes bug when literal 0x03 is used.
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wire disable_status_z;
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wire disable_status_c;
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wire disable_status_dc;
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// Instantiations
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// Instantiations
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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| Line 443... |
Line 451... |
assign addr_aux_adr_hi = (ram_adr_node[7:0] == 8'b00000110); // 06H
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assign addr_aux_adr_hi = (ram_adr_node[7:0] == 8'b00000110); // 06H
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// construct bit-mask for logical operations and bit tests
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// construct bit-mask for logical operations and bit tests
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assign mask_node = 1 << inst_reg[9:7];
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assign mask_node = 1 << inst_reg[9:7];
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// disable write access for status flags
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assign disable_status_z = (inst_addwf || inst_andwf || inst_clrf ||
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inst_clrw || inst_comf || inst_decf ||
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inst_incf || inst_iorwf || inst_movf ||
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inst_subwf || inst_xorwf || inst_addlw ||
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inst_andlw || inst_iorlw || inst_iorlw ||
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inst_sublw || inst_xorlw) ? 1:0;
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assign disable_status_c = (inst_addwf || inst_subwf || inst_rlf ||
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inst_rrf || inst_addlw || inst_sublw ) ? 1:0;
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assign disable_status_dc = (inst_addwf || inst_subwf || inst_addlw ||
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inst_sublw ) ? 1:0;
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// Create the exec_stall signal, based on the contents of the currently
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// Create the exec_stall signal, based on the contents of the currently
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// executing instruction (inst_reg). next_exec_stall reflects the state
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// executing instruction (inst_reg). next_exec_stall reflects the state
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// to assign to exec_stall following the conclusion of the next Q4 state.
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// to assign to exec_stall following the conclusion of the next Q4 state.
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// All of these instructions cause an execution stall in the next cycle
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// All of these instructions cause an execution stall in the next cycle
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// because they modify the program counter, and a new value is presented
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// because they modify the program counter, and a new value is presented
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| Line 721... |
Line 716... |
end // End of reset assignments
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end // End of reset assignments
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else if (~exec_stall_reg && clk_en_i)
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else if (~exec_stall_reg && clk_en_i)
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begin // Execution ceases during a stall cycle.
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begin // Execution ceases during a stall cycle.
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if (state_reg == Q2_PP) // 2-3. Q2 cycle
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if (state_reg == Q2_PP) // 2-3. Q2 cycle
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begin
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begin
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if( ~int_condition ) // Bug fixed
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begin
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// 2-3-1. Read data-RAM and store values to alu-input regs
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// 2-3-1. Read data-RAM and store values to alu-input regs
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// 2-3-1-1. Set aluinp1 register (source #1)
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// 2-3-1-1. Set aluinp1 register (source #1)
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if ( inst_movf || inst_swapf || inst_addwf || inst_subwf
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if ( inst_movf || inst_swapf || inst_addwf || inst_subwf
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|| inst_andwf || inst_iorwf || inst_xorwf || inst_decf
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|| inst_andwf || inst_iorwf || inst_xorwf || inst_decf
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|| inst_incf || inst_rlf || inst_rrf || inst_bcf
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|| inst_incf || inst_rlf || inst_rrf || inst_bcf
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| Line 771... |
Line 768... |
// It is not known to me (John Clayton) whether any glitches would
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// It is not known to me (John Clayton) whether any glitches would
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// really occur. It might be possible to generate these signals
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// really occur. It might be possible to generate these signals
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// using combinational logic only, without using registers!
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// using combinational logic only, without using registers!
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ram_we_reg <= (writeram_node && addr_sram);
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ram_we_reg <= (writeram_node && addr_sram);
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aux_we_reg <= (writeram_node && addr_aux_dat);
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aux_we_reg <= (writeram_node && addr_aux_dat);
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end // Bug fixed
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end // End of Q2 state
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end // End of Q2 state
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//---------------------------------------------------------------------
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//---------------------------------------------------------------------
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else if (state_reg == QINT_PP) // Interrupt execution (instead of Q4_PP)
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else if (state_reg == QINT_PP) // Interrupt execution (instead of Q4_PP)
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| Line 821... |
Line 819... |
// 2-5-2. Store calculation result into destination,
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// 2-5-2. Store calculation result into destination,
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// 2-5-2-1. Set W register
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// 2-5-2-1. Set W register
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if (writew_node) w_reg <= aluout; // write W reg
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if (writew_node) w_reg <= aluout; // write W reg
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// 2-5-2-2. Set data RAM/special registers,
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// 2-5-2-2. Set data RAM/special registers,
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if (writeram_node)
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if (writeram_node)
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begin
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begin
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if (addr_stat)
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if (addr_stat)
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begin
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begin
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status_reg[7:5] <= aluout[7:5]; // write IRP,RP1,RP0
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status_reg[7:5] <= aluout[7:5]; // write IRP,RP1,RP0
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// status(4),status(3)...unwritable, see below (/PD,/T0 part)
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// status(4),status(3)...unwritable, see below (/PD,/T0 part)
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if( ~disable_status_c ) status_reg[0] <= aluout[0]; // write C
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status_reg[1:0] <= aluout[1:0]; // write DC,C
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if( ~disable_status_dc ) status_reg[1] <= aluout[1]; // write DC
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end
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end
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if (addr_fsr) fsr_reg <= aluout; // write FSR
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if (addr_fsr) fsr_reg <= aluout; // write FSR
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if (addr_pclath) pclath_reg <= aluout[4:0]; // write PCLATH
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if (addr_pclath) pclath_reg <= aluout[4:0]; // write PCLATH
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if (addr_intcon) intcon_reg <= aluout; // write INTCON
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if (addr_intcon) intcon_reg <= aluout; // write INTCON
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if (addr_aux_adr_lo) aux_adr_lo_reg <= aluout; // write AUX low
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if (addr_aux_adr_lo) aux_adr_lo_reg <= aluout; // write AUX low
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if (addr_aux_adr_hi) aux_adr_hi_reg <= aluout; // write AUX high
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if (addr_aux_adr_hi) aux_adr_hi_reg <= aluout; // write AUX high
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end
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end
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// 2-5-2-3. Set/clear Z flag.
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// 2-5-2-3. Set/clear Z flag.
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if (addr_stat && ~disable_status_z) status_reg[2] <= aluout[2];
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if (addr_stat && !writew_node) status_reg[2] <= aluout[2]; // (dest. is Z flag) // Bug fixed
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else if ( inst_addlw || inst_addwf || inst_andlw || inst_andwf
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else if ( inst_addlw || inst_addwf || inst_andlw || inst_andwf
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|| inst_clrf || inst_clrw || inst_comf || inst_decf
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|| inst_clrf || inst_clrw || inst_comf || inst_decf
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|| inst_incf || inst_movf || inst_sublw || inst_subwf
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|| inst_incf || inst_movf || inst_sublw || inst_subwf
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|| inst_xorlw || inst_xorwf || inst_iorlw || inst_iorwf )
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|| inst_xorlw || inst_xorwf || inst_iorlw || inst_iorwf )
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status_reg[2] <= aluout_zero_node; // Z=1 if result == 0
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status_reg[2] <= aluout_zero_node; // Z=1 if result == 0
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| Line 942... |
Line 938... |
else if (clk_en_i && intrise && intcon_reg[4]) inte_sync_reg <= 1;
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else if (clk_en_i && intrise && intcon_reg[4]) inte_sync_reg <= 1;
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end
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end
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// Issue an interrupt when the interrupt is present.
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// Issue an interrupt when the interrupt is present.
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// Also, do not issue an interrupt when there is a stall cycle coming!
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// Also, do not issue an interrupt when there is a stall cycle coming!
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assign int_condition = (inte_sync_reg && ~exec_stall_reg && ~next_exec_stall && intcon_reg[7]);
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assign int_condition = (inte_sync_reg && ~exec_stall_reg && intcon_reg[7]);
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// Interrupt must be pending
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// Interrupt must be pending
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// Next processor cycle must not be a stall
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// Next processor cycle must not be a stall
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// GIE bit must be set to issue interrupt
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// GIE bit must be set to issue interrupt
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// Circuit's output signals
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// Circuit's output signals
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