| Line 45... |
Line 45... |
sc_trace(o_vcd, o_resp_data_data, "/top/cache0/d0/o_resp_data_data");
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sc_trace(o_vcd, o_resp_data_data, "/top/cache0/d0/o_resp_data_data");
|
sc_trace(o_vcd, r.dline_data, "/top/cache0/d0/r_dline_data");
|
sc_trace(o_vcd, r.dline_data, "/top/cache0/d0/r_dline_data");
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sc_trace(o_vcd, r.dline_addr_req, "/top/cache0/d0/r_dline_addr_req");
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sc_trace(o_vcd, r.dline_addr_req, "/top/cache0/d0/r_dline_addr_req");
|
sc_trace(o_vcd, r.dline_size_req, "/top/cache0/d0/r_dline_size_req");
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sc_trace(o_vcd, r.dline_size_req, "/top/cache0/d0/r_dline_size_req");
|
sc_trace(o_vcd, r.state, "/top/cache0/d0/r_state");
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sc_trace(o_vcd, r.state, "/top/cache0/d0/r_state");
|
}
|
sc_trace(o_vcd, w_wait_response, "/top/cache0/d0/w_wait_response"); }
|
}
|
}
|
|
|
void DCache::comb() {
|
void DCache::comb() {
|
bool w_o_req_data_ready;
|
bool w_o_req_data_ready;
|
bool w_o_req_mem_valid;
|
bool w_o_req_mem_valid;
|
| Line 68... |
Line 68... |
wb_o_req_strob = 0;
|
wb_o_req_strob = 0;
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wb_o_req_wdata = 0;
|
wb_o_req_wdata = 0;
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wb_o_resp_data = 0;
|
wb_o_resp_data = 0;
|
wb_rtmp = 0;
|
wb_rtmp = 0;
|
|
|
|
w_wait_response = 0;
|
|
if (r.state.read() == State_WaitResp && i_resp_mem_data_valid.read() == 0) {
|
|
w_wait_response = 1;
|
|
}
|
|
|
switch (i_req_data_sz.read()) {
|
switch (i_req_data_sz.read()) {
|
case 0:
|
case 0:
|
wb_o_req_wdata = (i_req_data_data.read()(7, 0),
|
wb_o_req_wdata = (i_req_data_data.read()(7, 0),
|
i_req_data_data.read()(7, 0), i_req_data_data.read()(7, 0),
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i_req_data_data.read()(7, 0), i_req_data_data.read()(7, 0),
|
i_req_data_data.read()(7, 0), i_req_data_data.read()(7, 0),
|
i_req_data_data.read()(7, 0), i_req_data_data.read()(7, 0),
|
| Line 123... |
Line 128... |
wb_o_req_strob = 0xFF;
|
wb_o_req_strob = 0xFF;
|
break;
|
break;
|
default:;
|
default:;
|
}
|
}
|
|
|
w_o_req_mem_valid = i_req_data_valid.read();
|
w_o_req_mem_valid = i_req_data_valid.read() && !w_wait_response;
|
wb_o_req_mem_addr = i_req_data_addr.read()(BUS_ADDR_WIDTH-1, 3) << 3;
|
wb_o_req_mem_addr = i_req_data_addr.read()(BUS_ADDR_WIDTH-1, 3) << 3;
|
w_o_req_data_ready = i_req_mem_ready.read();
|
w_o_req_data_ready = i_req_mem_ready.read();
|
w_req_fire = i_req_data_valid.read() && w_o_req_data_ready;
|
w_req_fire = w_o_req_mem_valid && w_o_req_data_ready;
|
switch (r.state.read()) {
|
switch (r.state.read()) {
|
case State_Idle:
|
case State_Idle:
|
if (i_req_data_valid.read()) {
|
if (i_req_data_valid.read()) {
|
if (i_req_mem_ready.read()) {
|
if (i_req_mem_ready.read()) {
|
v.state = State_WaitResp;
|
v.state = State_WaitResp;
|
