Line 16... |
Line 16... |
// You should have received a copy of the GNU General Public
|
// You should have received a copy of the GNU General Public
|
// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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|
`ifdef SIMPLY_RISC_TWEAKS
|
|
`define SIMPLY_RISC_SCANIN .si(0)
|
|
`else
|
|
`define SIMPLY_RISC_SCANIN .si()
|
|
`endif
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Description: Memory BIST Controller for the L1 ICache and DCache
|
// Description: Memory BIST Controller for the L1 ICache and DCache
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// Block Type: Control Block
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// Block Type: Control Block
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// Module: mbist_engine
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// Module: mbist_engine
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Line 194... |
Line 199... |
|
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//// reset buffer ////
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//// reset buffer ////
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|
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dffrl_async rstff(.din (grst_l),
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dffrl_async rstff(.din (grst_l),
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.q (mbist_reset_l),
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.q (mbist_reset_l),
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.clk (rclk), .se(mbist_se), .si(), .so(),
|
.clk (rclk), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so(),
|
.rst_l (arst_l));
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.rst_l (arst_l));
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|
|
assign mbist_reset = ~mbist_reset_l;
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assign mbist_reset = ~mbist_reset_l;
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|
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// /////////////////////////////////////////////////////////////////////////////
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// /////////////////////////////////////////////////////////////////////////////
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Line 218... |
Line 223... |
//
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//
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// /////////////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////////////
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|
|
|
|
|
|
dff #(8) config_reg (
|
dff_s #(8) config_reg (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( config_in[7:0] ),
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.din ( config_in[7:0] ),
|
.q ( config_out[7:0] ), .se(mbist_se), .si(), .so());
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.q ( config_out[7:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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|
|
|
|
|
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assign config_in[0] = mbist_start;
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assign config_in[0] = mbist_start;
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assign config_in[1] = config_out[0];
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assign config_in[1] = config_out[0];
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Line 251... |
Line 256... |
|
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assign config_in[7] = start_transition ? mbist_loop_on_address: config_out[7];
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assign config_in[7] = start_transition ? mbist_loop_on_address: config_out[7];
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assign loop_on_address = config_out[7];
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assign loop_on_address = config_out[7];
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|
|
|
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dff #(8) userdata_reg (
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dff_s #(8) userdata_reg (
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( userdata_in[7:0] ),
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.din ( userdata_in[7:0] ),
|
.q ( userdata_out[7:0] ), .se(mbist_se), .si(), .so());
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.q ( userdata_out[7:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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|
|
|
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assign userdata_in[7:0] = userdata_out[7:0];
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assign userdata_in[7:0] = userdata_out[7:0];
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dff #(7) user_address_reg (
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dff_s #(7) user_address_reg (
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( useradd_in[6:0] ),
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.din ( useradd_in[6:0] ),
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.q ( useradd_out[6:0] ), .se(mbist_se), .si(), .so());
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.q ( useradd_out[6:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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|
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assign useradd_in[6:0] = useradd_out[6:0];
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assign useradd_in[6:0] = useradd_out[6:0];
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// /////////////////////////////////////////////////////////////////////////////
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// /////////////////////////////////////////////////////////////////////////////
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Line 279... |
Line 284... |
// /////////////////////////////////////////////////////////////////////////////
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// /////////////////////////////////////////////////////////////////////////////
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// Remove Address mix disable before delivery
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// Remove Address mix disable before delivery
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// /////////////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////////////
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|
|
|
|
dff #(21) control_reg (
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dff_s #(21) control_reg (
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( control_in[20:0] ),
|
.din ( control_in[20:0] ),
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.q ( control_out[20:0] ), .se(mbist_se), .si(), .so());
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.q ( control_out[20:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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|
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assign msb = control_out[20];
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assign msb = control_out[20];
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assign array_sel = control_out[19];
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assign array_sel = control_out[19];
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assign data_control[1:0] = userdata_mode ? 2'b11 : control_out[18:17];
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assign data_control[1:0] = userdata_mode ? 2'b11 : control_out[18:17];
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assign address_mix = loop_on_address ? 1'b1: control_out[16];
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assign address_mix = loop_on_address ? 1'b1: control_out[16];
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Line 366... |
Line 371... |
|
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////////////////////////
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////////////////////////
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////////////////////////
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////////////////////////
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assign msb_rst = msb & ~reset_engine;
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assign msb_rst = msb & ~reset_engine;
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dff #(1) msb_d1_inst(
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dff_s #(1) msb_d1_inst(
|
.clk ( rclk ),
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.clk ( rclk ),
|
.din ( msb_rst ),
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.din ( msb_rst ),
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.q ( msb_d1 ), .se(mbist_se), .si(), .so());
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.q ( msb_d1 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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assign msb_d1_rst = msb_d1 & ~reset_engine;
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assign msb_d1_rst = msb_d1 & ~reset_engine;
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dff #(1) msb_d2_inst(
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dff_s #(1) msb_d2_inst(
|
.clk ( rclk ),
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.clk ( rclk ),
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.din ( msb_d1_rst ),
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.din ( msb_d1_rst ),
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.q ( msb_d2 ), .se(mbist_se), .si(), .so());
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.q ( msb_d2 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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assign msb_d2_rst = msb_d2 & ~reset_engine;
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assign msb_d2_rst = msb_d2 & ~reset_engine;
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dff #(1) msb_d3_inst(
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dff_s #(1) msb_d3_inst(
|
.clk ( rclk ),
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.clk ( rclk ),
|
.din ( msb_d2_rst ),
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.din ( msb_d2_rst ),
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.q ( msb_d3 ), .se(mbist_se), .si(), .so());
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.q ( msb_d3 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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assign msb_d3_rst = msb_d3 & ~reset_engine;
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assign msb_d3_rst = msb_d3 & ~reset_engine;
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dff #(1) msb_d4_inst(
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dff_s #(1) msb_d4_inst(
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.clk ( rclk ),
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.clk ( rclk ),
|
.din ( msb_d3_rst ),
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.din ( msb_d3_rst ),
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.q ( msb_d4 ), .se(mbist_se), .si(), .so());
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.q ( msb_d4 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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// /////////////////////////////////////////////////////////////////////////////
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// /////////////////////////////////////////////////////////////////////////////
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// Pipeline for Read, Data, and Address
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// Pipeline for Read, Data, and Address
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// /////////////////////////////////////////////////////////////////////////////
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// /////////////////////////////////////////////////////////////////////////////
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Line 397... |
Line 402... |
wire ic_read_pipe_out1_bf, ic_read_pipe_out2_bf, ic_read_pipe_out3_bf;
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wire ic_read_pipe_out1_bf, ic_read_pipe_out2_bf, ic_read_pipe_out3_bf;
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|
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////////////
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////////////
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////////////
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////////////
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dff #(1) dc_read_pipe_reg1 (
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dff_s #(1) dc_read_pipe_reg1 (
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( mbist_dcache_read ),
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.din ( mbist_dcache_read ),
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.q ( dc_read_pipe_out1 ), .se(mbist_se), .si(), .so());
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.q ( dc_read_pipe_out1 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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assign dc_read_pipe_out1_bf = dc_read_pipe_out1 & ~reset_engine;
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assign dc_read_pipe_out1_bf = dc_read_pipe_out1 & ~reset_engine;
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dff #(1) dc_read_pipe_reg2 (
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dff_s #(1) dc_read_pipe_reg2 (
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( dc_read_pipe_out1_bf ),
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.din ( dc_read_pipe_out1_bf ),
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.q ( dc_read_pipe_out2 ), .se(mbist_se), .si(), .so());
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.q ( dc_read_pipe_out2 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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assign dc_read_pipe_out2_bf = dc_read_pipe_out2 & ~reset_engine;
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assign dc_read_pipe_out2_bf = dc_read_pipe_out2 & ~reset_engine;
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dff #(1) dc_read_pipe_reg3 (
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dff_s #(1) dc_read_pipe_reg3 (
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( dc_read_pipe_out2_bf ),
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.din ( dc_read_pipe_out2_bf ),
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.q ( dc_read_pipe_out3 ), .se(mbist_se), .si(), .so());
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.q ( dc_read_pipe_out3 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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assign dc_read_pipe_out3_bf = dc_read_pipe_out3 & ~reset_engine;
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assign dc_read_pipe_out3_bf = dc_read_pipe_out3 & ~reset_engine;
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assign dcache_data_sel = dc_read_pipe_out3_bf;
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assign dcache_data_sel = dc_read_pipe_out3_bf;
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dff #(1) dc_read_pipe_reg4 (
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dff_s #(1) dc_read_pipe_reg4 (
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( dc_read_pipe_out3_bf ),
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.din ( dc_read_pipe_out3_bf ),
|
.q ( dc_read_pipe_out4 ), .se(mbist_se), .si(), .so());
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.q ( dc_read_pipe_out4 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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|
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assign dcache_piped_read = dc_read_pipe_out4 & ~reset_engine;
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assign dcache_piped_read = dc_read_pipe_out4 & ~reset_engine;
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|
|
////////////
|
////////////
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////////////
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////////////
|
|
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dff #(1) ic_read_pipe_reg1 (
|
dff_s #(1) ic_read_pipe_reg1 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( mbist_icache_read_bf ),
|
.din ( mbist_icache_read_bf ),
|
.q ( ic_read_pipe_out1 ), .se(mbist_se), .si(), .so());
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.q ( ic_read_pipe_out1 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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|
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assign ic_read_pipe_out1_bf = ic_read_pipe_out1 & ~reset_engine;
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assign ic_read_pipe_out1_bf = ic_read_pipe_out1 & ~reset_engine;
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assign mbist_icache_read = ic_read_pipe_out1;
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assign mbist_icache_read = ic_read_pipe_out1;
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|
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dff #(1) ic_read_pipe_reg2 (
|
dff_s #(1) ic_read_pipe_reg2 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( ic_read_pipe_out1_bf ),
|
.din ( ic_read_pipe_out1_bf ),
|
.q ( ic_read_pipe_out2 ), .se(mbist_se), .si(), .so());
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.q ( ic_read_pipe_out2 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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|
|
assign ic_read_pipe_out2_bf = ic_read_pipe_out2 & ~reset_engine;
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assign ic_read_pipe_out2_bf = ic_read_pipe_out2 & ~reset_engine;
|
|
|
dff #(1) ic_read_pipe_reg3 (
|
dff_s #(1) ic_read_pipe_reg3 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( ic_read_pipe_out2_bf ),
|
.din ( ic_read_pipe_out2_bf ),
|
.q ( ic_read_pipe_out3 ), .se(mbist_se), .si(), .so());
|
.q ( ic_read_pipe_out3 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ic_read_pipe_out3_bf = ic_read_pipe_out3 & ~reset_engine;
|
assign ic_read_pipe_out3_bf = ic_read_pipe_out3 & ~reset_engine;
|
|
|
dff #(1) ic_read_pipe_reg4 (
|
dff_s #(1) ic_read_pipe_reg4 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( ic_read_pipe_out3_bf ),
|
.din ( ic_read_pipe_out3_bf ),
|
.q ( ic_read_pipe_out4 ), .se(mbist_se), .si(), .so());
|
.q ( ic_read_pipe_out4 ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
assign icache_piped_read = ic_read_pipe_out4 & ~reset_engine;
|
assign icache_piped_read = ic_read_pipe_out4 & ~reset_engine;
|
|
|
////////////
|
////////////
|
////////////
|
////////////
|
|
|
dff #(1) ic_write_pipe_reg1 (
|
dff_s #(1) ic_write_pipe_reg1 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( mbist_icache_write_bf ),
|
.din ( mbist_icache_write_bf ),
|
.q ( mbist_icache_write ), .se(mbist_se), .si(), .so());
|
.q ( mbist_icache_write ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
////////////
|
////////////
|
////////////
|
////////////
|
|
|
wire [7:0] data_pipe_out3, data_pipe_out4;
|
wire [7:0] data_pipe_out3, data_pipe_out4;
|
|
|
dff #(8) data_pipe_reg1 (
|
dff_s #(8) data_pipe_reg1 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( mbist_write_data_bf[7:0] ),
|
.din ( mbist_write_data_bf[7:0] ),
|
.q ( data_pipe_out1[7:0] ), .se(mbist_se), .si(), .so());
|
.q ( data_pipe_out1[7:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign mbist_icache_wdata = data_pipe_out1;
|
assign mbist_icache_wdata = data_pipe_out1;
|
|
|
dff #(8) data_pipe_reg2 (
|
dff_s #(8) data_pipe_reg2 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( data_pipe_out1[7:0] ),
|
.din ( data_pipe_out1[7:0] ),
|
.q ( data_pipe_out2[7:0] ), .se(mbist_se), .si(), .so());
|
.q ( data_pipe_out2[7:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(8) data_pipe_reg3 (
|
dff_s #(8) data_pipe_reg3 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( data_pipe_out2[7:0] ),
|
.din ( data_pipe_out2[7:0] ),
|
.q ( data_pipe_out3[7:0] ), .se(mbist_se), .si(), .so());
|
.q ( data_pipe_out3[7:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(8) data_pipe_reg4 (
|
dff_s #(8) data_pipe_reg4 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( data_pipe_out3[7:0] ),
|
.din ( data_pipe_out3[7:0] ),
|
.q ( data_pipe_out4[7:0] ), .se(mbist_se), .si(), .so());
|
.q ( data_pipe_out4[7:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
////////////
|
////////////
|
////////////
|
////////////
|
|
|
wire [10:0] add_pipe_out3, add_pipe_out4;
|
wire [10:0] add_pipe_out3, add_pipe_out4;
|
wire mbist_word_sel_bf;
|
wire mbist_word_sel_bf;
|
|
|
assign mbist_word_sel_bf = loop_on_address ? useradd_out[6] : mbist_word_sel;
|
assign mbist_word_sel_bf = loop_on_address ? useradd_out[6] : mbist_word_sel;
|
|
|
dff #(11) add_pipe_reg1 (
|
dff_s #(11) add_pipe_reg1 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( {mbist_word_sel_bf, mbist_address_bf[9:0]} ),
|
.din ( {mbist_word_sel_bf, mbist_address_bf[9:0]} ),
|
.q ( add_pipe_out1[10:0] ), .se(mbist_se), .si(), .so());
|
.q ( add_pipe_out1[10:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign mbist_address = add_pipe_out1;
|
assign mbist_address = add_pipe_out1;
|
|
|
dff #(11) add_pipe_reg2 (
|
dff_s #(11) add_pipe_reg2 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( add_pipe_out1[10:0] ),
|
.din ( add_pipe_out1[10:0] ),
|
.q ( add_pipe_out2[10:0] ), .se(mbist_se), .si(), .so());
|
.q ( add_pipe_out2[10:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(11) add_pipe_reg3 (
|
dff_s #(11) add_pipe_reg3 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( add_pipe_out2[10:0] ),
|
.din ( add_pipe_out2[10:0] ),
|
.q ( add_pipe_out3[10:0] ), .se(mbist_se), .si(), .so());
|
.q ( add_pipe_out3[10:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(11) add_pipe_reg4 (
|
dff_s #(11) add_pipe_reg4 (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( add_pipe_out3[10:0] ),
|
.din ( add_pipe_out3[10:0] ),
|
.q ( add_pipe_out4[10:0] ), .se(mbist_se), .si(), .so());
|
.q ( add_pipe_out4[10:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
assign dcache_piped_address[9:0] = {add_pipe_out4[10], add_pipe_out4[8:0]};
|
assign dcache_piped_address[9:0] = {add_pipe_out4[10], add_pipe_out4[8:0]};
|
assign icache_piped_address[10:0] = add_pipe_out4[10:0];
|
assign icache_piped_address[10:0] = add_pipe_out4[10:0];
|
|
|
// /////////////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////////////
|
// Shared Fail Detection
|
// Shared Fail Detection
|
// /////////////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////////////
|
|
|
dff #(2) fail_reg (
|
dff_s #(2) fail_reg (
|
.clk ( rclk ),
|
.clk ( rclk ),
|
.din ( fail_reg_in[1:0] ),
|
.din ( fail_reg_in[1:0] ),
|
.q ( fail_reg_out[1:0] ), .se(mbist_se), .si(), .so());
|
.q ( fail_reg_out[1:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
assign fail_reg_in[1:0] = reset_engine ? 2'b0: {qual_dcache_fail,qual_icache_fail} | fail_reg_out[1:0];
|
assign fail_reg_in[1:0] = reset_engine ? 2'b0: {qual_dcache_fail,qual_icache_fail} | fail_reg_out[1:0];
|
|
|
|
|
Line 559... |
Line 564... |
(icache_piped_read ? {2{data_pipe_out4[1:0]}} : data_pipe_out4[3:0]), {7{data_pipe_out4[7:0]}},
|
(icache_piped_read ? {2{data_pipe_out4[1:0]}} : data_pipe_out4[3:0]), {7{data_pipe_out4[7:0]}},
|
(icache_piped_read ? data_pipe_out4[7:4] : data_pipe_out4[3:0]), data_pipe_out4[3:0] };
|
(icache_piped_read ? data_pipe_out4[7:4] : data_pipe_out4[3:0]), data_pipe_out4[3:0] };
|
|
|
assign compare_data_bf[71:0] = dcache_data_sel ? mbist_dcache_data_in[71:0]: {4'h0,mbist_icache_data_in[67:0]};
|
assign compare_data_bf[71:0] = dcache_data_sel ? mbist_dcache_data_in[71:0]: {4'h0,mbist_icache_data_in[67:0]};
|
|
|
dff #(72) compare_data_inst(
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dff_s #(72) compare_data_inst(
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( compare_data_bf[71:0] ),
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.din ( compare_data_bf[71:0] ),
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.q ( compare_data[71:0] ), .se(mbist_se), .si(), .so());
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.q ( compare_data[71:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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assign mismatch = expect_data[71:0] != compare_data[71:0];
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assign mismatch = expect_data[71:0] != compare_data[71:0];
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assign mbist_dcache_fail = fail_reg_out[1];
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assign mbist_dcache_fail = fail_reg_out[1];
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Line 580... |
Line 585... |
// Fail Address and Data Capture and Control Reg Store
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// Fail Address and Data Capture and Control Reg Store
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// /////////////////////////////////////////////////////////////////////////////
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// /////////////////////////////////////////////////////////////////////////////
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dff #(11) fail_add_reg(
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dff_s #(11) fail_add_reg(
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( fail_add_reg_in[10:0] ),
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.din ( fail_add_reg_in[10:0] ),
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.q ( fail_add_reg_out[10:0] ), .se(mbist_se), .si(), .so());
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.q ( fail_add_reg_out[10:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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assign fail_add_reg_in[10:0] = reset_engine ? 11'b0:
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assign fail_add_reg_in[10:0] = reset_engine ? 11'b0:
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qual_dcache_fail ? {1'b0,dcache_piped_address[9:0]}:
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qual_dcache_fail ? {1'b0,dcache_piped_address[9:0]}:
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qual_icache_fail ? icache_piped_address[10:0]:
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qual_icache_fail ? icache_piped_address[10:0]:
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fail_add_reg_out[10:0];
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fail_add_reg_out[10:0];
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dff #(72) fail_data_reg(
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dff_s #(72) fail_data_reg(
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( fail_data_reg_in[71:0] ),
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.din ( fail_data_reg_in[71:0] ),
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.q ( fail_data_reg_out[71:0] ), .se(mbist_se), .si(), .so());
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.q ( fail_data_reg_out[71:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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assign fail_data_reg_in[71:0] = reset_engine ? 72'b0:
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assign fail_data_reg_in[71:0] = reset_engine ? 72'b0:
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qual_fail ? compare_data[71:0]:
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qual_fail ? compare_data[71:0]:
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fail_data_reg_out[71:0];
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fail_data_reg_out[71:0];
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Line 607... |
Line 612... |
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assign fail_control_reg_in[20:0] = (reset_engine && !mbist_stop_on_next_fail) ? 21'b0:
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assign fail_control_reg_in[20:0] = (reset_engine && !mbist_stop_on_next_fail) ? 21'b0:
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qual_fail ? qual_control_out[20:0]:
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qual_fail ? qual_control_out[20:0]:
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fail_control_reg_out[20:0];
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fail_control_reg_out[20:0];
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dff #(21) fail_control_reg_inst(
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dff_s #(21) fail_control_reg_inst(
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.clk ( rclk ),
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.clk ( rclk ),
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.din ( fail_control_reg_in[20:0] ),
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.din ( fail_control_reg_in[20:0] ),
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.q ( fail_control_reg_out[20:0] ), .se(mbist_se), .si(), .so());
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.q ( fail_control_reg_out[20:0] ), .se(mbist_se), `SIMPLY_RISC_SCANIN, .so());
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////////
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////////
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assign beyond_last_fail = qual_control_out[20:0] > fail_control_reg_out[20:0];
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assign beyond_last_fail = qual_control_out[20:0] > fail_control_reg_out[20:0];
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