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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : WbClkDomain-Rtl-ea.vhdl
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-- Owner : Rainer Kastl
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-- Description : Top level of wishbone clock domain
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-- Links :
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.Global.all;
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use work.Wishbone.all;
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use work.Sd.all;
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use work.SdWb.all;
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entity WbClkDomain is
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port (
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iWbClk : in std_ulogic;
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iWbRstSync : in std_ulogic;
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iCyc : in std_ulogic;
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iLock : in std_ulogic;
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iStb : in std_ulogic;
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iWe : in std_ulogic;
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iCti : in std_ulogic_vector(2 downto 0);
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iBte : in std_ulogic_vector(1 downto 0);
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iSel : in std_ulogic_vector(0 downto 0);
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iAdr : in std_ulogic_vector(6 downto 4);
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iDat : in std_ulogic_vector(31 downto 0);
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oDat : out std_ulogic_vector(31 downto 0);
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oAck : out std_ulogic;
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oErr : out std_ulogic;
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oRty : out std_ulogic;
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iWriteFifo : in aiWriteFifo;
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iReadFifo : in aiReadFifo;
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oWriteFifo : out aoWriteFifo;
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oReadFifo : out aoReadFifo;
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oWbToSdCtrl : out aSdWbSlaveToSdController;
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iSdCtrlToWb : in aSdControllerToSdWbSlave
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);
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end entity WbClkDomain;
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architecture Rtl of WbClkDomain is
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signal iWbCtrl : aWbSlaveCtrlInput;
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signal oWbCtrl : aWbSlaveCtrlOutput;
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signal iWbDat : aSdWbSlaveDataInput;
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signal oWbDat : aSdWbSlaveDataOutput;
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begin
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SdWbSlave_inst : entity work.SdWbSlave
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port map (
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iClk => iWbClk,
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iRstSync => iWbRstSync,
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-- wishbone
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iWbCtrl => iWbCtrl,
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oWbCtrl => oWbCtrl,
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iWbDat => iWbDat,
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oWbDat => oWbDat,
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-- To sd controller
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iController => iSdCtrlToWb,
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oController => oWbToSdCtrl,
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-- To write fifo
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oWriteFifo => oWriteFifo,
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iWriteFifo => iWriteFifo,
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-- To read fifo
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oReadFifo => oReadFifo,
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iReadFifo => iReadFifo
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);
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-- map wishbone signals to internal signals
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iWbCtrl <= (
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Cyc => iCyc,
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Lock => iLock,
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Stb => iStb,
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We => iWe,
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Cti => iCti,
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Bte => iBte
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);
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oAck <= oWbCtrl.Ack;
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oErr <= oWbCtrl.Err;
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oRty <= oWbCtrl.Rty;
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oDat <= oWbDat.Dat;
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iWbDat <= (
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Sel => iSel,
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Adr => iAdr,
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Dat => iDat
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);
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end architecture Rtl;
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