OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [ver_fig1.sch] - Diff between revs 28 and 39

Show entire file | Details | Blame | View Log

Rev 28 Rev 39
Line 53... Line 53...
T 56900 20300 9 10 1 0 0 0 1
T 56900 20300 9 10 1 0 0 0 1
LOG FILE
LOG FILE
B 56400 19100 2800 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 56400 19100 2800 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 56500 19300 9 10 1 0 0 0 1
T 56500 19300 9 10 1 0 0 0 1
VALUE CHANGE DUMP  FILE
VALUE CHANGE DUMP  FILE
L 55565 20197 56400 20300 3 0 0 0 -1 -1
L 55613 20072 56400 20300 3 0 0 0 -1 -1
L 55700 19400 56400 19300 3 0 0 0 -1 -1
L 55653 19452 56400 19300 3 0 0 0 -1 -1
L 54700 18700 54700 17400 3 0 0 0 -1 -1
L 54700 18700 54700 17400 3 0 0 0 -1 -1
L 54700 18700 54600 18600 3 0 0 0 -1 -1
L 54700 18700 54600 18600 3 0 0 0 -1 -1
L 54700 18700 54800 18600 3 0 0 0 -1 -1
L 54700 18700 54800 18600 3 0 0 0 -1 -1
T 54200 19600 9 10 1 0 0 0 2
T 54200 19600 9 10 1 0 0 0 2
  VERILOG
  VERILOG
SIMULATOR
SIMULATOR
L 56400 20300 56283 20335 3 0 0 0 -1 -1
L 56400 20300 56283 20335 3 0 0 0 -1 -1
L 56400 20300 56301 20223 3 0 0 0 -1 -1
L 56400 20300 56300 20200 3 0 0 0 -1 -1
L 56400 19300 56300 19400 3 0 0 0 -1 -1
L 56400 19300 56300 19400 3 0 0 0 -1 -1
L 56400 19300 56289 19228 3 0 0 0 -1 -1
L 56400 19300 56274 19243 3 0 0 0 -1 -1
T 51300 20600 9 10 1 0 0 0 2
T 51300 20500 9 10 1 0 0 0 2
  COMMAND
  COMMAND
LINE OPTIONS
LINE OPTIONS
T 51400 19800 9 10 1 0 0 0 2
T 51400 19600 9 10 1 0 0 0 2
FIRMWARE
FIRMWARE
BIT IMAGE
BIT IMAGE
T 51400 18900 9 10 1 0 0 0 2
T 51400 17800 9 10 1 0 0 0 2
EXPECTED
EXPECTED
VALUES
VALUES
B 51200 20400 1500 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 51200 20300 1500 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 51200 19600 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 51200 19400 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 51200 18700 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 51200 18500 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 52700 20800 53800 20100 3 0 0 0 -1 -1
L 52700 20800 53821 20187 3 0 0 0 -1 -1
L 52700 20000 53700 19500 3 0 0 0 -1 -1
L 52700 19800 53694 19722 3 0 0 0 -1 -1
L 52700 19000 54000 19000 3 0 0 0 -1 -1
L 52700 19000 53757 19362 3 0 0 0 -1 -1
L 54000 19000 53772 19084 3 0 0 0 -1 -1
L 53766 19368 53633 19412 3 0 0 0 -1 -1
L 54000 19000 53811 18890 3 0 0 0 -1 -1
L 53761 19363 53687 19263 3 0 0 0 -1 -1
L 53800 20100 53690 20271 3 0 0 0 -1 -1
L 53816 20196 53747 20331 3 0 0 0 -1 -1
L 53800 20100 53621 20122 3 0 0 0 -1 -1
L 53821 20177 53672 20162 3 0 0 0 -1 -1
L 53700 19500 53529 19692 3 0 0 0 -1 -1
L 53701 19722 53561 19840 3 0 0 0 -1 -1
L 53700 19500 53486 19480 3 0 0 0 -1 -1
L 53694 19715 53554 19641 3 0 0 0 -1 -1
B 56400 18100 2800 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 56400 18100 2800 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 55400 19000 56400 18300 3 0 0 0 -1 -1
L 55469 19065 56400 18300 3 0 0 0 -1 -1
L 56400 18300 56325 18474 3 0 0 0 -1 -1
L 56400 18300 56313 18439 3 0 0 0 -1 -1
L 56400 18300 56253 18287 3 0 0 0 -1 -1
L 56400 18300 56254 18325 3 0 0 0 -1 -1
T 56500 18300 9 10 1 0 0 0 1
T 56500 18300 9 10 1 0 0 0 1
RECORDED VALUES
RECORDED VALUES
B 51200 17700 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 51200 17600 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 51400 17900 9 10 1 0 0 0 2
T 51400 18700 9 10 1 0 0 0 2
INPUT
INPUT
DATA
DATA
L 52700 18000 54284 18789 3 0 0 0 -1 -1
L 52700 18000 53950 19050 3 0 0 0 -1 -1
L 54300 18800 54100 18800 3 0 0 0 -1 -1
L 53933 19058 53816 19050 3 0 0 0 -1 -1
L 54300 18800 54210 18637 3 0 0 0 -1 -1
L 53948 19053 53916 18906 3 0 0 0 -1 -1
L 53948 19053 53916 18906 3 0 0 0 -1 -1
L 53948 19053 53916 18906 3 0 0 0 -1 -1

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.