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https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
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../rtl/port_macro.v
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../rtl/port_macro.v
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../rtl/port_ring_tap_fsm.v
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../rtl/port_ring_tap_fsm.v
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../rtl/port_ring_tap.v
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../rtl/port_ring_tap.v
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../rtl/sd_rx_gigmac.v
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../rtl/sd_rx_gigmac.v
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../rtl/sd_tx_gigmac.v
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../rtl/sd_tx_gigmac.v
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../rtl/mac_crc32.v
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+libext+.v
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+libext+.v
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-y ../../../rtl/verilog/buffers
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-y ../../../rtl/verilog/buffers
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-y ../../../rtl/verilog/closure
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-y ../../../rtl/verilog/closure
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-y ../../../rtl/verilog/forks
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-y ../../../rtl/verilog/forks
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-y ../../../rtl/verilog/memory
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-y ../../../rtl/verilog/memory
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