URL
https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
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$dumpvars;
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$dumpvars;
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`endif
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`endif
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reset = 1;
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reset = 1;
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#200;
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#200;
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reset = 0;
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reset = 0;
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#200;
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end // initial begin
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repeat (`FIB_ENTRIES)
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@(posedge clk);
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fork
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driver0.send_packet (1, 2, 20);
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driver1.send_packet (2, 3, 64);
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driver2.send_packet (3, 4, 64);
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driver3.send_packet (4, 1, 64);
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join
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#2000;
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$finish;
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end
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire gmii_rx_clk_0; // From driver0 of gmii_driver.v
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wire gmii_rx_clk_0; // From driver0 of gmii_driver.v
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wire gmii_rx_clk_1; // From driver1 of gmii_driver.v
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wire gmii_rx_clk_1; // From driver1 of gmii_driver.v
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