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https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
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Rev 11 |
Line 65... |
Line 65... |
// Swap and Complement:
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// Swap and Complement:
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crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
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crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
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end
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end
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endtask
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endtask
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task print_packet;
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input [31:0] length;
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integer i;
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begin
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for (i=0; i<length; i=i+1)
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begin
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if (i % 16 == 0) $write ("%x: ", i[15:0]);
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$write ("%x ", rxbuf[i]);
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if (i % 16 == 7) $write ("| ");
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if (i % 16 == 15) $write ("\n");
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end
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if (i % 16 != 0) $write ("\n");
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end
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endtask
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task send_packet;
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task send_packet;
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input [47:0] da, sa;
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input [47:0] da, sa;
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input [15:0] length;
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input [15:0] length;
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integer p;
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integer p;
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begin
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begin
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Line 80... |
Line 95... |
gencrc32 (length);
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gencrc32 (length);
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{ rxbuf[length-4], rxbuf[length-3],
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{ rxbuf[length-4], rxbuf[length-3],
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rxbuf[length-2], rxbuf[length-1] } = crc32_result;
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rxbuf[length-2], rxbuf[length-1] } = crc32_result;
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$display ("%m : Sending packet DA=%x SA=%x of length %0d", da, sa, length);
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$display ("%m : Sending packet DA=%x SA=%x of length %0d", da, sa, length);
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print_packet (length);
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repeat (7)
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repeat (7)
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begin
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begin
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@(posedge rx_clk);
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@(posedge rx_clk);
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rx_dv <= #1 1;
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rx_dv <= #1 1;
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rxd <= #1 `GMII_PRE;
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rxd <= #1 `GMII_PRE;
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