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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [video.v] - Diff between revs 216 and 217
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| Rev 216 |
Rev 217 |
| Line 149... |
Line 149... |
endcase
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endcase
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end
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end
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else begin // writing!
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else begin // writing!
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case (address)
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case (address)
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6'h00: begin
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6'h00: begin
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VSYNC <= data;
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VSYNC <= data[1];
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end
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end
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6'h01: begin
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6'h01: begin
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VBLANK <= data;
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VBLANK <= {data[7:6], data[1]};
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end
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end
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6'h02: begin
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6'h02: begin
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WSYNC <= data;
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WSYNC <= 1'b1; // STROBE
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end
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end
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6'h03: begin
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6'h03: begin
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RSYNC <= data;
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RSYNC <= 1'b1; // STROBE
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end
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end
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6'h04: begin
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6'h04: begin
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NUSIZ0 <= data;
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NUSIZ0 <= data[5:0];
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end
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end
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6'h05: begin
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6'h05: begin
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NUSIZ1 <= data;
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NUSIZ1 <= data[5:0];
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end
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end
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6'h06: begin
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6'h06: begin
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COLUP0 <= data;
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COLUP0 <= data[7:1];
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end
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end
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6'h07: begin
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6'h07: begin
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COLUP1 <= data;
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COLUP1 <= data[7:1];
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end
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end
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6'h08: begin
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6'h08: begin
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COLUPF <= data;
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COLUPF <= data[7:1];
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end
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end
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6'h09: begin
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6'h09: begin
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COLUBK <= data;
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COLUBK <= data[7:1];
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end
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end
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6'h0a: begin
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6'h0a: begin
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CTRLPF <= data;
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CTRLPF <= {data[5:4], data[2:0]};
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end
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end
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6'h0b: begin
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6'h0b: begin
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NUSIZ1 <= data;
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REFP0 <= data[3];
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end
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end
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6'h0c: begin
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6'h0c: begin
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NUSIZ1 <= data;
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REFP1 <= data[3];
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end
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end
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6'h0d: begin
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PF0 <= data[7:4 ];
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end
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6'h0e: begin
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PF1 <= data;
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end
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6'h0f: begin
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PF2 <= data;
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end
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6'h10: begin
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RESP0 <= 1'b1; // STROBE
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end
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6'h11: begin
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RESP1 <= 1'b1; // STROBE
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end
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6'h12: begin
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RESM0 <= 1'b1; // STROBE
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end
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6'h13: begin
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RESM1 <= 1'b1; // STROBE
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end
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6'h14: begin
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RESBL <= 1'b1; // STROBE
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end
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6'h15: begin
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AUDC0 <= data[3:0];
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end
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6'h16: begin
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AUDC1 <= data[4:0];
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end
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6'h17: begin
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AUDF0 <= data[4:0];
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end
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6'h18: begin
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AUDF1 <= data[3:0];
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end
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6'h19: begin
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AUDV0 <= data[3:0];
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end
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6'h1A: begin
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AUDV1 <= data[3:0];
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end
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6'h1B: begin
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GRP0 <= data;
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end
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6'h1C: begin
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GRP1 <= data;
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end
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6'h1D: begin
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ENAM0 <= data[1];
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end
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6'h1E: begin
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ENAM1 <= data[1];
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end
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6'h1F: begin
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ENABL <= data[1];
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end
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6'h20: begin
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HMP0 <= data[7:4];
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end
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6'h21: begin
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HMP1 <= data[7:4];
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end
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6'h22: begin
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HMM0 <= data[7:4];
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end
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6'h23: begin
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HMM1 <= data[7:4];
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end
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6'h24: begin
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HMBL <= data[7:4];
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end
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6'h25: begin
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VDELP0 <= data[0];
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end
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6'h26: begin
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VDEL01 <= data[0];
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end
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6'h27: begin
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VDELBL <= data[0];
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end
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6'h28: begin
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RESMP0 <= data[1];
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end
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6'h29: begin
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RESMP1 <= data[1];
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end
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6'h2a: begin
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HMOVE <= 1'b1; // STROBE
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end
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6'h2b: begin
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HMCLR <= 1'b1; // STROBE
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end
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6'h2c: begin
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CXCLR <= 1'b1; // STROBE
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end
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default: begin
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default: begin
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end
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end
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endcase
|
endcase
|
end
|
end
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end
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end
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