| Line 36... |
Line 36... |
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// Approx. 100,000 LUTs. 160,000 LC's.
|
// Approx. 100,000 LUTs. 160,000 LC's.
|
|
// 38,000LUTs???
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
`include "FT64_config.vh"
|
`include "FT64_config.vh"
|
`include "FT64_defines.vh"
|
`include "FT64_defines.vh"
|
|
|
| Line 112... |
Line 113... |
parameter IQS_AGEN = 2'd1;
|
parameter IQS_AGEN = 2'd1;
|
parameter IQS_LDDONE = 2'd2;
|
parameter IQS_LDDONE = 2'd2;
|
parameter IQS_S3 = 2'd3;
|
parameter IQS_S3 = 2'd3;
|
|
|
wire clk;
|
wire clk;
|
BUFG uclkb1
|
//BUFG uclkb1
|
(
|
//(
|
.I(clk_i),
|
// .I(clk_i),
|
.O(clk)
|
// .O(clk)
|
);
|
//);
|
|
assign clk = clk_i;
|
|
|
wire dc_ack;
|
wire dc_ack;
|
wire acki = ack_i|dc_ack;
|
wire acki = ack_i|dc_ack;
|
wire [RBIT:0] Ra0, Ra1;
|
wire [RBIT:0] Ra0, Ra1;
|
wire [RBIT:0] Rb0, Rb1;
|
wire [RBIT:0] Rb0, Rb1;
|
| Line 490... |
Line 492... |
reg [QENTRIES-1:0] iqentry_alu = 8'h00; // alu type instruction
|
reg [QENTRIES-1:0] iqentry_alu = 8'h00; // alu type instruction
|
reg [QENTRIES-1:0] iqentry_alu0; // only valid on alu #0
|
reg [QENTRIES-1:0] iqentry_alu0; // only valid on alu #0
|
reg [QENTRIES-1:0] iqentry_fpu; // floating point instruction
|
reg [QENTRIES-1:0] iqentry_fpu; // floating point instruction
|
reg [QENTRIES-1:0] iqentry_fc; // flow control instruction
|
reg [QENTRIES-1:0] iqentry_fc; // flow control instruction
|
reg [QENTRIES-1:0] iqentry_canex = 8'h00; // true if it's an instruction that can exception
|
reg [QENTRIES-1:0] iqentry_canex = 8'h00; // true if it's an instruction that can exception
|
|
reg [QENTRIES-1:0] iqentry_oddball = 8'h00; // writes to register file
|
reg [QENTRIES-1:0] iqentry_load; // is a memory load instruction
|
reg [QENTRIES-1:0] iqentry_load; // is a memory load instruction
|
|
reg [QENTRIES-1:0] iqentry_loadv; // is a volatile memory load instruction
|
|
reg [QENTRIES-1:0] iqentry_store; // is a memory store instruction
|
reg [QENTRIES-1:0] iqentry_preload; // is a memory preload instruction
|
reg [QENTRIES-1:0] iqentry_preload; // is a memory preload instruction
|
reg [QENTRIES-1:0] iqentry_ldcmp;
|
reg [QENTRIES-1:0] iqentry_ldcmp;
|
reg [QENTRIES-1:0] iqentry_mem; // touches memory: 1 if LW/SW
|
reg [QENTRIES-1:0] iqentry_mem; // touches memory: 1 if LW/SW
|
reg [QENTRIES-1:0] iqentry_memndx; // indexed memory operation
|
reg [QENTRIES-1:0] iqentry_memndx; // indexed memory operation
|
|
reg [2:0] iqentry_memsz [0:QENTRIES-1]; // size of memory op
|
reg [QENTRIES-1:0] iqentry_rmw; // memory RMW op
|
reg [QENTRIES-1:0] iqentry_rmw; // memory RMW op
|
reg [QENTRIES-1:0] iqentry_memdb;
|
reg [QENTRIES-1:0] iqentry_memdb;
|
reg [QENTRIES-1:0] iqentry_memsb;
|
reg [QENTRIES-1:0] iqentry_memsb;
|
reg [QENTRIES-1:0] iqentry_rtop;
|
reg [QENTRIES-1:0] iqentry_rtop;
|
reg [QENTRIES-1:0] iqentry_sei;
|
reg [QENTRIES-1:0] iqentry_sei;
|
| Line 838... |
Line 844... |
reg [3:0] dram0_id;
|
reg [3:0] dram0_id;
|
reg [`XBITS] dram0_exc;
|
reg [`XBITS] dram0_exc;
|
reg dram0_unc;
|
reg dram0_unc;
|
reg [2:0] dram0_memsize;
|
reg [2:0] dram0_memsize;
|
reg dram0_load; // is a load operation
|
reg dram0_load; // is a load operation
|
|
reg dram0_store;
|
reg [1:0] dram0_ol;
|
reg [1:0] dram0_ol;
|
reg [63:0] dram1_data;
|
reg [63:0] dram1_data;
|
reg [`ABITS] dram1_addr;
|
reg [`ABITS] dram1_addr;
|
reg [31:0] dram1_seg;
|
reg [31:0] dram1_seg;
|
reg [47:0] dram1_instr;
|
reg [47:0] dram1_instr;
|
| Line 851... |
Line 858... |
reg [3:0] dram1_id;
|
reg [3:0] dram1_id;
|
reg [`XBITS] dram1_exc;
|
reg [`XBITS] dram1_exc;
|
reg dram1_unc;
|
reg dram1_unc;
|
reg [2:0] dram1_memsize;
|
reg [2:0] dram1_memsize;
|
reg dram1_load;
|
reg dram1_load;
|
|
reg dram1_store;
|
reg [1:0] dram1_ol;
|
reg [1:0] dram1_ol;
|
reg [63:0] dram2_data;
|
reg [63:0] dram2_data;
|
reg [`ABITS] dram2_addr;
|
reg [`ABITS] dram2_addr;
|
reg [31:0] dram2_seg;
|
reg [31:0] dram2_seg;
|
reg [47:0] dram2_instr;
|
reg [47:0] dram2_instr;
|
| Line 864... |
Line 872... |
reg [3:0] dram2_id;
|
reg [3:0] dram2_id;
|
reg [`XBITS] dram2_exc;
|
reg [`XBITS] dram2_exc;
|
reg dram2_unc;
|
reg dram2_unc;
|
reg [2:0] dram2_memsize;
|
reg [2:0] dram2_memsize;
|
reg dram2_load;
|
reg dram2_load;
|
|
reg dram2_store;
|
reg [1:0] dram2_ol;
|
reg [1:0] dram2_ol;
|
|
|
reg dramA_v;
|
reg dramA_v;
|
reg [3:0] dramA_id;
|
reg [3:0] dramA_id;
|
reg [63:0] dramA_bus;
|
reg [63:0] dramA_bus;
|
| Line 1124... |
Line 1133... |
(
|
(
|
iqentry_instr[head1][`INSTRUCTION_OP]==`JAL ||
|
iqentry_instr[head1][`INSTRUCTION_OP]==`JAL ||
|
iqentry_instr[head1][`INSTRUCTION_OP]==`BRK ||
|
iqentry_instr[head1][`INSTRUCTION_OP]==`BRK ||
|
IsRTI(iqentry_instr[head1]));
|
IsRTI(iqentry_instr[head1]));
|
|
|
`ifdef FCU_ENH
|
|
wire fcu_clk;
|
wire fcu_clk;
|
BUFGCE ufcuclk
|
`ifdef FCU_ENH
|
(
|
//BUFGCE ufcuclk
|
.I(clk_i),
|
//(
|
.CE(fcu_available),
|
// .I(clk_i),
|
.O(fcu_clk)
|
// .CE(fcu_available),
|
);
|
// .O(fcu_clk)
|
|
//);
|
`endif
|
`endif
|
|
assign fcu_clk = clk_i;
|
|
|
`ifdef FCU_ENH
|
`ifdef FCU_ENH
|
FT64_BTB ubtb1
|
FT64_BTB ubtb1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
| Line 1678... |
Line 1688... |
`VSHLV: fnRa = (vqei+1+isn[15:11] >= vli) ? 11'h000 : {vli-vqei-isn[15:11]-1,1'b1,isn[`INSTRUCTION_RA]};
|
`VSHLV: fnRa = (vqei+1+isn[15:11] >= vli) ? 11'h000 : {vli-vqei-isn[15:11]-1,1'b1,isn[`INSTRUCTION_RA]};
|
`VSHRV: fnRa = (vqei+isn[15:11] >= vli) ? 11'h000 : {vqei+isn[15:11],1'b1,isn[`INSTRUCTION_RA]};
|
`VSHRV: fnRa = (vqei+isn[15:11] >= vli) ? 11'h000 : {vqei+isn[15:11],1'b1,isn[`INSTRUCTION_RA]};
|
`VSxx,`VSxxU,`VSxxS,`VSxxSU: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
`VSxx,`VSxxU,`VSxxS,`VSxxSU: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
default: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
default: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
`R2: case(isn[`INSTRUCTION_S2])
|
`R2: casez(isn[`INSTRUCTION_S2])
|
`MOV:
|
`MOV:
|
case(isn[25:23])
|
case(isn[25:23])
|
3'd0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
| Line 1784... |
Line 1794... |
`VEINS: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]}; // ToDo: add element # from Ra
|
`VEINS: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]}; // ToDo: add element # from Ra
|
`V2BITS: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
`V2BITS: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
default: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
|
|
`R2: case(isn[`INSTRUCTION_S2])
|
`R2: casez(isn[`INSTRUCTION_S2])
|
`MOV:
|
`MOV:
|
case(isn[25:23])
|
case(isn[25:23])
|
3'd0: fnRt = {isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd0: fnRt = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
| Line 1880... |
Line 1890... |
`VSHLV: fnRa = (vqei+1+isn[15:11] >= vli) ? 11'h000 : {vli-vqei-isn[15:11]-1,1'b1,isn[`INSTRUCTION_RA]};
|
`VSHLV: fnRa = (vqei+1+isn[15:11] >= vli) ? 11'h000 : {vli-vqei-isn[15:11]-1,1'b1,isn[`INSTRUCTION_RA]};
|
`VSHRV: fnRa = (vqei+isn[15:11] >= vli) ? 11'h000 : {vqei+isn[15:11],1'b1,isn[`INSTRUCTION_RA]};
|
`VSHRV: fnRa = (vqei+isn[15:11] >= vli) ? 11'h000 : {vqei+isn[15:11],1'b1,isn[`INSTRUCTION_RA]};
|
`VSxx,`VSxxU,`VSxxS,`VSxxSU: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
`VSxx,`VSxxU,`VSxxS,`VSxxSU: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
default: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
default: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
`RR: case(isn[`INSTRUCTION_S2])
|
`R2:
|
|
casez(isn[`INSTRUCTION_S2])
|
`MOV:
|
`MOV:
|
case(isn[25:23])
|
case(isn[25:23])
|
3'd0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp1_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp1_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp1_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp1_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
| Line 2004... |
Line 2015... |
`VEINS: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]}; // ToDo: add element # from Ra
|
`VEINS: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]}; // ToDo: add element # from Ra
|
`V2BITS: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
`V2BITS: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
default: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
|
|
`R2: case(isn[`INSTRUCTION_S2])
|
`R2:
|
|
casez(isn[`INSTRUCTION_S2])
|
`MOV:
|
`MOV:
|
case(isn[25:23])
|
case(isn[25:23])
|
3'd0: fnRt = {isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd0: fnRt = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp1_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp1_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
| Line 2105... |
Line 2117... |
`SHIFT63: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
`SHIFT63: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
`SLT,`SLTU,`SLE,`SLEU,
|
`SLT,`SLTU,`SLE,`SLEU,
|
`ADD,`SUB,
|
`ADD,`SUB,
|
`AND,`OR,`XOR,
|
`AND,`OR,`XOR,
|
`NAND,`NOR,`XNOR,
|
`NAND,`NOR,`XNOR,
|
`DIVMOD,`DIVMODU,`DIVMODSU,
|
`DIV,`DIVU,`DIVSU,
|
`MUL,`MULU,`MULSU:
|
`MOD,`MODU,`MODSU,
|
|
`MUL,`MULU,`MULSU,
|
|
`MULH,`MULUH,`MULSUH:
|
case(isn[25:23])
|
case(isn[25:23])
|
3'b000: fnWe = 8'h01;
|
3'b000: fnWe = 8'h01;
|
3'b001: fnWe = 8'h03;
|
3'b001: fnWe = 8'h03;
|
3'b010: fnWe = 8'h0F;
|
3'b010: fnWe = 8'h0F;
|
3'b011: fnWe = 8'hFF;
|
3'b011: fnWe = 8'hFF;
|
| Line 2416... |
Line 2430... |
`LCX: IsLoad = TRUE;
|
`LCX: IsLoad = TRUE;
|
`LCUX: IsLoad = TRUE;
|
`LCUX: IsLoad = TRUE;
|
`LHX: IsLoad = TRUE;
|
`LHX: IsLoad = TRUE;
|
`LHUX: IsLoad = TRUE;
|
`LHUX: IsLoad = TRUE;
|
`LWX: IsLoad = TRUE;
|
`LWX: IsLoad = TRUE;
|
|
`LVBX: IsLoad = TRUE;
|
|
`LVBUX: IsLoad = TRUE;
|
|
`LVCX: IsLoad = TRUE;
|
|
`LVCUX: IsLoad = TRUE;
|
|
`LVHX: IsLoad = TRUE;
|
|
`LVHUX: IsLoad = TRUE;
|
|
`LVWX: IsLoad = TRUE;
|
`LWRX: IsLoad = TRUE;
|
`LWRX: IsLoad = TRUE;
|
`LVX: IsLoad = TRUE;
|
`LVX: IsLoad = TRUE;
|
`LVx: IsLoad = TRUE;
|
`LVx: IsLoad = TRUE;
|
default: IsLoad = FALSE;
|
default: IsLoad = FALSE;
|
endcase
|
endcase
|
| Line 2434... |
Line 2455... |
`LVx: IsLoad = TRUE;
|
`LVx: IsLoad = TRUE;
|
default: IsLoad = FALSE;
|
default: IsLoad = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsVolatileLoad;
|
|
input [47:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`MEMNDX:
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
|
case(isn[`INSTRUCTION_S2])
|
|
`LWRX: IsVolatileLoad = TRUE;
|
|
`LVx: IsVolatileLoad = TRUE;
|
|
default: IsVolatileLoad = FALSE;
|
|
endcase
|
|
else
|
|
IsVolatileLoad = FALSE;
|
|
`LWR: IsVolatileLoad = TRUE;
|
|
`LVx: IsVolatileLoad = TRUE;
|
|
default: IsVolatileLoad = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
|
function [2:0] MemSize;
|
|
input [47:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`MEMNDX:
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
|
case(isn[`INSTRUCTION_S2])
|
|
`LBX,`LBUX,`SBX: MemSize = byt;
|
|
`LCX,`LCUX,`SCX: MemSize = wyde;
|
|
`LHX,`SHX: MemSize = tetra;
|
|
`LHUX: MemSize = tetra;
|
|
`LWX,`SWX: MemSize = octa;
|
|
`LWRX,`SWCX: MemSize = octa;
|
|
`LVX,`SVX: MemSize = octa;
|
|
`LVx:
|
|
case(isn[25:23])
|
|
3'd0,3'd1: MemSize = byt;
|
|
3'd2,3'd3: MemSize = wyde;
|
|
3'd4,3'd5: MemSize = tetra;
|
|
default: MemSize = octa;
|
|
endcase
|
|
default: MemSize = octa;
|
|
endcase
|
|
else
|
|
MemSize = octa;
|
|
`LB,`LBU,`SB: MemSize = byt;
|
|
`Lx,`LxU,`Sx:
|
|
casez(isn[20:18])
|
|
3'b100: MemSize = octa;
|
|
3'b?10: MemSize = tetra;
|
|
3'b??1: MemSize = wyde;
|
|
default: MemSize = octa;
|
|
endcase
|
|
`LWR,`SWC: MemSize = octa;
|
|
`LV,`SV: MemSize = octa;
|
|
`AMO:
|
|
case(isn[23:21])
|
|
3'd0: MemSize = byt;
|
|
3'd1: MemSize = wyde;
|
|
3'd2: MemSize = tetra;
|
|
3'd3: MemSize = octa;
|
|
default: MemSize = octa;
|
|
endcase
|
|
`LVx:
|
|
case(isn[30:28])
|
|
3'd0,3'd1: MemSize = byt;
|
|
3'd2,3'd3: MemSize = wyde;
|
|
3'd4,3'd5: MemSize = tetra;
|
|
default: MemSize = octa;
|
|
endcase
|
|
default: MemSize = octa;
|
|
endcase
|
|
endfunction
|
|
|
|
function IsStore;
|
|
input [47:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`MEMNDX:
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
|
case(isn[`INSTRUCTION_S2])
|
|
`SBX: IsStore = TRUE;
|
|
`SCX: IsStore = TRUE;
|
|
`SHX: IsStore = TRUE;
|
|
`SWX: IsStore = TRUE;
|
|
`SWCX: IsStore = TRUE;
|
|
`SVX: IsStore = TRUE;
|
|
`CASX: IsStore = TRUE;
|
|
`INC: IsStore = TRUE;
|
|
default: IsStore = FALSE;
|
|
endcase
|
|
else
|
|
IsStore = FALSE;
|
|
`SB: IsStore = TRUE;
|
|
`Sx: IsStore = TRUE;
|
|
`SWC: IsStore = TRUE;
|
|
`INC: IsStore = TRUE;
|
|
`SV: IsStore = TRUE;
|
|
`CAS: IsStore = TRUE;
|
|
`AMO: IsStore = TRUE;
|
|
default: IsStore = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
|
function IsInc;
|
function IsInc;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX:
|
`MEMNDX:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| Line 2742... |
Line 2663... |
`CACHE: CacheCmd = isn[15:11];
|
`CACHE: CacheCmd = isn[15:11];
|
default: CacheCmd = 5'd0;
|
default: CacheCmd = 5'd0;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsSync;
|
|
input [47:0] isn;
|
|
IsSync = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`SYNC);
|
|
endfunction
|
|
|
|
function IsFSync;
|
|
input [47:0] isn;
|
|
IsFSync = (isn[`INSTRUCTION_OP]==`FLOAT && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`FSYNC);
|
|
endfunction
|
|
|
|
function IsMemsb;
|
function IsMemsb;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsMemsb = (isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMSB);
|
IsMemsb = (isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMSB);
|
endfunction
|
endfunction
|
|
|
| Line 2805... |
Line 2716... |
`OR: IsRFW = TRUE;
|
`OR: IsRFW = TRUE;
|
`XOR: IsRFW = TRUE;
|
`XOR: IsRFW = TRUE;
|
`MULU: IsRFW = TRUE;
|
`MULU: IsRFW = TRUE;
|
`MULSU: IsRFW = TRUE;
|
`MULSU: IsRFW = TRUE;
|
`MUL: IsRFW = TRUE;
|
`MUL: IsRFW = TRUE;
|
`DIVMODU: IsRFW = TRUE;
|
`MULUH: IsRFW = TRUE;
|
`DIVMODSU: IsRFW = TRUE;
|
`MULSUH: IsRFW = TRUE;
|
`DIVMOD:IsRFW = TRUE;
|
`MULH: IsRFW = TRUE;
|
|
`DIVU: IsRFW = TRUE;
|
|
`DIVSU: IsRFW = TRUE;
|
|
`DIV:IsRFW = TRUE;
|
|
`MODU: IsRFW = TRUE;
|
|
`MODSU: IsRFW = TRUE;
|
|
`MOD:IsRFW = TRUE;
|
`MOV: IsRFW = TRUE;
|
`MOV: IsRFW = TRUE;
|
`VMOV: IsRFW = TRUE;
|
`VMOV: IsRFW = TRUE;
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
IsRFW = TRUE;
|
IsRFW = TRUE;
|
`MIN,`MAX: IsRFW = TRUE;
|
`MIN,`MAX: IsRFW = TRUE;
|
| Line 2828... |
Line 2745... |
`LCX: IsRFW = TRUE;
|
`LCX: IsRFW = TRUE;
|
`LCUX: IsRFW = TRUE;
|
`LCUX: IsRFW = TRUE;
|
`LHX: IsRFW = TRUE;
|
`LHX: IsRFW = TRUE;
|
`LHUX: IsRFW = TRUE;
|
`LHUX: IsRFW = TRUE;
|
`LWX: IsRFW = TRUE;
|
`LWX: IsRFW = TRUE;
|
|
`LVBX: IsRFW = TRUE;
|
|
`LVBUX: IsRFW = TRUE;
|
|
`LVCX: IsRFW = TRUE;
|
|
`LVCUX: IsRFW = TRUE;
|
|
`LVHX: IsRFW = TRUE;
|
|
`LVHUX: IsRFW = TRUE;
|
|
`LVWX: IsRFW = TRUE;
|
`LWRX: IsRFW = TRUE;
|
`LWRX: IsRFW = TRUE;
|
`LVX: IsRFW = TRUE;
|
`LVX: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
|
`CASX: IsRFW = TRUE;
|
`CASX: IsRFW = TRUE;
|
default: IsRFW = FALSE;
|
default: IsRFW = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsRFW = FALSE;
|
IsRFW = FALSE;
|
| Line 2906... |
Line 2829... |
endfunction
|
endfunction
|
|
|
function IsMul;
|
function IsMul;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`RR:
|
`R2:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`MULU,`MULSU,`MUL: IsMul = TRUE;
|
`MULU,`MULSU,`MUL: IsMul = TRUE;
|
|
`MULUH,`MULSUH,`MULH: IsMul = TRUE;
|
default: IsMul = FALSE;
|
default: IsMul = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsMul = FALSE;
|
IsMul = FALSE;
|
`MULUI,`MULI: IsMul = TRUE;
|
`MULUI,`MULI: IsMul = TRUE;
|
| Line 2922... |
Line 2846... |
endfunction
|
endfunction
|
|
|
function IsDivmod;
|
function IsDivmod;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`RR:
|
`R2:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`DIVMODU,`DIVMODSU,`DIVMOD: IsDivmod = TRUE;
|
`DIVU,`DIVSU,`DIV: IsDivmod = TRUE;
|
|
`MODU,`MODSU,`MOD: IsDivmod = TRUE;
|
default: IsDivmod = FALSE;
|
default: IsDivmod = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsDivmod = FALSE;
|
IsDivmod = FALSE;
|
`DIVUI,`DIVI,`MODI: IsDivmod = TRUE;
|
`DIVUI,`DIVI,`MODI: IsDivmod = TRUE;
|
| Line 5365... |
Line 5290... |
wire [4:0] id1_ido, id2_ido, id3_ido;
|
wire [4:0] id1_ido, id2_ido, id3_ido;
|
wire id1_vo, id2_vo, id3_vo;
|
wire id1_vo, id2_vo, id3_vo;
|
wire id1_clk, id2_clk, id3_clk;
|
wire id1_clk, id2_clk, id3_clk;
|
|
|
// Always at least one decoder
|
// Always at least one decoder
|
BUFGCE uclkb2
|
assign id1_clk = clk_i;
|
(
|
//BUFGCE uclkb2
|
.I(clk_i),
|
//(
|
.CE(id1_available),
|
// .I(clk_i),
|
.O(id1_clk)
|
// .CE(id1_available),
|
);
|
// .O(id1_clk)
|
|
//);
|
|
|
FT64_idecoder uid1
|
FT64_idecoder uid1
|
(
|
(
|
.clk(id1_clk),
|
.clk(id1_clk),
|
.idv_i(id1_vi),
|
.idv_i(id1_vi),
|
| Line 5390... |
Line 5316... |
.idv_o(id1_vo)
|
.idv_o(id1_vo)
|
);
|
);
|
|
|
generate begin : gIDUInst
|
generate begin : gIDUInst
|
if (`NUM_IDU > 1) begin
|
if (`NUM_IDU > 1) begin
|
BUFGCE uclkb3
|
//BUFGCE uclkb3
|
(
|
//(
|
.I(clk_i),
|
// .I(clk_i),
|
.CE(id2_available),
|
// .CE(id2_available),
|
.O(id2_clk)
|
// .O(id2_clk)
|
);
|
//);
|
|
assign id2_clk = clk_i;
|
|
|
FT64_idecoder uid2
|
FT64_idecoder uid2
|
(
|
(
|
.clk(id2_clk),
|
.clk(id2_clk),
|
.idv_i(id2_vi),
|
.idv_i(id2_vi),
|
| Line 5414... |
Line 5341... |
.id_o(id2_ido),
|
.id_o(id2_ido),
|
.idv_o(id2_vo)
|
.idv_o(id2_vo)
|
);
|
);
|
end
|
end
|
if (`NUM_IDU > 2) begin
|
if (`NUM_IDU > 2) begin
|
BUFGCE uclkb4
|
//BUFGCE uclkb4
|
(
|
//(
|
.I(clk_i),
|
// .I(clk_i),
|
.CE(id3_available),
|
// .CE(id3_available),
|
.O(id3_clk)
|
// .O(id3_clk)
|
);
|
//);
|
|
assign id3_clk = clk_i;
|
|
|
FT64_idecoder uid2
|
FT64_idecoder uid2
|
(
|
(
|
.clk(id3_clk),
|
.clk(id3_clk),
|
.idv_i(id3_vi),
|
.idv_i(id3_vi),
|
| Line 5509... |
Line 5437... |
endgenerate
|
endgenerate
|
|
|
generate begin : gFPUInst
|
generate begin : gFPUInst
|
if (`NUM_FPU > 0) begin
|
if (`NUM_FPU > 0) begin
|
wire fpu1_clk;
|
wire fpu1_clk;
|
BUFGCE ufpc1
|
//BUFGCE ufpc1
|
(
|
//(
|
.I(clk_i),
|
// .I(clk_i),
|
.CE(fpu1_available),
|
// .CE(fpu1_available),
|
.O(fpu1_clk)
|
// .O(fpu1_clk)
|
);
|
//);
|
|
assign fpu1_clk = clk_i;
|
|
|
fpUnit ufp1
|
fpUnit ufp1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(fpu1_clk),
|
.clk(fpu1_clk),
|
.clk4x(clk4x),
|
.clk4x(clk4x),
|
| Line 5535... |
Line 5465... |
.done(fpu1_done)
|
.done(fpu1_done)
|
);
|
);
|
end
|
end
|
if (`NUM_FPU > 1) begin
|
if (`NUM_FPU > 1) begin
|
wire fpu2_clk;
|
wire fpu2_clk;
|
BUFGCE ufpc2
|
//BUFGCE ufpc2
|
(
|
//(
|
.I(clk_i),
|
// .I(clk_i),
|
.CE(fpu2_available),
|
// .CE(fpu2_available),
|
.O(fpu2_clk)
|
// .O(fpu2_clk)
|
);
|
//);
|
|
assign fpu2_clk = clk_i;
|
fpUnit ufp1
|
fpUnit ufp1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(fpu2_clk),
|
.clk(fpu2_clk),
|
.clk4x(clk4x),
|
.clk4x(clk4x),
|
| Line 5771... |
Line 5702... |
iqentry_memready[4] = (iqentry_v[4] & iqentry_memopsvalid[4] & ~iqentry_memissue[4] & ~iqentry_done[4] & ~iqentry_out[4] & ~iqentry_stomp[4]),
|
iqentry_memready[4] = (iqentry_v[4] & iqentry_memopsvalid[4] & ~iqentry_memissue[4] & ~iqentry_done[4] & ~iqentry_out[4] & ~iqentry_stomp[4]),
|
iqentry_memready[5] = (iqentry_v[5] & iqentry_memopsvalid[5] & ~iqentry_memissue[5] & ~iqentry_done[5] & ~iqentry_out[5] & ~iqentry_stomp[5]),
|
iqentry_memready[5] = (iqentry_v[5] & iqentry_memopsvalid[5] & ~iqentry_memissue[5] & ~iqentry_done[5] & ~iqentry_out[5] & ~iqentry_stomp[5]),
|
iqentry_memready[6] = (iqentry_v[6] & iqentry_memopsvalid[6] & ~iqentry_memissue[6] & ~iqentry_done[6] & ~iqentry_out[6] & ~iqentry_stomp[6]),
|
iqentry_memready[6] = (iqentry_v[6] & iqentry_memopsvalid[6] & ~iqentry_memissue[6] & ~iqentry_done[6] & ~iqentry_out[6] & ~iqentry_stomp[6]),
|
iqentry_memready[7] = (iqentry_v[7] & iqentry_memopsvalid[7] & ~iqentry_memissue[7] & ~iqentry_done[7] & ~iqentry_out[7] & ~iqentry_stomp[7]);
|
iqentry_memready[7] = (iqentry_v[7] & iqentry_memopsvalid[7] & ~iqentry_memissue[7] & ~iqentry_done[7] & ~iqentry_out[7] & ~iqentry_stomp[7]);
|
|
|
assign outstanding_stores = (dram0 && IsStore(dram0_instr)) ||
|
assign outstanding_stores = (dram0 && dram0_store) ||
|
(dram1 && IsStore(dram1_instr)) ||
|
(dram1 && dram1_store) ||
|
(dram2 && IsStore(dram2_instr));
|
(dram2 && dram2_store);
|
|
|
//
|
//
|
// additional COMMIT logic
|
// additional COMMIT logic
|
//
|
//
|
always @*
|
always @*
|
| Line 6294... |
Line 6225... |
cr0[17] <= 1'b0;
|
cr0[17] <= 1'b0;
|
if (waitctr != 64'd0)
|
if (waitctr != 64'd0)
|
waitctr <= waitctr - 64'd1;
|
waitctr <= waitctr - 64'd1;
|
|
|
|
|
if (IsFlowCtrl(iqentry_instr[fcu_id[`QBITS]]) && iqentry_v[fcu_id[`QBITS]] && !iqentry_done[fcu_id[`QBITS]] && iqentry_out[fcu_id[`QBITS]])
|
if (iqentry_fc[fcu_id[`QBITS]] && iqentry_v[fcu_id[`QBITS]] && !iqentry_done[fcu_id[`QBITS]] && iqentry_out[fcu_id[`QBITS]])
|
fcu_timeout <= fcu_timeout + 8'd1;
|
fcu_timeout <= fcu_timeout + 8'd1;
|
|
|
if (branchmiss) begin
|
if (branchmiss) begin
|
for (n = 1; n < PREGS; n = n + 1)
|
for (n = 1; n < PREGS; n = n + 1)
|
if (~livetarget[n]) begin
|
if (~livetarget[n]) begin
|
| Line 7048... |
Line 6979... |
end
|
end
|
|
|
//
|
//
|
// set the IQ entry == DONE as soon as the SW is let loose to the memory system
|
// set the IQ entry == DONE as soon as the SW is let loose to the memory system
|
//
|
//
|
if (mem1_available && dram0 == `DRAMSLOT_BUSY && IsStore(dram0_instr)) begin
|
if (mem1_available && dram0 == `DRAMSLOT_BUSY && dram0_store) begin
|
if ((alu0_v && (dram0_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram0_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
if ((alu0_v && (dram0_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram0_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
iqentry_done[ dram0_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dram0_id[`QBITS] ] <= `VAL;
|
iqentry_out[ dram0_id[`QBITS] ] <= `INV;
|
iqentry_out[ dram0_id[`QBITS] ] <= `INV;
|
end
|
end
|
if (mem2_available && `NUM_MEM > 1 && dram1 == `DRAMSLOT_BUSY && IsStore(dram1_instr)) begin
|
if (mem2_available && `NUM_MEM > 1 && dram1 == `DRAMSLOT_BUSY && dram1_store) begin
|
if ((alu0_v && (dram1_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram1_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
if ((alu0_v && (dram1_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram1_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
iqentry_done[ dram1_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dram1_id[`QBITS] ] <= `VAL;
|
iqentry_out[ dram1_id[`QBITS] ] <= `INV;
|
iqentry_out[ dram1_id[`QBITS] ] <= `INV;
|
end
|
end
|
if (mem3_available && `NUM_MEM > 2 && dram2 == `DRAMSLOT_BUSY && IsStore(dram2_instr)) begin
|
if (mem3_available && `NUM_MEM > 2 && dram2 == `DRAMSLOT_BUSY && dram2_store) begin
|
if ((alu0_v && (dram2_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram2_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
if ((alu0_v && (dram2_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram2_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
iqentry_done[ dram2_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dram2_id[`QBITS] ] <= `VAL;
|
iqentry_out[ dram2_id[`QBITS] ] <= `INV;
|
iqentry_out[ dram2_id[`QBITS] ] <= `INV;
|
end
|
end
|
|
|
| Line 7447... |
Line 7378... |
dram0 <= `DRAMSLOT_AVAIL;
|
dram0 <= `DRAMSLOT_AVAIL;
|
dramA_v <= dram0_load;
|
dramA_v <= dram0_load;
|
dramA_id <= dram0_id;
|
dramA_id <= dram0_id;
|
dramA_exc <= dram0_exc;
|
dramA_exc <= dram0_exc;
|
dramA_bus <= fnDati(dram0_instr,dram0_addr,rdat0);
|
dramA_bus <= fnDati(dram0_instr,dram0_addr,rdat0);
|
if (IsStore(dram0_instr)) $display("m[%h] <- %h", dram0_addr, dram0_data);
|
if (dram0_store) $display("m[%h] <- %h", dram0_addr, dram0_data);
|
end
|
end
|
// else
|
// else
|
// dramA_v <= `INV;
|
// dramA_v <= `INV;
|
if (mem2_available && dram1 == `DRAMREQ_READY && `NUM_MEM > 1) begin
|
if (mem2_available && dram1 == `DRAMREQ_READY && `NUM_MEM > 1) begin
|
dram1 <= `DRAMSLOT_AVAIL;
|
dram1 <= `DRAMSLOT_AVAIL;
|
dramB_v <= dram1_load;
|
dramB_v <= dram1_load;
|
dramB_id <= dram1_id;
|
dramB_id <= dram1_id;
|
dramB_exc <= dram1_exc;
|
dramB_exc <= dram1_exc;
|
dramB_bus <= fnDati(dram1_instr,dram1_addr,rdat1);
|
dramB_bus <= fnDati(dram1_instr,dram1_addr,rdat1);
|
if (IsStore(dram1_instr)) $display("m[%h] <- %h", dram1_addr, dram1_data);
|
if (dram1_store) $display("m[%h] <- %h", dram1_addr, dram1_data);
|
end
|
end
|
// else
|
// else
|
// dramB_v <= `INV;
|
// dramB_v <= `INV;
|
if (mem3_available && dram2 == `DRAMREQ_READY && `NUM_MEM > 2) begin
|
if (mem3_available && dram2 == `DRAMREQ_READY && `NUM_MEM > 2) begin
|
dram2 <= `DRAMSLOT_AVAIL;
|
dram2 <= `DRAMSLOT_AVAIL;
|
dramC_v <= dram2_load;
|
dramC_v <= dram2_load;
|
dramC_id <= dram2_id;
|
dramC_id <= dram2_id;
|
dramC_exc <= dram2_exc;
|
dramC_exc <= dram2_exc;
|
dramC_bus <= fnDati(dram2_instr,dram2_addr,rdat2);
|
dramC_bus <= fnDati(dram2_instr,dram2_addr,rdat2);
|
if (IsStore(dram2_instr)) $display("m[%h] <- %h", dram2_addr, dram2_data);
|
if (dram2_store) $display("m[%h] <- %h", dram2_addr, dram2_data);
|
end
|
end
|
// else
|
// else
|
// dramC_v <= `INV;
|
// dramC_v <= `INV;
|
|
|
//
|
//
|
| Line 7511... |
Line 7442... |
dram0_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram0_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram0_addr <= iqentry_a1[n];
|
dram0_addr <= iqentry_a1[n];
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// dram0_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// dram0_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// else
|
// else
|
dram0_unc <= iqentry_a1[n][31:20]==12'hFFD || !dce || IsVolatileLoad(iqentry_instr[n]);
|
dram0_unc <= iqentry_a1[n][39:20]==20'hFFFFD || !dce || iqentry_loadv[n];
|
dram0_memsize <= MemSize(iqentry_instr[n]);
|
dram0_memsize <= iqentry_memsz[n];
|
dram0_load <= iqentry_load[n];
|
dram0_load <= iqentry_load[n];
|
|
dram0_store <= iqentry_store[n];
|
dram0_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
dram0_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
// Once the memory op is issued reset the a1_v flag.
|
// Once the memory op is issued reset the a1_v flag.
|
// This will cause the a1 bus to look for new data from memory (a1_s is pointed to a memory bus)
|
// This will cause the a1 bus to look for new data from memory (a1_s is pointed to a memory bus)
|
// This is used for the load and compare instructions.
|
// This is used for the load and compare instructions.
|
iqentry_a1_v[n] <= `INV;
|
iqentry_a1_v[n] <= `INV;
|
| Line 7540... |
Line 7472... |
dram1_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram1_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram1_addr <= iqentry_a1[n];
|
dram1_addr <= iqentry_a1[n];
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// dram1_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// dram1_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// else
|
// else
|
dram1_unc <= iqentry_a1[n][31:20]==12'hFFD || !dce || IsVolatileLoad(iqentry_instr[n]);
|
dram1_unc <= iqentry_a1[n][39:20]==20'hFFFFD || !dce || iqentry_loadv[n];
|
dram1_memsize <= MemSize(iqentry_instr[n]);
|
dram1_memsize <= iqentry_memsz[n];
|
dram1_load <= iqentry_load[n];
|
dram1_load <= iqentry_load[n];
|
|
dram1_store <= iqentry_store[n];
|
dram1_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
dram1_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
iqentry_a1_v[n] <= `INV;
|
iqentry_a1_v[n] <= `INV;
|
last_issue = n;
|
last_issue = n;
|
end
|
end
|
end
|
end
|
| Line 7567... |
Line 7500... |
dram2_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram2_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram2_addr <= iqentry_a1[n];
|
dram2_addr <= iqentry_a1[n];
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// dram2_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// dram2_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// else
|
// else
|
dram2_unc <= iqentry_a1[n][31:20]==12'hFFD || !dce || IsVolatileLoad(iqentry_instr[n]);
|
dram2_unc <= iqentry_a1[n][39:20]==20'hFFFFD || !dce || iqentry_loadv[n];
|
dram2_memsize <= MemSize(iqentry_instr[n]);
|
dram2_memsize <= iqentry_memsz[n];
|
dram2_load <= iqentry_load[n];
|
dram2_load <= iqentry_load[n];
|
|
dram2_store <= iqentry_store[n];
|
dram2_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
dram2_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
iqentry_a1_v[n] <= `INV;
|
iqentry_a1_v[n] <= `INV;
|
end
|
end
|
end
|
end
|
end
|
end
|
| Line 7600... |
Line 7534... |
// always @(posedge clk) begin: commit_phase
|
// always @(posedge clk) begin: commit_phase
|
|
|
oddball_commit(commit0_v, head0);
|
oddball_commit(commit0_v, head0);
|
if (`NUM_CMT > 1)
|
if (`NUM_CMT > 1)
|
oddball_commit(commit1_v, head1);
|
oddball_commit(commit1_v, head1);
|
|
//if (`NUM_CMT > 2)
|
|
// oddball_commit(commit2_v, head2);
|
|
|
// Fetch and queue are limited to two instructions per cycle, so we might as
|
// Fetch and queue are limited to two instructions per cycle, so we might as
|
// well limit retiring to two instructions max to conserve logic.
|
// well limit retiring to two instructions max to conserve logic.
|
//
|
//
|
if (~|panic)
|
if (~|panic)
|
| Line 7648... |
Line 7584... |
end
|
end
|
else begin
|
else begin
|
head_inc(1);
|
head_inc(1);
|
end
|
end
|
6'b0?_11_11:
|
6'b0?_11_11:
|
if (`NUM_CMT > 2 || (`NUM_CMT > 1 && iqentry_tgt[head2] == 12'd0)) begin
|
if (`NUM_CMT > 2 || (`NUM_CMT > 1 && iqentry_tgt[head2] == 12'd0 && !iqentry_oddball[head2] && ~|iqentry_exc[head2])) begin
|
iqentry_v[head1] <= `INV;
|
iqentry_v[head1] <= `INV;
|
iqentry_v[head2] <= `INV;
|
iqentry_v[head2] <= `INV;
|
head_inc(3);
|
head_inc(3);
|
end
|
end
|
else if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
else if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
| Line 7684... |
Line 7620... |
iqentry_v[head0] <= `INV;
|
iqentry_v[head0] <= `INV;
|
head_inc(1);
|
head_inc(1);
|
end
|
end
|
6'b11_0?_11:
|
6'b11_0?_11:
|
if (head1 != tail0) begin
|
if (head1 != tail0) begin
|
if (`NUM_CMT > 2 || iqentry_tgt[head2]==12'd0) begin
|
if (`NUM_CMT > 2 || (iqentry_tgt[head2]==12'd0 && !iqentry_oddball[head2] && ~|iqentry_exc[head2])) begin
|
iqentry_v[head0] <= `INV;
|
iqentry_v[head0] <= `INV;
|
iqentry_v[head2] <= `INV;
|
iqentry_v[head2] <= `INV;
|
head_inc(3);
|
head_inc(3);
|
end
|
end
|
else begin
|
else begin
|
| Line 7734... |
Line 7670... |
else begin
|
else begin
|
iqentry_v[head0] <= `INV;
|
iqentry_v[head0] <= `INV;
|
head_inc(1);
|
head_inc(1);
|
end
|
end
|
6'b11_11_11:
|
6'b11_11_11:
|
if (`NUM_CMT > 2 || (`NUM_CMT > 1 && iqentry_tgt[head2]==12'd0)) begin
|
if (`NUM_CMT > 2 || (`NUM_CMT > 1 && iqentry_tgt[head2]==12'd0 && !iqentry_oddball[head2] && ~|iqentry_exc[head2])) begin
|
iqentry_v[head0] <= `INV;
|
iqentry_v[head0] <= `INV;
|
iqentry_v[head1] <= `INV;
|
iqentry_v[head1] <= `INV;
|
iqentry_v[head2] <= `INV;
|
iqentry_v[head2] <= `INV;
|
head_inc(3);
|
head_inc(3);
|
end
|
end
|
| Line 8023... |
Line 7959... |
dat_o <= fnDato(dram2_instr,dram2_data);
|
dat_o <= fnDato(dram2_instr,dram2_data);
|
ol_o <= dram2_ol;
|
ol_o <= dram2_ol;
|
bstate <= B12;
|
bstate <= B12;
|
end
|
end
|
end
|
end
|
else if (mem1_available && dram0==`DRAMSLOT_BUSY && IsStore(dram0_instr)) begin
|
else if (mem1_available && dram0==`DRAMSLOT_BUSY && dram0_store) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_smatch0) begin
|
if (dbg_smatch0) begin
|
dramA_v <= `TRUE;
|
dramA_v <= `TRUE;
|
dramA_id <= dram0_id;
|
dramA_id <= dram0_id;
|
dramA_exc <= `FLT_DBG;
|
dramA_exc <= `FLT_DBG;
|
| Line 8065... |
Line 8001... |
end
|
end
|
`endif
|
`endif
|
// cr_o <= IsSWC(dram0_instr);
|
// cr_o <= IsSWC(dram0_instr);
|
end
|
end
|
end
|
end
|
else if (mem2_available && dram1==`DRAMSLOT_BUSY && IsStore(dram1_instr) && `NUM_MEM > 1) begin
|
else if (mem2_available && dram1==`DRAMSLOT_BUSY && dram1_store && `NUM_MEM > 1) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_smatch1) begin
|
if (dbg_smatch1) begin
|
dramB_v <= `TRUE;
|
dramB_v <= `TRUE;
|
dramB_id <= dram1_id;
|
dramB_id <= dram1_id;
|
dramB_exc <= `FLT_DBG;
|
dramB_exc <= `FLT_DBG;
|
| Line 8107... |
Line 8043... |
end
|
end
|
`endif
|
`endif
|
// cr_o <= IsSWC(dram0_instr);
|
// cr_o <= IsSWC(dram0_instr);
|
end
|
end
|
end
|
end
|
else if (mem3_available && dram2==`DRAMSLOT_BUSY && IsStore(dram2_instr) && `NUM_MEM > 2) begin
|
else if (mem3_available && dram2==`DRAMSLOT_BUSY && dram2_store && `NUM_MEM > 2) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_smatch2) begin
|
if (dbg_smatch2) begin
|
dramC_v <= `TRUE;
|
dramC_v <= `TRUE;
|
dramC_id <= dram2_id;
|
dramC_id <= dram2_id;
|
dramC_exc <= `FLT_DBG;
|
dramC_exc <= `FLT_DBG;
|
| Line 9115... |
Line 9051... |
iqentry_alu [nn] <= bus[`IB_ALU];
|
iqentry_alu [nn] <= bus[`IB_ALU];
|
iqentry_alu0 [nn] <= bus[`IB_ALU0];
|
iqentry_alu0 [nn] <= bus[`IB_ALU0];
|
iqentry_fpu [nn] <= bus[`IB_FPU];
|
iqentry_fpu [nn] <= bus[`IB_FPU];
|
iqentry_fc [nn] <= bus[`IB_FC];
|
iqentry_fc [nn] <= bus[`IB_FC];
|
iqentry_canex[nn] <= bus[`IB_CANEX];
|
iqentry_canex[nn] <= bus[`IB_CANEX];
|
|
iqentry_loadv[nn] <= bus[`IB_LOADV];
|
iqentry_load [nn] <= bus[`IB_LOAD];
|
iqentry_load [nn] <= bus[`IB_LOAD];
|
iqentry_preload[nn]<= bus[`IB_PRELOAD];
|
iqentry_preload[nn]<= bus[`IB_PRELOAD];
|
|
iqentry_store[nn] <= bus[`IB_STORE];
|
|
iqentry_oddball[nn] <= bus[`IB_ODDBALL];
|
|
iqentry_memsz[nn] <= bus[`IB_MEMSZ];
|
iqentry_mem [nn] <= bus[`IB_MEM];
|
iqentry_mem [nn] <= bus[`IB_MEM];
|
iqentry_memndx[nn] <= bus[`IB_MEMNDX];
|
iqentry_memndx[nn] <= bus[`IB_MEMNDX];
|
iqentry_rmw [nn] <= bus[`IB_RMW];
|
iqentry_rmw [nn] <= bus[`IB_RMW];
|
iqentry_memdb[nn] <= bus[`IB_MEMDB];
|
iqentry_memdb[nn] <= bus[`IB_MEMDB];
|
iqentry_memsb[nn] <= bus[`IB_MEMSB];
|
iqentry_memsb[nn] <= bus[`IB_MEMSB];
|
| Line 9255... |
Line 9195... |
iqentry_a3_v [tail] <= Source3Valid(fetchbuf1_instr) | regIsValid[Rc1s];
|
iqentry_a3_v [tail] <= Source3Valid(fetchbuf1_instr) | regIsValid[Rc1s];
|
iqentry_a3_s [tail] <= rf_source[Rc1s];
|
iqentry_a3_s [tail] <= rf_source[Rc1s];
|
end
|
end
|
endtask
|
endtask
|
|
|
function IsOddball;
|
|
input [`QBITS] head;
|
|
if (|iqentry_exc[head])
|
|
IsOddball = TRUE;
|
|
else
|
|
case(iqentry_instr[head][`INSTRUCTION_OP])
|
|
`BRK: IsOddball = TRUE;
|
|
`IVECTOR:
|
|
case(iqentry_instr[head][`INSTRUCTION_S2])
|
|
`VSxx: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
`RR:
|
|
case(iqentry_instr[head][`INSTRUCTION_S2])
|
|
`VMOV: IsOddball = TRUE;
|
|
`SEI,`RTI,`CACHEX: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
`CSRRW,`REX,`CACHE,`FLOAT: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
|
// This task takes care of commits for things other than the register file.
|
// This task takes care of commits for things other than the register file.
|
task oddball_commit;
|
task oddball_commit;
|
input v;
|
input v;
|
input [`QBITS] head;
|
input [`QBITS] head;
|
reg thread;
|
reg thread;
|
