assert( MemAddr = x"0150")report"mov to IP doesn't work"severityerror;--DebugIP uses regOut, so it won't be updated until next clock cycle actually, but it's correct.
assert( MemAddr = x"0150")report"mov to IP doesn't work"severityerror;--DebugIP uses regOut, so it won't be updated until next clock cycle actually, but it's correct.
MemIn <= x"0020";--mov r0, 0x20
MemIn <= x"0020";--mov r0, 0x20
waitfor10ns;
waitfor10ns;
assert(MemAddr = x"0152"and DebugIP=x"50")report"fetching is wrong after move to IP"severityerror;--DebugIP uses regOut, Fetchaddress uses regIn, so this is correct
assert(MemAddr = x"0152"and DebugIP=x"50")report"fetching is wrong after move to IP"severityerror;--DebugIP uses regOut, Fetchaddress uses regIn, so this is correct
MemIn <= x"0160";--mov r0,0x60 if TR is set
waitfor10ns;--wait until register write happens
waitfor10ns;--wait until register write happens
assert(DebugR0 = x"20")report"mov to r0 is wrong after move to IP"severityerror;
assert(DebugR0 = x"20")report"mov to r0 is wrong after move to IP"severityerror;
MemIn <= x"1050";--mov [r0], 0x50 (r0 is 0x20)
waitfor10ns;
assert(DebugR0 = x"20"and DebugTR='0')report"moved to r0 conditional thought TR is 0"severityerror;
waitfor10ns;
waitfor10ns;--wait for memory
assert(MemAddr = x"0020"and MemWE='1' and MemWW='0' and MemOut=x"0050")report"Write to memory doesn't work"severityerror;
waitfor10ns;
--wait for 10 ns; --have to wait an extra cycle for memory