| Line 10... |
Line 10... |
-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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component registerfile
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component registerfile
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port(
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port(
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Write:in std_logic_vector(7 downto 0); --what should be put into the write register
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Write:in std_logic_vector(7 downto 0); --what should be put into the write register
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SelRead:in std_logic_vector(2 downto 0); --select which register to read
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SelRead1:in std_logic_vector(2 downto 0); --select which register to read
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SelRead2: in std_logic_vector(2 downto 0); --select second register to read
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SelWrite:in std_logic_vector(2 downto 0); --select which register to write
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SelWrite:in std_logic_vector(2 downto 0); --select which register to write
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UseWrite:in std_logic; --if the register should actually be written to
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UseWrite:in std_logic; --if the register should actually be written to
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Clock:in std_logic;
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Clock:in std_logic;
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Read:out std_logic_vector(7 downto 0) --register to be read output
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Read1:out std_logic_vector(7 downto 0); --register to be read output
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Read2:out std_logic_vector(7 downto 0) --register to be read on second output
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);
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);
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end component;
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end component;
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--Inputs
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--Inputs
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signal Write : std_logic_vector(7 downto 0) := (others => '0');
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signal Write : std_logic_vector(7 downto 0) := (others => '0');
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signal SelRead: std_logic_vector(2 downto 0) := (others => '0');
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signal SelRead1: std_logic_vector(2 downto 0) := (others => '0');
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signal SelRead2: std_logic_vector(2 downto 0) := (others => '0');
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signal SelWrite: std_logic_vector(2 downto 0) := (others => '0');
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signal SelWrite: std_logic_vector(2 downto 0) := (others => '0');
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signal UseWrite: std_logic := '0';
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signal UseWrite: std_logic := '0';
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--Outputs
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--Outputs
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signal Read : std_logic_vector(7 downto 0);
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signal Read1 : std_logic_vector(7 downto 0);
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signal Read2 : std_logic_vector(7 downto 0);
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signal Clock: std_logic;
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signal Clock: std_logic;
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constant clock_period : time := 10 ns;
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constant clock_period : time := 10 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: registerfile PORT MAP (
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uut: registerfile PORT MAP (
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Write => Write,
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Write => Write,
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SelRead => SelRead,
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SelRead1 => SelRead1,
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SelRead2 => SelRead2,
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SelWrite => SelWrite,
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SelWrite => SelWrite,
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UseWrite => UseWrite,
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UseWrite => UseWrite,
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Clock => Clock,
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Clock => Clock,
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Read => Read
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Read1 => Read1,
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Read2 => Read2
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clock_process :process
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clock_process :process
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begin
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begin
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| Line 67... |
Line 73... |
-- case 1
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-- case 1
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SelWrite <= "000";
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SelWrite <= "000";
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Write <= "11110000";
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Write <= "11110000";
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UseWrite <= '1';
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UseWrite <= '1';
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wait for 10 ns;
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wait for 10 ns;
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SelRead <= "000";
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SelRead1 <= "000";
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UseWrite <= '0';
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UseWrite <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (Read="11110000") report "Storage error case 1" severity error;
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assert (Read1="11110000") report "Storage error case 1" severity error;
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if (Read/="11110000") then
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if (Read1/="11110000") then
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err_cnt:=err_cnt+1;
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err_cnt:=err_cnt+1;
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end if;
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end if;
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-- case 2
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-- case 2
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SelWrite <= "100";
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SelWrite <= "100";
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Write <= "11110001";
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Write <= "11110001";
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UseWrite <= '1';
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UseWrite <= '1';
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wait for 10 ns;
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wait for 10 ns;
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SelRead <= "100";
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SelRead1 <= "100";
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UseWrite <= '0';
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UseWrite <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (Read="11110001") report "Storage selector error case 2" severity error;
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assert (Read1="11110001") report "Storage selector error case 2" severity error;
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if (Read/="11110001") then
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if (Read1/="11110001") then
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err_cnt:=err_cnt+1;
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err_cnt:=err_cnt+1;
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end if;
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end if;
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-- case 3
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-- case 3
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SelRead <= "000";
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SelRead1 <= "000";
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UseWrite <= '0';
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UseWrite <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (Read="11110000") report "Storage selector(remembering) error case 3" severity error;
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assert (Read1="11110000") report "Storage selector(remembering) error case 3" severity error;
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if (Read/="11110000") then
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if (Read1/="11110000") then
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err_cnt:=err_cnt+1;
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err_cnt:=err_cnt+1;
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end if;
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end if;
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-- summary of testbench
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-- summary of testbench
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if (err_cnt=0) then
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if (err_cnt=0) then
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