Line 80... |
Line 80... |
sys_rst_i : in std_logic; -- system reset
|
sys_rst_i : in std_logic; -- system reset
|
-- TX/RX process command line
|
-- TX/RX process command line
|
echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
|
echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
|
tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
|
tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
|
-- serial I/O side
|
-- serial I/O side
|
lantronix_output_i : in std_logic; -- Lantronix Serial data OUTPUT signal
|
uart_din_i : in std_logic; -- Serial data INPUT signal (from the FPGA)
|
lantronix_input_o : out std_logic; -- Lantronix Serial data INPUT signal
|
uart_dout_o : out std_logic; -- Serial data OUTPUT signal (to the FPGA)
|
cp_b : inout std_logic_vector(2 downto 0); -- general purpose IO pins
|
|
-- parallel I/O side
|
-- parallel I/O side
|
s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
|
s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
|
-- RX part/control
|
-- RX part/control
|
v_rx_add_o : out std_logic_vector(15 downto 0); -- 16 bits full addr ram input
|
v_rx_add_o : out std_logic_vector(15 downto 0); -- 16 bits full addr ram input
|
v_rx_data_o : out std_logic_vector(31 downto 0); -- 32 bits full data ram input
|
v_rx_data_o : out std_logic_vector(31 downto 0); -- 32 bits full data ram input
|
Line 108... |
Line 107... |
-- generic signals
|
-- generic signals
|
signal s_rst : std_logic; -- main reset
|
signal s_rst : std_logic; -- main reset
|
signal s_clk_uart : std_logic; -- slow (29 MHz) clock
|
signal s_clk_uart : std_logic; -- slow (29 MHz) clock
|
|
|
-- uart control signals
|
-- uart control signals
|
signal s_uart_cp : std_logic_vector (2 downto 0); -- unused
|
|
signal s_uart_br_clk : std_logic; -- unused clock monitor
|
signal s_uart_br_clk : std_logic; -- unused clock monitor
|
signal s_uart_rx_add : std_logic_vector (15 downto 0);
|
signal s_uart_rx_add : std_logic_vector (15 downto 0);
|
signal s_uart_rx_data : std_logic_vector (31 downto 0);
|
signal s_uart_rx_data : std_logic_vector (31 downto 0);
|
signal s_uart_rx_rdy : std_logic;
|
signal s_uart_rx_rdy : std_logic;
|
signal s_uart_rx_stb_read_data : std_logic;
|
signal s_uart_rx_stb_read_data : std_logic;
|
Line 284... |
Line 282... |
port map(
|
port map(
|
sys_clk_i => s_clk_uart,
|
sys_clk_i => s_clk_uart,
|
sys_rst_i => s_rst,
|
sys_rst_i => s_rst,
|
echo_en_i => r_config_addr_uart(0),
|
echo_en_i => r_config_addr_uart(0),
|
tx_addr_wwo_i => r_config_addr_uart(1),
|
tx_addr_wwo_i => r_config_addr_uart(1),
|
lantronix_output_i => uart_dout_i,
|
uart_dout_i => uart_dout_i,
|
lantronix_input_o => uart_din_o,
|
uart_din_o => uart_din_o,
|
cp_b => s_uart_cp,
|
|
s_br_clk_uart_o => s_uart_br_clk,
|
s_br_clk_uart_o => s_uart_br_clk,
|
v_rx_add_o => s_uart_rx_add,
|
v_rx_add_o => s_uart_rx_add,
|
v_rx_data_o => s_uart_rx_data,
|
v_rx_data_o => s_uart_rx_data,
|
s_rx_rdy_o => s_uart_rx_rdy,
|
s_rx_rdy_o => s_uart_rx_rdy,
|
s_rx_stb_read_data_i => s_uart_rx_stb_read_data,
|
s_rx_stb_read_data_i => s_uart_rx_stb_read_data,
|