Line 4651... |
Line 4651... |
input [dat_width-1:0] wb_dat_i;
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input [dat_width-1:0] wb_dat_i;
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input [adr_width-1:0] wb_adr_i;
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input [adr_width-1:0] wb_adr_i;
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input [dat_width/8-1:0] wb_sel_i;
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input [dat_width/8-1:0] wb_sel_i;
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input wb_we_i, wb_stb_i, wb_cyc_i;
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input wb_we_i, wb_stb_i, wb_cyc_i;
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output [dat_width-1:0] wb_dat_o;
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output [dat_width-1:0] wb_dat_o;
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reg [dat_width-1:0] wb_dat_o;
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output stall_o;
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output stall_o;
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output wb_ack_o;
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output wb_ack_o;
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reg wb_ack_o;
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reg wb_ack_o;
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input wb_clk, wb_rst;
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input wb_clk, wb_rst;
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generate
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generate
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if (dat_width==32) begin
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if (dat_width==32) begin
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reg [7:0] ram3, ram2, ram1, ram0 [1<<(adr_width-2)-1:0];
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reg [7:0] ram3 [1<<(adr_width-2)-1:0];
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reg [7:0] ram2 [1<<(adr_width-2)-1:0];
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reg [7:0] ram1 [1<<(adr_width-2)-1:0];
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reg [7:0] ram0 [1<<(adr_width-2)-1:0];
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always @ (posedge wb_clk)
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always @ (posedge wb_clk)
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begin
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begin
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if (wb_sel_i[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
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if (wb_sel_i[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
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if (wb_sel_i[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
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if (wb_sel_i[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
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if (wb_sel_i[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
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if (wb_sel_i[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
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if (wb_sel_i[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
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if (wb_sel_i[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
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wb_dat_o <= {ram3[adr_width-1:2],ram2[adr_width-1:2],ram1[adr_width-1:2],ram0[adr_width-1:2]};
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wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
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end
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end
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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