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[/] [zet86/] [trunk/] [sim/] [testbench.v] - Diff between revs 21 and 35
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Rev 35 |
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`timescale 10ns/100ps
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`timescale 10ns/100ps
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module testbench;
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module testbench;
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// Net declarations
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// Net declarations
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wire [15:0] rd_data;
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wire [15:0] dat_o;
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wire [15:0] wr_data, mem_data, io_data;
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wire [15:0] mem_dat_i, io_dat_i, dat_i;
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wire [19:0] addr;
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wire [19:1] adr;
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wire we;
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wire we;
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wire m_io;
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wire tga;
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wire byte_m;
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wire [ 1:0] sel;
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wire ack_i;
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wire stb;
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wire stb;
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wire cyc;
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wire ack, mem_ack, io_ack;
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reg clk;
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reg rst;
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reg clk, rst;
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reg [15:0] io_reg;
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reg [15:0] io_reg;
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reg [ 1:0] ack;
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// Module instantiations
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// Module instantiations
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memory mem0 (clk, addr, wr_data, mem_data, stb & we & ~m_io, byte_m);
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memory mem0 (
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.wb_clk_i (clk),
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.wb_rst_i (rst),
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.wb_dat_i (dat_o),
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.wb_dat_o (mem_dat_i),
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.wb_adr_i (adr),
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.wb_we_i (we),
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.wb_sel_i (sel),
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.wb_stb_i (stb & !tga),
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.wb_cyc_i (cyc & !tga),
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.wb_ack_o (mem_ack)
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);
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cpu cpu0 (
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cpu cpu0 (
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.clk_i (clk),
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.wb_clk_i (clk),
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.rst_i (rst),
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.wb_rst_i (rst),
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.dat_i (rd_data),
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.wb_dat_i (dat_i),
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.dat_o (wr_data),
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.wb_dat_o (dat_o),
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.adr_o (addr),
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.wb_adr_o (adr),
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.we_o (we),
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.wb_we_o (we),
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.mio_o (m_io),
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.wb_tga_o (tga),
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.byte_o (byte_m),
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.wb_sel_o (sel),
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.stb_o (stb),
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.wb_stb_o (stb),
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.ack_i (ack_i)
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.wb_cyc_o (cyc),
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.wb_ack_i (ack)
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);
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);
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// Assignments
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// Assignments
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assign io_data = (addr[15:0]==16'hb7) ? io_reg : 16'd0;
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assign io_dat_i = (adr[15:1]==15'h5b) ? { io_reg[7:0], 8'h0 }
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assign rd_data = m_io ? io_data : mem_data;
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: ((adr[15:1]==15'h5c) ? { 8'h0, io_reg[15:8] } : 16'h0);
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assign ack_i = (ack==2'b10);
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assign dat_i = tga ? io_dat_i : mem_dat_i;
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assign ack = tga ? io_ack : mem_ack;
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assign io_ack = stb;
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// Behaviour
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// Behaviour
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// IO Stub
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// IO Stub
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always @(posedge clk)
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always @(posedge clk)
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if (addr==20'hb7 & we & m_io)
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if (adr[15:1]==15'h5b && sel[1] && cyc && stb)
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io_reg <= byte_m ? { io_reg[15:8], wr_data[7:0] } : wr_data;
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io_reg[7:0] <= dat_o[15:8];
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else if (adr[15:1]==15'h5c & sel[0] && cyc && stb)
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io_reg[15:8] <= dat_o[7:0];
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always #1 clk = ~clk;
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always #1 clk = ~clk;
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always #2.13 ack = ack + 2'd1;
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initial
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initial
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begin
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begin
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clk <= 1'b1;
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clk <= 1'b1;
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rst <= 1'b0;
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rst <= 1'b0;
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ack <= 2'b0;
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#5 rst <= 1'b1;
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#5 rst <= 1'b1;
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#2 rst <= 1'b0;
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#2 rst <= 1'b0;
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end
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end
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endmodule
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endmodule
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