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---------------------------------------------------------------------
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-- (c) Copyright 2006, CoreTex Systems, LLC --
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-- (c) Copyright 2006, CoreTex Systems, LLC --
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-- www.coretexsys.com --
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-- www.coretexsys.com --
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-- --
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-- --
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-- This source file may be used and distributed without --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer. --
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-- the original copyright notice and the associated disclaimer. --
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-- --
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-- --
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- Poject structure:
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-- Poject structure:
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-- |- tdes_top.vhd
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-- |- tdes_top.vhd
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-- |
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-- |
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-- |- des_cipher_top.vhd
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-- |- des_cipher_top.vhd
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-- |- des_top.vhd
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-- |- des_top.vhd
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-- |- block_top.vhd
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-- |- block_top.vhd
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-- |- add_key.vhd
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-- |- add_key.vhd
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-- |
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-- |
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-- |- add_left.vhd
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-- |- add_left.vhd
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-- |
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-- |
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-- |- e_expansion_function.vhd
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-- |- e_expansion_function.vhd
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-- |
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-- |
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-- |- p_box.vhd
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-- |- p_box.vhd
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-- |
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-- |
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-- |- s_box.vhd
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-- |- s_box.vhd
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-- |- s1_box.vhd
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-- |- s1_box.vhd
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-- |- s2_box.vhd
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-- |- s2_box.vhd
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-- |- s3_box.vhd
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-- |- s3_box.vhd
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-- |- s4_box.vhd
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-- |- s4_box.vhd
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-- |- s5_box.vhd
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-- |- s5_box.vhd
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-- |- s6_box.vhd
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-- |- s6_box.vhd
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-- |- s7_box.vhd
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-- |- s7_box.vhd
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-- |- s8_box.vhd
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-- |- s8_box.vhd
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-- |- key_schedule.vhd
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-- |- key_schedule.vhd
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Title : add_key
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-- Title : add_key
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-- Company : CoreTex Systems, LLC
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-- Company : CoreTex Systems, LLC
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity add_key is
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entity add_key is
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port(
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port(
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x0_in: in std_logic_vector(0 to 5);
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x0_in: in std_logic_vector(0 to 5);
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x1_in: in std_logic_vector(0 to 5);
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x1_in: in std_logic_vector(0 to 5);
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x2_in: in std_logic_vector(0 to 5);
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x2_in: in std_logic_vector(0 to 5);
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x3_in: in std_logic_vector(0 to 5);
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x3_in: in std_logic_vector(0 to 5);
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x4_in: in std_logic_vector(0 to 5);
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x4_in: in std_logic_vector(0 to 5);
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x5_in: in std_logic_vector(0 to 5);
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x5_in: in std_logic_vector(0 to 5);
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x6_in: in std_logic_vector(0 to 5);
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x6_in: in std_logic_vector(0 to 5);
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x7_in: in std_logic_vector(0 to 5);
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x7_in: in std_logic_vector(0 to 5);
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key: in std_logic_vector(0 to 47);
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key: in std_logic_vector(0 to 47);
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x0_out: out std_logic_vector(5 downto 0);
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x0_out: out std_logic_vector(5 downto 0);
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x1_out: out std_logic_vector(5 downto 0);
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x1_out: out std_logic_vector(5 downto 0);
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x2_out: out std_logic_vector(5 downto 0);
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x2_out: out std_logic_vector(5 downto 0);
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x3_out: out std_logic_vector(5 downto 0);
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x3_out: out std_logic_vector(5 downto 0);
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x4_out: out std_logic_vector(5 downto 0);
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x4_out: out std_logic_vector(5 downto 0);
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x5_out: out std_logic_vector(5 downto 0);
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x5_out: out std_logic_vector(5 downto 0);
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x6_out: out std_logic_vector(5 downto 0);
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x6_out: out std_logic_vector(5 downto 0);
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x7_out: out std_logic_vector(5 downto 0)
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x7_out: out std_logic_vector(5 downto 0)
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);
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);
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end add_key;
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end add_key;
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architecture Behavioral of add_key is
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architecture Behavioral of add_key is
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begin
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begin
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x0_out <= x0_in xor key(0 to 5);
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x0_out <= x0_in xor key(0 to 5);
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x1_out <= x1_in xor key(6 to 11);
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x1_out <= x1_in xor key(6 to 11);
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x2_out <= x2_in xor key(12 to 17);
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x2_out <= x2_in xor key(12 to 17);
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x3_out <= x3_in xor key(18 to 23);
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x3_out <= x3_in xor key(18 to 23);
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x4_out <= x4_in xor key(24 to 29);
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x4_out <= x4_in xor key(24 to 29);
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x5_out <= x5_in xor key(30 to 35);
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x5_out <= x5_in xor key(30 to 35);
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x6_out <= x6_in xor key(36 to 41);
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x6_out <= x6_in xor key(36 to 41);
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x7_out <= x7_in xor key(42 to 47);
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x7_out <= x7_in xor key(42 to 47);
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end Behavioral;
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end Behavioral;
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