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---------------------------------------------------------------------
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-- (c) Copyright 2006, CoreTex Systems, LLC --
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-- (c) Copyright 2006, CoreTex Systems, LLC --
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-- www.coretexsys.com --
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-- www.coretexsys.com --
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-- --
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-- --
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-- This source file may be used and distributed without --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer. --
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-- the original copyright notice and the associated disclaimer. --
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-- --
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-- --
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- Poject structure:
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-- Poject structure:
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-- |- tdes_top.vhd
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-- |- tdes_top.vhd
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-- |
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-- |
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-- |- des_cipher_top.vhd
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-- |- des_cipher_top.vhd
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-- |- des_top.vhd
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-- |- des_top.vhd
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-- |- block_top.vhd
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-- |- block_top.vhd
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-- |- add_key.vhd
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-- |- add_key.vhd
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-- |
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-- |
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-- |- add_left.vhd
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-- |- add_left.vhd
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-- |
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-- |
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-- |- e_expansion_function.vhd
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-- |- e_expansion_function.vhd
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-- |
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-- |
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-- |- p_box.vhd
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-- |- p_box.vhd
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-- |
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-- |
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-- |- s_box.vhd
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-- |- s_box.vhd
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-- |- s1_box.vhd
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-- |- s1_box.vhd
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-- |- s2_box.vhd
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-- |- s2_box.vhd
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-- |- s3_box.vhd
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-- |- s3_box.vhd
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-- |- s4_box.vhd
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-- |- s4_box.vhd
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-- |- s5_box.vhd
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-- |- s5_box.vhd
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-- |- s6_box.vhd
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-- |- s6_box.vhd
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-- |- s7_box.vhd
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-- |- s7_box.vhd
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-- |- s8_box.vhd
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-- |- s8_box.vhd
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-- |- key_schedule.vhd
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-- |- key_schedule.vhd
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- Title : tdes_top
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-- Title : tdes_top
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-- Company : CoreTex Systems, LLC
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-- Company : CoreTex Systems, LLC
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--
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--
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity tdes_top is
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entity tdes_top is
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port(
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port(
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--
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--
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-- inputs for key expander
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-- inputs for key expander
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--
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--
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key1_in: in std_logic_vector(0 to 63);
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key1_in: in std_logic_vector(0 to 63);
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key2_in: in std_logic_vector(0 to 63);
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key2_in: in std_logic_vector(0 to 63);
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key3_in: in std_logic_vector(0 to 63);
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key3_in: in std_logic_vector(0 to 63);
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--
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--
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-- function select
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-- function select
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--
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--
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function_select: in std_logic; -- active when encryption, inactive when decryption
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function_select: in std_logic; -- active when encryption, inactive when decryption
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--
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--
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-- input into des_cipher_top
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-- input into des_cipher_top
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--
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--
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data_in: in std_logic_vector(0 to 63);
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data_in: in std_logic_vector(0 to 63);
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--
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--
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-- input into des_cipher_top
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-- input into des_cipher_top
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--
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--
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data_out: out std_logic_vector(0 to 63);
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data_out: out std_logic_vector(0 to 63);
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--
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--
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-- data interface to MCU
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-- data interface to MCU
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--
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--
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lddata: in std_logic; -- active when data for loading is ready
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lddata: in std_logic; -- active when data for loading is ready
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ldkey: in std_logic; -- active when key for loading is ready
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ldkey: in std_logic; -- active when key for loading is ready
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out_ready: out std_logic; -- active when encryption of data is done
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out_ready: out std_logic; -- active when encryption of data is done
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--
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--
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-- General clock and reset
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-- General clock and reset
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--
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--
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reset: in std_logic;
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reset: in std_logic;
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clock: in std_logic
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clock: in std_logic
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);
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);
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end tdes_top;
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end tdes_top;
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architecture Behavioral of tdes_top is
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architecture Behavioral of tdes_top is
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component des_cipher_top is
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component des_cipher_top is
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port(
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port(
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--
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--
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-- inputs for key expander
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-- inputs for key expander
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--
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--
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key_in: in std_logic_vector(0 to 63); -- interface to MCU
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key_in: in std_logic_vector(0 to 63); -- interface to MCU
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--ldkey: in std_logic; -- active signal for loading keys
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--ldkey: in std_logic; -- active signal for loading keys
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--
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--
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-- function select
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-- function select
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--
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--
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function_select: in std_logic; -- active when encryption, inactive when decryption
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function_select: in std_logic; -- active when encryption, inactive when decryption
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--
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--
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-- input into des_cipher_top
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-- input into des_cipher_top
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--
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--
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data_in: in std_logic_vector(0 to 63);
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data_in: in std_logic_vector(0 to 63);
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--
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--
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-- input into des_cipher_top
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-- input into des_cipher_top
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--
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--
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data_out: out std_logic_vector(0 to 63);
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data_out: out std_logic_vector(0 to 63);
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--
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--
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-- data interface to MCU
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-- data interface to MCU
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--
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--
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lddata: in std_logic; -- active when data for loading is ready
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lddata: in std_logic; -- active when data for loading is ready
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des_out_rdy: out std_logic; -- active when encryption of data is done
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des_out_rdy: out std_logic; -- active when encryption of data is done
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--
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--
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-- General clock and reset
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-- General clock and reset
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--
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--
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reset: in std_logic;
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reset: in std_logic;
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clock: in std_logic
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clock: in std_logic
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);
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);
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end component;
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end component;
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type statetype is (WaitKeyState, WaitDataState);
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type statetype is (WaitKeyState, WaitDataState);
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signal nextstate: statetype;
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signal nextstate: statetype;
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signal key1_in_internal: std_logic_vector(0 to 63);
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signal key1_in_internal: std_logic_vector(0 to 63);
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signal key2_in_internal: std_logic_vector(0 to 63);
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signal key2_in_internal: std_logic_vector(0 to 63);
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signal key3_in_internal: std_logic_vector(0 to 63);
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signal key3_in_internal: std_logic_vector(0 to 63);
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signal memkey1: std_logic_vector(0 to 63);
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signal memkey1: std_logic_vector(0 to 63);
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signal memkey3: std_logic_vector(0 to 63);
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signal memkey3: std_logic_vector(0 to 63);
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signal fsel_internal: std_logic;
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signal fsel_internal: std_logic;
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signal fsel_internal_inv: std_logic;
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signal fsel_internal_inv: std_logic;
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signal des_out_rdy_internal: std_logic;
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signal des_out_rdy_internal: std_logic;
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signal des_out_rdy_internal1: std_logic;
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signal des_out_rdy_internal1: std_logic;
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signal des_out_rdy_internal2: std_logic;
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signal des_out_rdy_internal2: std_logic;
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signal data_in_internal: std_logic_vector(0 to 63);
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signal data_in_internal: std_logic_vector(0 to 63);
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signal data_out_internal: std_logic_vector(0 to 63);
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signal data_out_internal: std_logic_vector(0 to 63);
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signal data_out_internal1: std_logic_vector(0 to 63);
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signal data_out_internal1: std_logic_vector(0 to 63);
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signal data_out_internal2: std_logic_vector(0 to 63);
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signal data_out_internal2: std_logic_vector(0 to 63);
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signal lddata_internal: std_logic;
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signal lddata_internal: std_logic;
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begin
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begin
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process (clock)
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process (clock)
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begin
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begin
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if rising_edge(clock) then
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if rising_edge(clock) then
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if reset = '1' then
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if reset = '1' then
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nextstate <= WaitKeyState;
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nextstate <= WaitKeyState;
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lddata_internal <= '0';
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lddata_internal <= '0';
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out_ready <= '0';
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out_ready <= '0';
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fsel_internal <= function_select;
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fsel_internal <= function_select;
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fsel_internal_inv <= not function_select;
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fsel_internal_inv <= not function_select;
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else
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else
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data_out <= data_out_internal;
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data_out <= data_out_internal;
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out_ready <= des_out_rdy_internal;
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out_ready <= des_out_rdy_internal;
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case nextstate is
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case nextstate is
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--
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--
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-- wait key state
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-- wait key state
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--
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--
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when WaitKeyState =>
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when WaitKeyState =>
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-- wait until key is ready (as well as the function_select)
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-- wait until key is ready (as well as the function_select)
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if ldkey = '0' then
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if ldkey = '0' then
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nextstate <= WaitKeyState;
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nextstate <= WaitKeyState;
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else
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else
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key1_in_internal <= key1_in;
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key1_in_internal <= key1_in;
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key2_in_internal <= key2_in;
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key2_in_internal <= key2_in;
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key3_in_internal <= key3_in;
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key3_in_internal <= key3_in;
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memkey1 <= key1_in;
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memkey1 <= key1_in;
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memkey3 <= key3_in;
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memkey3 <= key3_in;
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nextstate <= WaitDataState;
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nextstate <= WaitDataState;
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end if;
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end if;
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--
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--
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-- wait data state
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-- wait data state
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--
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--
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when WaitDataState =>
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when WaitDataState =>
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-- wait until data is ready to be loaded
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-- wait until data is ready to be loaded
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if lddata = '0' then
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if lddata = '0' then
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nextstate <= WaitDataState;
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nextstate <= WaitDataState;
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lddata_internal <= '0';
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lddata_internal <= '0';
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else
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else
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lddata_internal <= '1';
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lddata_internal <= '1';
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if fsel_internal = '0' then
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if fsel_internal = '0' then
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key1_in_internal <= memkey3;
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key1_in_internal <= memkey3;
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key3_in_internal <= memkey1;
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key3_in_internal <= memkey1;
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end if;
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end if;
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data_in_internal <= data_in;
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data_in_internal <= data_in;
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nextstate <= WaitDataState;
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nextstate <= WaitDataState;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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DESCIPHERTOP1: des_cipher_top
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DESCIPHERTOP1: des_cipher_top
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port map (
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port map (
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key_in => key1_in_internal, -- interface to MCU
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key_in => key1_in_internal, -- interface to MCU
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function_select => fsel_internal, -- active when encryption, inactive when decryption
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function_select => fsel_internal, -- active when encryption, inactive when decryption
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data_in => data_in_internal,
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data_in => data_in_internal,
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data_out => data_out_internal1,
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data_out => data_out_internal1,
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lddata => lddata_internal, -- active when data for loading is ready
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lddata => lddata_internal, -- active when data for loading is ready
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des_out_rdy => des_out_rdy_internal1, -- active when encryption of data is done
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des_out_rdy => des_out_rdy_internal1, -- active when encryption of data is done
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reset => reset,
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reset => reset,
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clock => clock
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clock => clock
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);
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);
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DESCIPHERTOP2: des_cipher_top
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DESCIPHERTOP2: des_cipher_top
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port map (
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port map (
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key_in => key2_in_internal, --subkey_in_internal, -- interface to MCU
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key_in => key2_in_internal, --subkey_in_internal, -- interface to MCU
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function_select => fsel_internal_inv, -- active when encryption, inactive when decryption
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function_select => fsel_internal_inv, -- active when encryption, inactive when decryption
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data_in => data_out_internal1,
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data_in => data_out_internal1,
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data_out => data_out_internal2,
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data_out => data_out_internal2,
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lddata => des_out_rdy_internal1, -- active when data for loading is ready
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lddata => des_out_rdy_internal1, -- active when data for loading is ready
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des_out_rdy => des_out_rdy_internal2, -- active when encryption of data is done
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des_out_rdy => des_out_rdy_internal2, -- active when encryption of data is done
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reset => reset,
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reset => reset,
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clock => clock
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clock => clock
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);
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);
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DESCIPHERTOP3: des_cipher_top
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DESCIPHERTOP3: des_cipher_top
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port map (
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port map (
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key_in => key3_in_internal, -- subkey_in_internal, -- interface to MCU
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key_in => key3_in_internal, -- subkey_in_internal, -- interface to MCU
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function_select => fsel_internal, -- active when encryption, inactive when decryption
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function_select => fsel_internal, -- active when encryption, inactive when decryption
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data_in => data_out_internal2,
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data_in => data_out_internal2,
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data_out => data_out_internal,
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data_out => data_out_internal,
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lddata => des_out_rdy_internal2, -- active when data for loading is ready
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lddata => des_out_rdy_internal2, -- active when data for loading is ready
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des_out_rdy => des_out_rdy_internal, -- active when encryption of data is done
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des_out_rdy => des_out_rdy_internal, -- active when encryption of data is done
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reset => reset,
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reset => reset,
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clock => clock
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clock => clock
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);
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);
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end Behavioral;
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end Behavioral;
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