/*
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/*
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*
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*
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* MC6809/HD6309 Compatible code
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* MC6809/HD6309 Compatible code
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* (c) 2013 R.A. Paz Schmidt
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* (c) 2013 R.A. Paz Schmidt
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* distributed under the terms of the Lesser GPL, see LICENSE.TXT
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* distributed under the terms of the Lesser GPL, see LICENSE.TXT
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*
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*
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*/
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*/
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`include "defs.v"
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`include "defs.v"
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module MC6809_cpu(
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module MC6809_cpu(
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input wire cpu_clk,
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input wire cpu_clk,
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input wire cpu_reset,
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input wire cpu_reset,
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input wire cpu_nmi_n,
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input wire cpu_nmi_n,
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input wire cpu_irq_n,
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input wire cpu_irq_n,
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input wire cpu_firq_n,
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input wire cpu_firq_n,
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output wire [5:0] cpu_state_o,
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output wire [5:0] cpu_state_o,
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output wire cpu_we_o,
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output wire cpu_we_o,
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output wire cpu_oe_o,
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output wire cpu_oe_o,
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output wire [15:0] cpu_addr_o,
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output wire [15:0] cpu_addr_o,
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input wire [7:0] cpu_data_i,
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input wire [7:0] cpu_data_i,
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output wire [7:0] cpu_data_o,
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output wire [7:0] cpu_data_o,
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input wire debug_clk,
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input wire debug_clk,
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output wire debug_data_o // serial debug info, 64 bit shift register
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output wire debug_data_o // serial debug info, 64 bit shift register
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);
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);
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wire k_reset;
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wire k_reset;
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reg [7:0] k_opcode, k_postbyte, k_ind_ea; /* all bytes of an instruction */
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reg [7:0] k_opcode, k_postbyte, k_ind_ea; /* all bytes of an instruction */
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reg [7:0] k_pp_regs; // push/pull registers to process
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reg [7:0] k_pp_regs; // push/pull registers to process
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reg [3:0] k_pp_active_reg; // push/pull active register
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reg [3:0] k_pp_active_reg; // push/pull active register
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reg [7:0] k_memhi, k_memlo, k_cpu_data_o; /* operand read from memory */
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reg [7:0] k_memhi, k_memlo, k_cpu_data_o; /* operand read from memory */
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reg [7:0] k_ofslo, k_ofshi, k_eahi, k_ealo;
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reg [7:0] k_ofslo, k_ofshi, k_eahi, k_ealo;
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reg [5:0] state, // state of the main state machine
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reg [5:0] state, // state of the main state machine
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next_state, // next state to exit to from the read from [PC] state machine
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next_state, // next state to exit to from the read from [PC] state machine
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next_mem_state, // next state to exit to from the read from memory state machine
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next_mem_state, // next state to exit to from the read from memory state machine
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next_push_state; // next state to exit to from push multiple state machine
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next_push_state; // next state to exit to from push multiple state machine
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reg k_write_tfr, k_write_exg;
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reg k_write_tfr, k_write_exg;
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reg k_cpu_oe, k_cpu_we, k_inc_pc;
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reg k_cpu_oe, k_cpu_we, k_inc_pc;
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reg k_indirect_loaded; // set when in indirect indexed and the address has been loaded
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reg k_indirect_loaded; // set when in indirect indexed and the address has been loaded
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reg [15:0] k_cpu_addr, k_new_pc;
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reg [15:0] k_cpu_addr, k_new_pc;
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reg k_write_pc, k_inc_su, k_dec_su, k_set_e, k_clear_e;
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reg k_write_pc, k_inc_su, k_dec_su, k_set_e, k_clear_e;
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reg [1:0] k_mem_dest;
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reg [1:0] k_mem_dest;
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reg k_mul_cnt; // multiplier couner
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reg k_mul_cnt; // multiplier couner
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reg k_write_dest; // set for 1 clock when a register has to be written, dec_o_dest_reg_addr has the register source
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reg k_write_dest; // set for 1 clock when a register has to be written, dec_o_dest_reg_addr has the register source
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reg k_write_post_incdec; // asserted when in the last write cycle or in write back for loads
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reg k_write_post_incdec; // asserted when in the last write cycle or in write back for loads
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reg k_forced_mem_size; // used to force the size of a memory read to be 16 bits, used for vector fetch
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reg k_forced_mem_size; // used to force the size of a memory read to be 16 bits, used for vector fetch
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/****
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/****
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* Decoder outputs
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* Decoder outputs
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*/
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*/
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wire [2:0] dec_o_p1_mode; // addressing mode
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wire [2:0] dec_o_p1_mode; // addressing mode
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wire [2:0] dec_o_p1_optype; // k_opcode type
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wire dec_o_use_s; // signals when S should be used instead of U
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wire dec_o_use_s; // signals when S should be used instead of U
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wire dec_o_alu_size; /* size of the result of an alu opcode (destination to be written) */
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wire dec_o_alu_size; /* size of the result of an alu opcode (destination to be written) */
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wire op_SYNC, op_EXG, op_TFR, op_RTS, op_RTI, op_CWAI;
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wire op_MUL, op_SWI, op_PUSH, op_PULL, op_LEA, op_JMP, op_JSR;
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/* ea decoder */
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/* ea decoder */
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wire dec_o_ea_ofs8, dec_o_ea_ofs16, dec_o_ea_wpost, dec_o_ea_ofs0, dec_o_ea_indirect;
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wire dec_o_ea_ofs8, dec_o_ea_ofs16, dec_o_ea_wpost, dec_o_ea_ofs0, dec_o_ea_indirect;
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/* alu k_opcode decoder */
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/* alu k_opcode decoder */
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wire [4:0] dec_o_alu_opcode;
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wire [4:0] dec_o_alu_opcode;
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wire [1:0] dec_o_right_path_mod; /* Modifier for alu's right path input */
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wire [1:0] dec_o_right_path_mod; /* Modifier for alu's right path input */
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/* register decoder */
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/* register decoder */
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wire dec_o_wdest, dec_o_source_size, dec_o_write_flags;
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wire dec_o_wdest, dec_o_source_size, dec_o_write_flags;
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wire [3:0] dec_o_left_path_addr, dec_o_right_path_addr, dec_o_dest_reg_addr;
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wire [3:0] dec_o_left_path_addr, dec_o_right_path_addr, dec_o_dest_reg_addr;
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// latched versions, used for muxes, regs and alu
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// latched versions, used for muxes, regs and alu
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wire [3:0] dec_lo_left_path_addr, dec_lo_right_path_addr, dec_lo_dest_reg_addr;
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wire [3:0] dec_lo_left_path_addr, dec_lo_right_path_addr, dec_lo_dest_reg_addr;
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/* test condition */
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/* test condition */
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wire dec_o_cond_taken;
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wire dec_o_cond_taken;
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/* ALU outputs */
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/* ALU outputs */
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wire [15:0] alu_o_result;
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wire [15:0] alu_o_result;
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wire [7:0] alu_o_CCR;
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wire [7:0] alu_o_CCR;
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wire [7:0] alu8_o_result;
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wire [7:0] alu8_o_CCR;
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/* Register Module outputs */
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/* Register Module outputs */
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wire [15:0] regs_o_left_path_data, regs_o_right_path_data, regs_o_eamem_addr, regs_o_su;
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wire [15:0] regs_o_left_path_data, regs_o_right_path_data, regs_o_eamem_addr, regs_o_su;
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wire [7:0] regs_o_dp;
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wire [7:0] regs_o_dp;
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wire [15:0] regs_o_pc;
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wire [15:0] regs_o_pc;
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wire [7:0] regs_o_CCR;
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wire [7:0] regs_o_CCR;
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/* Data Muxes */
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/* Data Muxes */
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reg [3:0] datamux_o_dest_reg_addr, datamux_o_alu_in_left_path_addr;
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reg [3:0] datamux_o_dest_reg_addr, datamux_o_alu_in_left_path_addr;
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reg [15:0] datamux_o_alu_in_left_path_data, datamux_o_alu_in_right_path_data, datamux_o_dest;
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reg [15:0] datamux_o_alu_in_left_path_data, datamux_o_alu_in_right_path_data, datamux_o_dest;
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reg k_p2_valid, k_p3_valid; /* 1 when k_postbyte has been loaded for page 2 or page 3 */
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reg k_p2_valid, k_p3_valid; /* 1 when k_postbyte has been loaded for page 2 or page 3 */
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/*
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/*
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* Interrupt sync registers
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* Interrupt sync registers
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*/
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*/
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reg [2:0] k_reg_nmi, k_reg_irq, k_reg_firq;
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reg [2:0] k_reg_nmi, k_reg_irq, k_reg_firq;
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wire k_nmi_req, k_firq_req, k_irq_req;
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wire k_nmi_req, k_firq_req, k_irq_req;
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assign k_nmi_req = k_reg_nmi[2] & k_reg_nmi[1];
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assign k_nmi_req = k_reg_nmi[2] & k_reg_nmi[1];
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assign k_firq_req = k_reg_firq[2] & k_reg_firq[1];
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assign k_firq_req = k_reg_firq[2] & k_reg_firq[1];
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assign k_irq_req = k_reg_irq[2] & k_reg_irq[1];
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assign k_irq_req = k_reg_irq[2] & k_reg_irq[1];
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/* Debug */
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/* Debug */
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`ifdef SERIAL_DEBUG
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`ifdef SERIAL_DEBUG
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reg [63:0] debug_r;
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reg [63:0] debug_r;
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always @(posedge debug_clk)
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always @(posedge debug_clk)
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begin
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begin
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if (cpu_clk)
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if (cpu_clk)
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begin
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begin
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debug_r[15:0] <= regs_o_pc;
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debug_r[15:0] <= regs_o_pc;
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debug_r[23:16] <= k_opcode;
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debug_r[23:16] <= k_opcode;
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debug_r[27:24] <= datamux_o_alu_in_left_path_addr;
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debug_r[27:24] <= datamux_o_alu_in_left_path_addr;
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debug_r[31:28] <= dec_o_right_path_addr;
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debug_r[31:28] <= dec_o_right_path_addr;
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debug_r[35:32] <= datamux_o_dest_reg_addr;
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debug_r[35:32] <= datamux_o_dest_reg_addr;
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debug_r[39:36] <= { k_write_pc, 1'b0, k_mem_dest}; //regs_o_CCR[3:0];
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debug_r[39:36] <= { k_write_pc, 1'b0, k_mem_dest}; //regs_o_CCR[3:0];
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debug_r[55:40] <= { k_memhi,k_memlo };//k_new_pc;
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debug_r[55:40] <= { k_memhi,k_memlo };//k_new_pc;
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debug_r[63:56] <= cpu_data_i;
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debug_r[63:56] <= cpu_data_i;
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end
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end
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else
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else
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debug_r <= debug_r << 1; // shift out
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debug_r <= debug_r << 1; // shift out
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end
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end
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assign debug_data_o = debug_r[63];
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assign debug_data_o = debug_r[63];
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`else
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`else
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assign debug_data_o = 1'b0;
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assign debug_data_o = 1'b0;
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`endif
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`endif
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alu alu(
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alu alu(
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.clk_in(cpu_clk),
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.clk_in(cpu_clk),
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.a_in(datamux_o_alu_in_left_path_data),
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.a_in(datamux_o_alu_in_left_path_data),
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.b_in(datamux_o_alu_in_right_path_data),
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.b_in(datamux_o_alu_in_right_path_data),
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.CCR(regs_o_CCR), /* flags */
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.CCR(regs_o_CCR), /* flags */
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.opcode_in(dec_o_alu_opcode), /* ALU k_opcode */
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.opcode_in(dec_o_alu_opcode), /* ALU k_opcode */
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.sz_in(dec_o_alu_size),
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.sz_in(dec_o_alu_size),
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.q_out(alu_o_result), /* ALU result */
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.q_out(alu_o_result), /* ALU result */
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.CCRo(alu_o_CCR)
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.CCRo(alu_o_CCR)
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);
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);
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regblock regs(
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regblock regs(
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.clk_in(cpu_clk),
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.clk_in(cpu_clk),
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.path_left_addr(datamux_o_alu_in_left_path_addr),
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.path_left_addr(datamux_o_alu_in_left_path_addr),
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.path_right_addr(dec_lo_right_path_addr),
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.path_right_addr(dec_lo_right_path_addr),
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.write_reg_addr(datamux_o_dest_reg_addr),
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.write_reg_addr(datamux_o_dest_reg_addr),
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.exg_dest_r(k_postbyte[7:4]),
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.exg_dest_r(k_postbyte[7:4]),
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.eapostbyte( k_ind_ea ),
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.eapostbyte( k_ind_ea ),
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.offset16({ k_ofshi, k_ofslo }),
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.offset16({ k_ofshi, k_ofslo }),
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.write_reg(k_write_dest),
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.write_reg(k_write_dest),
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.write_tfr(k_write_tfr),
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.write_tfr(k_write_tfr),
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.write_exg(k_write_exg),
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.write_exg(k_write_exg),
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.write_post(k_write_post_incdec),
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.write_post(k_write_post_incdec),
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.write_pc(k_write_pc),
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.write_pc(k_write_pc),
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.inc_pc(k_inc_pc),
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.inc_pc(k_inc_pc),
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.inc_su(k_inc_su),
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.inc_su(k_inc_su),
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.dec_su(k_dec_su),
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.dec_su(k_dec_su),
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.use_s(dec_o_use_s),
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.use_s(dec_o_use_s),
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.data_w(datamux_o_dest),
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.data_w(datamux_o_dest),
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.new_pc(k_new_pc),
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.new_pc(k_new_pc),
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.CCR_in(alu_o_CCR),
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.CCR_in(alu_o_CCR),
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.write_flags(dec_o_write_flags & (state == `SEQ_GRAL_WBACK)),
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.write_flags(dec_o_write_flags & (state == `SEQ_GRAL_WBACK)),
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.set_e(k_set_e),
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.set_e(k_set_e),
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.clear_e(k_clear_e),
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.clear_e(k_clear_e),
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.CCR_o(regs_o_CCR),
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.CCR_o(regs_o_CCR),
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.path_left_data(regs_o_left_path_data),
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.path_left_data(regs_o_left_path_data),
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.path_right_data(regs_o_right_path_data),
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.path_right_data(regs_o_right_path_data),
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.eamem_addr_o(regs_o_eamem_addr),
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.eamem_addr_o(regs_o_eamem_addr),
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.reg_pc(regs_o_pc),
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.reg_pc(regs_o_pc),
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.reg_dp(regs_o_dp),
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.reg_dp(regs_o_dp),
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.reg_su(regs_o_su)
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.reg_su(regs_o_su)
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);
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);
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decode_regs dec_regs(
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decode_regs dec_regs(
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.cpu_clk(cpu_clk),
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.cpu_clk(cpu_clk),
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.opcode(k_opcode),
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.opcode(k_opcode),
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.postbyte0(k_postbyte),
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.postbyte0(k_postbyte),
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.page2_valid(k_p2_valid),
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.page2_valid(k_p2_valid),
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.page3_valid(k_p3_valid),
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.page3_valid(k_p3_valid),
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.path_left_addr_o(dec_o_left_path_addr),
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.path_left_addr_o(dec_o_left_path_addr),
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.path_right_addr_o(dec_o_right_path_addr),
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.path_right_addr_o(dec_o_right_path_addr),
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.dest_reg_o(dec_o_dest_reg_addr),
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.dest_reg_o(dec_o_dest_reg_addr),
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.path_left_addr_lo(dec_lo_left_path_addr),
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.path_left_addr_lo(dec_lo_left_path_addr),
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.path_right_addr_lo(dec_lo_right_path_addr),
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.path_right_addr_lo(dec_lo_right_path_addr),
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.dest_reg_lo(dec_lo_dest_reg_addr),
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.dest_reg_lo(dec_lo_dest_reg_addr),
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.write_dest(dec_o_wdest),
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.write_dest(dec_o_wdest),
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.source_size(dec_o_source_size),
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.source_size(dec_o_source_size),
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.result_size(dec_o_alu_size)
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.result_size(dec_o_alu_size)
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);
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);
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decode_op dec_op(
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decode_op dec_op(
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.opcode(k_opcode),
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.opcode(k_opcode),
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.postbyte0(k_postbyte),
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.postbyte0(k_postbyte),
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.page2_valid(k_p2_valid),
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.page2_valid(k_p2_valid),
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.page3_valid(k_p3_valid),
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.page3_valid(k_p3_valid),
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.mode(dec_o_p1_mode),
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.mode(dec_o_p1_mode),
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.optype(dec_o_p1_optype),
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.op_SYNC(op_SYNC),
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.op_EXG (op_EXG ),
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.op_TFR (op_TFR ),
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.op_RTS (op_RTS ),
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.op_RTI (op_RTI ),
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.op_CWAI(op_CWAI),
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.op_MUL (op_MUL ),
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.op_SWI (op_SWI ),
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.op_PUSH(op_PUSH),
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.op_PULL(op_PULL),
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.op_LEA (op_LEA ),
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.op_JSR (op_JSR ),
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.op_JMP (op_JMP ),
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.use_s(dec_o_use_s)
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.use_s(dec_o_use_s)
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);
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);
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decode_ea dec_ea(
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decode_ea dec_ea(
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.eapostbyte( k_ind_ea ),
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.eapostbyte( k_ind_ea ),
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.noofs(dec_o_ea_ofs0),
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.noofs(dec_o_ea_ofs0),
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.ofs8(dec_o_ea_ofs8),
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.ofs8(dec_o_ea_ofs8),
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.ofs16(dec_o_ea_ofs16),
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.ofs16(dec_o_ea_ofs16),
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.write_post(dec_o_ea_wpost),
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.write_post(dec_o_ea_wpost),
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.isind(dec_o_ea_indirect)
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.isind(dec_o_ea_indirect)
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);
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);
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/* Opcodes for the ALU are decoded here
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/* Opcodes for the ALU are decoded here
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* Write Flags are also decoded here
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* Write Flags are also decoded here
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*/
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*/
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decode_alu dec_alu(
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decode_alu dec_alu(
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.opcode(k_opcode),
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.opcode(k_opcode),
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.postbyte0(k_postbyte),
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.postbyte0(k_postbyte),
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.page2_valid(k_p2_valid),
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.page2_valid(k_p2_valid),
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.page3_valid(k_p3_valid),
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.page3_valid(k_p3_valid),
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.alu_opcode(dec_o_alu_opcode),
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.alu_opcode(dec_o_alu_opcode),
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.dec_alu_right_path_mod(dec_o_right_path_mod),
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.dec_alu_right_path_mod(dec_o_right_path_mod),
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.dest_flags(dec_o_write_flags)
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.dest_flags(dec_o_write_flags)
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);
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);
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/* Condition decoder */
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/* Condition decoder */
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test_condition test_cond(
|
test_condition test_cond(
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.opcode(k_opcode),
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.opcode(k_opcode),
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.postbyte0(k_postbyte),
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.postbyte0(k_postbyte),
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.page2_valid(k_p2_valid),
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.page2_valid(k_p2_valid),
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.CCR(regs_o_CCR),
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.CCR(regs_o_CCR),
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.cond_taken(dec_o_cond_taken)
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.cond_taken(dec_o_cond_taken)
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);
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);
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/* Module IO */
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/* Module IO */
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assign cpu_oe_o = k_cpu_oe; // we latch on the rising edge
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assign cpu_oe_o = k_cpu_oe; // we latch on the rising edge
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assign cpu_we_o = k_cpu_we;
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assign cpu_we_o = k_cpu_we;
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assign cpu_addr_o = k_cpu_addr;
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assign cpu_addr_o = k_cpu_addr;
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assign cpu_data_o = k_cpu_data_o;
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assign cpu_data_o = k_cpu_data_o;
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assign k_reset = cpu_reset;
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assign k_reset = cpu_reset;
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assign cpu_state_o = state;
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assign cpu_state_o = state;
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|
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/* Left Register read mux
|
/* Left Register read mux
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*/
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*/
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always @(*)
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always @(*)
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begin
|
begin
|
if (k_pp_active_reg != `RN_INV)
|
if (k_pp_active_reg != `RN_INV)
|
datamux_o_alu_in_left_path_addr = k_pp_active_reg;
|
datamux_o_alu_in_left_path_addr = k_pp_active_reg;
|
else
|
else
|
datamux_o_alu_in_left_path_addr = dec_lo_left_path_addr;
|
datamux_o_alu_in_left_path_addr = dec_lo_left_path_addr;
|
end
|
end
|
|
|
/* Destination register address MUX
|
/* Destination register address MUX
|
*/
|
*/
|
always @(*)
|
always @(*)
|
begin
|
begin
|
if (k_pp_active_reg != `RN_INV)
|
if (k_pp_active_reg != `RN_INV)
|
datamux_o_dest_reg_addr = k_pp_active_reg;
|
datamux_o_dest_reg_addr = k_pp_active_reg;
|
else
|
else
|
datamux_o_dest_reg_addr = dec_lo_dest_reg_addr;
|
datamux_o_dest_reg_addr = dec_lo_dest_reg_addr;
|
end
|
end
|
|
|
/* Destination register data mux
|
/* Destination register data mux
|
* selects the source to write to register. 16 bit registers have to be written at once after reading the low byte
|
* selects the source to write to register. 16 bit registers have to be written at once after reading the low byte
|
*
|
*
|
*/
|
*/
|
always @(*)
|
always @(*)
|
begin
|
begin
|
datamux_o_dest = alu_o_result;
|
if (op_PULL | op_RTS | op_RTI) // destination register
|
case (dec_o_p1_optype)
|
|
`OP_PULL, `OP_RTS: // destination register
|
|
datamux_o_dest = { k_memhi, k_memlo };
|
datamux_o_dest = { k_memhi, k_memlo };
|
`OP_LEA:
|
else
|
|
if (op_LEA)
|
|
begin
|
if (dec_o_ea_indirect)// & dec_o_alu_size)
|
if (dec_o_ea_indirect)// & dec_o_alu_size)
|
datamux_o_dest = { k_memhi, k_memlo };
|
datamux_o_dest = { k_memhi, k_memlo };
|
else
|
else
|
datamux_o_dest = regs_o_eamem_addr;
|
datamux_o_dest = regs_o_eamem_addr;
|
endcase
|
end
|
|
else
|
|
datamux_o_dest = alu_o_result;
|
end
|
end
|
|
|
/* ALU left input mux */
|
/* ALU left input mux */
|
|
|
always @(*)
|
always @(*)
|
begin
|
begin
|
if (dec_lo_left_path_addr == `RN_MEM8)
|
if (dec_lo_left_path_addr == `RN_MEM8)
|
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
|
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
|
else
|
else
|
case (dec_o_p1_optype)
|
if (op_LEA)
|
`OP_LEA:
|
begin
|
if (dec_o_ea_indirect)// & dec_o_alu_size)
|
if (dec_o_ea_indirect)// & dec_o_alu_size)
|
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
|
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
|
else
|
else
|
datamux_o_alu_in_left_path_data = regs_o_eamem_addr;
|
datamux_o_alu_in_left_path_data = regs_o_eamem_addr;
|
default:
|
end
|
|
else
|
datamux_o_alu_in_left_path_data = regs_o_left_path_data;
|
datamux_o_alu_in_left_path_data = regs_o_left_path_data;
|
endcase
|
|
end
|
end
|
/* PC as destination from jmp/bsr mux */
|
/* PC as destination from jmp/bsr mux */
|
always @(*)
|
always @(*)
|
begin
|
begin
|
k_new_pc = { k_memhi,k_memlo }; // used to fetch reset vector
|
k_new_pc = { k_memhi,k_memlo }; // used to fetch reset vector
|
if (k_mem_dest != `MEMDEST_PC)
|
if (k_mem_dest != `MEMDEST_PC)
|
begin
|
begin
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`REL16: k_new_pc = regs_o_pc + { k_memhi,k_memlo };
|
`REL16: k_new_pc = regs_o_pc + { k_memhi,k_memlo };
|
`REL8: k_new_pc = regs_o_pc + { {8{k_memlo[7]}}, k_memlo };
|
`REL8: k_new_pc = regs_o_pc + { {8{k_memlo[7]}}, k_memlo };
|
`EXTENDED: k_new_pc = { k_eahi,k_ealo };
|
`EXTENDED: k_new_pc = { k_eahi,k_ealo };
|
`DIRECT: k_new_pc = { regs_o_dp, k_ealo };
|
`DIRECT: k_new_pc = { regs_o_dp, k_ealo };
|
`INDEXED:
|
`INDEXED:
|
if (dec_o_ea_indirect)
|
if (dec_o_ea_indirect)
|
k_new_pc = { k_memhi,k_memlo };
|
k_new_pc = { k_memhi,k_memlo };
|
else
|
else
|
k_new_pc = regs_o_eamem_addr;
|
k_new_pc = regs_o_eamem_addr;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
/* ALU right input mux */
|
/* ALU right input mux */
|
always @(*)
|
always @(*)
|
begin
|
begin
|
case (dec_lo_right_path_addr)
|
case (dec_lo_right_path_addr)
|
`RN_MEM8:
|
`RN_MEM8:
|
datamux_o_alu_in_right_path_data = { 8'h00, k_memlo };
|
datamux_o_alu_in_right_path_data = { 8'h00, k_memlo };
|
`RN_MEM16:
|
`RN_MEM16:
|
datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
|
datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
|
`RN_IMM8:
|
`RN_IMM8:
|
datamux_o_alu_in_right_path_data = { 8'h0, k_memlo };
|
datamux_o_alu_in_right_path_data = { 8'h0, k_memlo };
|
`RN_IMM16:
|
`RN_IMM16:
|
datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
|
datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
|
default:
|
default:
|
case (dec_o_right_path_mod)
|
case (dec_o_right_path_mod)
|
`MOD_DEFAULT: datamux_o_alu_in_right_path_data = regs_o_right_path_data;
|
`MOD_DEFAULT: datamux_o_alu_in_right_path_data = regs_o_right_path_data;
|
`MOD_ONE: datamux_o_alu_in_right_path_data = 16'h0001;
|
`MOD_ONE: datamux_o_alu_in_right_path_data = 16'h0001;
|
`MOD_ZERO: datamux_o_alu_in_right_path_data = 16'h0000;
|
`MOD_ZERO: datamux_o_alu_in_right_path_data = 16'h0000;
|
`MOD_MINUS1: datamux_o_alu_in_right_path_data = 16'hffff;
|
`MOD_MINUS1: datamux_o_alu_in_right_path_data = 16'hffff;
|
endcase
|
endcase
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge cpu_clk or posedge k_reset)
|
always @(posedge cpu_clk or posedge k_reset)
|
begin
|
begin
|
if (k_reset == 1'b1)
|
if (k_reset == 1'b1)
|
begin
|
begin
|
state <= `SEQ_COLDRESET;
|
state <= `SEQ_COLDRESET;
|
k_reg_nmi <= 0;
|
k_reg_nmi <= 0;
|
k_reg_firq <= 0;
|
k_reg_firq <= 0;
|
k_reg_irq <= 0;
|
k_reg_irq <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
/* Inrerrupt recognition and acknowledge */
|
/* Interrupt recognition and acknowledge */
|
if (!k_reg_nmi[2])
|
if (!k_reg_nmi[2])
|
k_reg_nmi <= { k_reg_nmi[1:0], cpu_nmi_n };
|
k_reg_nmi <= { k_reg_nmi[1:0], cpu_nmi_n };
|
if (!k_reg_irq[2])
|
if (!k_reg_irq[2])
|
k_reg_irq <= { k_reg_irq[1:0], cpu_irq_n };
|
k_reg_irq <= { k_reg_irq[1:0], cpu_irq_n };
|
if (!k_reg_firq[2])
|
if (!k_reg_firq[2])
|
k_reg_firq <= { k_reg_firq[1:0], cpu_firq_n };
|
k_reg_firq <= { k_reg_firq[1:0], cpu_firq_n };
|
/* modifier registers */
|
/* modifier registers */
|
if (k_inc_pc)
|
if (k_inc_pc)
|
k_inc_pc <= 0;
|
k_inc_pc <= 0;
|
if (k_write_pc)
|
if (k_write_pc)
|
k_write_pc <= 0;
|
k_write_pc <= 0;
|
if (k_cpu_we)
|
if (k_cpu_we)
|
k_cpu_we <= 0;
|
k_cpu_we <= 0;
|
if (k_cpu_oe)
|
if (k_cpu_oe)
|
k_cpu_oe <= 0;
|
k_cpu_oe <= 0;
|
if (k_write_post_incdec)
|
if (k_write_post_incdec)
|
k_write_post_incdec <= 0;
|
k_write_post_incdec <= 0;
|
if (k_dec_su)
|
if (k_dec_su)
|
k_dec_su <= 0;
|
k_dec_su <= 0;
|
if (k_inc_su)
|
if (k_inc_su)
|
k_inc_su <= 0;
|
k_inc_su <= 0;
|
if (k_set_e)
|
if (k_set_e)
|
k_set_e <= 0;
|
k_set_e <= 0;
|
if (k_clear_e)
|
if (k_clear_e)
|
k_clear_e <= 0;
|
k_clear_e <= 0;
|
if (k_write_dest)
|
if (k_write_dest)
|
k_write_dest <= 0;
|
k_write_dest <= 0;
|
if (k_write_exg)
|
if (k_write_exg)
|
k_write_exg <= 0;
|
k_write_exg <= 0;
|
if (k_write_tfr)
|
if (k_write_tfr)
|
k_write_tfr <= 0;
|
k_write_tfr <= 0;
|
case (state)
|
case (state)
|
`SEQ_COLDRESET:
|
`SEQ_COLDRESET:
|
begin
|
begin
|
k_forced_mem_size <= 1;
|
k_forced_mem_size <= 1;
|
state <= `SEQ_MEM_READ_H;
|
state <= `SEQ_MEM_READ_H;
|
k_eahi <= 8'hff;
|
k_eahi <= 8'hff;
|
k_ealo <= 8'hfe;
|
k_ealo <= 8'hfe;
|
next_mem_state <= `SEQ_LOADPC;
|
next_mem_state <= `SEQ_LOADPC;
|
k_mem_dest <= `MEMDEST_PC;
|
k_mem_dest <= `MEMDEST_PC;
|
end
|
end
|
`SEQ_NMI:
|
`SEQ_NMI:
|
begin
|
begin
|
k_forced_mem_size <= 1;
|
k_forced_mem_size <= 1;
|
k_reg_nmi <= 3'h0;
|
k_reg_nmi <= 3'h0;
|
{ k_eahi, k_ealo } <= 16'hfffc;
|
{ k_eahi, k_ealo } <= 16'hfffc;
|
k_pp_regs <= 8'hff;
|
k_pp_regs <= 8'hff;
|
k_set_e <= 1;
|
k_set_e <= 1;
|
state <= `SEQ_PREPUSH; // first stack the registers
|
state <= `SEQ_PREPUSH; // first stack the registers
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
end
|
end
|
`SEQ_SWI:
|
`SEQ_SWI:
|
begin
|
begin
|
k_forced_mem_size <= 1;
|
k_forced_mem_size <= 1;
|
state <= `SEQ_MEM_READ_H;
|
state <= `SEQ_MEM_READ_H;
|
{ k_eahi, k_ealo } <= 16'hfffa;
|
{ k_eahi, k_ealo } <= 16'hfffa;
|
k_pp_regs <= 8'hff;
|
k_pp_regs <= 8'hff;
|
state <= `SEQ_PREPUSH; // first stack the registers
|
state <= `SEQ_PREPUSH; // first stack the registers
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
k_set_e <= 1;
|
k_set_e <= 1;
|
end
|
end
|
`SEQ_IRQ:
|
`SEQ_IRQ:
|
begin
|
begin
|
k_forced_mem_size <= 1;
|
k_forced_mem_size <= 1;
|
k_reg_irq <= 3'h0;
|
k_reg_irq <= 3'h0;
|
state <= `SEQ_MEM_READ_H;
|
state <= `SEQ_MEM_READ_H;
|
{ k_eahi, k_ealo } <= 16'hfff8;
|
{ k_eahi, k_ealo } <= 16'hfff8;
|
k_pp_regs <= 8'hff;
|
k_pp_regs <= 8'hff;
|
next_mem_state <= `SEQ_PREPUSH;
|
next_mem_state <= `SEQ_PREPUSH;
|
k_set_e <= 1;
|
k_set_e <= 1;
|
state <= `SEQ_PREPUSH; // first stack the registers
|
state <= `SEQ_PREPUSH; // first stack the registers
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
end
|
end
|
`SEQ_FIRQ:
|
`SEQ_FIRQ:
|
begin
|
begin
|
k_forced_mem_size <= 1;
|
k_forced_mem_size <= 1;
|
k_reg_firq <= 3'h0;
|
k_reg_firq <= 3'h0;
|
{ k_eahi, k_ealo } <= 16'hfff6;
|
{ k_eahi, k_ealo } <= 16'hfff6;
|
k_pp_regs <= 8'h81; // PC & CC
|
k_pp_regs <= 8'h81; // PC & CC
|
k_clear_e <= 1;
|
k_clear_e <= 1;
|
state <= `SEQ_PREPUSH; // first stack the registers
|
state <= `SEQ_PREPUSH; // first stack the registers
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
end
|
end
|
`SEQ_SWI2:
|
`SEQ_SWI2:
|
begin
|
begin
|
k_forced_mem_size <= 1;
|
k_forced_mem_size <= 1;
|
{ k_eahi, k_ealo } <= 16'hfff4;
|
{ k_eahi, k_ealo } <= 16'hfff4;
|
k_pp_regs <= 8'hff;
|
k_pp_regs <= 8'hff;
|
k_set_e <= 1;
|
k_set_e <= 1;
|
state <= `SEQ_PREPUSH; // first stack the registers
|
state <= `SEQ_PREPUSH; // first stack the registers
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
end
|
end
|
`SEQ_SWI3:
|
`SEQ_SWI3:
|
begin
|
begin
|
k_forced_mem_size <= 1;
|
k_forced_mem_size <= 1;
|
{ k_eahi, k_ealo } <= 16'hfff2;
|
{ k_eahi, k_ealo } <= 16'hfff2;
|
k_pp_regs <= 8'hff;
|
k_pp_regs <= 8'hff;
|
k_set_e <= 1;
|
k_set_e <= 1;
|
state <= `SEQ_PREPUSH; // first stack the registers
|
state <= `SEQ_PREPUSH; // first stack the registers
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
end
|
end
|
`SEQ_UNDEF:
|
`SEQ_UNDEF:
|
begin
|
begin
|
k_forced_mem_size <= 1;
|
k_forced_mem_size <= 1;
|
{ k_eahi, k_ealo } <= 16'hfff0;
|
{ k_eahi, k_ealo } <= 16'hfff0;
|
k_pp_regs <= 8'hff;
|
k_pp_regs <= 8'hff;
|
k_set_e <= 1;
|
k_set_e <= 1;
|
state <= `SEQ_PREPUSH; // first stack the registers
|
state <= `SEQ_PREPUSH; // first stack the registers
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
end
|
end
|
`SEQ_LOADPC: /* loads the PC with the address taken from the reset vector */
|
`SEQ_LOADPC: /* loads the PC with the address taken from the reset vector */
|
begin
|
begin
|
$display("cpu_data_i %02x %t", cpu_data_i, $time);
|
$display("cpu_data_i %02x %t", cpu_data_i, $time);
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
end
|
end
|
`SEQ_FETCH: /* execution starts here */
|
`SEQ_FETCH: /* execution starts here */
|
begin
|
begin
|
if (k_nmi_req)
|
if (k_nmi_req)
|
state <= `SEQ_NMI;
|
state <= `SEQ_NMI;
|
else
|
else
|
if (k_firq_req & `FLAGF)
|
if (k_firq_req & `FLAGF)
|
state <= `SEQ_FIRQ;
|
state <= `SEQ_FIRQ;
|
else
|
else
|
if (k_irq_req & `FLAGI)
|
if (k_irq_req & `FLAGI)
|
state <= `SEQ_IRQ;
|
state <= `SEQ_IRQ;
|
else
|
else
|
begin
|
begin
|
state <= `SEQ_FETCH_1;
|
state <= `SEQ_FETCH_1;
|
k_cpu_addr <= regs_o_pc;
|
k_cpu_addr <= regs_o_pc;
|
end
|
end
|
end
|
end
|
`SEQ_FETCH_1:
|
`SEQ_FETCH_1:
|
begin
|
begin
|
k_cpu_oe <= 1;
|
k_cpu_oe <= 1;
|
k_inc_pc <= 1;
|
k_inc_pc <= 1;
|
k_p2_valid <= 0; // set when an k_opcode is page 2
|
k_p2_valid <= 0; // set when an k_opcode is page 2
|
k_p3_valid <= 0; // set when an k_opcode is page 3
|
k_p3_valid <= 0; // set when an k_opcode is page 3
|
k_pp_active_reg <= `RN_INV; // ensures that only push/pull control the left/dest muxes
|
k_pp_active_reg <= `RN_INV; // ensures that only push/pull control the left/dest muxes
|
state <= `SEQ_FETCH_2;
|
state <= `SEQ_FETCH_2;
|
end
|
end
|
`SEQ_FETCH_2:
|
`SEQ_FETCH_2:
|
begin
|
begin
|
k_opcode <= cpu_data_i;
|
k_opcode <= cpu_data_i;
|
case (cpu_data_i[7:0]) /* page 2 & 3 opcodes are recognized here */
|
case (cpu_data_i[7:0]) /* page 2 & 3 opcodes are recognized here */
|
8'h10:
|
8'h10:
|
begin
|
begin
|
k_p2_valid <= 1;
|
k_p2_valid <= 1;
|
state <= `SEQ_FETCH_3;
|
state <= `SEQ_FETCH_3;
|
end
|
end
|
8'h11:
|
8'h11:
|
begin
|
begin
|
k_p3_valid <= 1;
|
k_p3_valid <= 1;
|
state <= `SEQ_FETCH_3;
|
state <= `SEQ_FETCH_3;
|
end
|
end
|
8'h1e, 8'h1f:
|
8'h1e, 8'h1f:
|
state <= `SEQ_FETCH_3; // tfr, exg, treated separately
|
state <= `SEQ_FETCH_3; // tfr, exg, treated separately
|
default:
|
default:
|
state <= `SEQ_DECODE;
|
state <= `SEQ_DECODE;
|
endcase
|
endcase
|
end
|
end
|
`SEQ_FETCH_3:
|
`SEQ_FETCH_3:
|
begin
|
begin
|
state <= `SEQ_FETCH_4;
|
state <= `SEQ_FETCH_4;
|
k_cpu_addr <= regs_o_pc;
|
k_cpu_addr <= regs_o_pc;
|
end
|
end
|
`SEQ_FETCH_4:
|
`SEQ_FETCH_4:
|
begin
|
begin
|
k_cpu_oe <= 1;
|
k_cpu_oe <= 1;
|
state <= `SEQ_FETCH_5;
|
state <= `SEQ_FETCH_5;
|
end
|
end
|
`SEQ_FETCH_5: /* fetches a page 2 or 3 opcode */
|
`SEQ_FETCH_5: /* fetches a page 2 or 3 opcode */
|
begin
|
begin
|
k_postbyte <= cpu_data_i;
|
k_postbyte <= cpu_data_i;
|
k_inc_pc <= 1;
|
k_inc_pc <= 1;
|
state <= `SEQ_DECODE_P23;
|
state <= `SEQ_DECODE_P23;
|
end
|
end
|
`SEQ_DECODE:
|
`SEQ_DECODE:
|
begin
|
begin
|
/* here we have the first byte of the opcode and should be decided to which state we jump
|
/* here we have the first byte of the opcode and should be decided to which state we jump
|
* inherent means that no extra info is needed
|
* inherent means that no extra info is needed
|
* ALU opcodes need routing of registers to/from the ALU to the registers
|
* ALU opcodes need routing of registers to/from the ALU to the registers
|
*/
|
*/
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE: // unknown opcode or push/pull... refetch ?
|
`NONE: // unknown opcode or push/pull... refetch ?
|
begin
|
begin
|
casex (k_opcode)
|
if (op_SYNC) state <= `SEQ_SYNC;
|
8'h13: state <= `SEQ_SYNC;
|
else if (op_PUSH) // PUSH S&U
|
8'h39: // RTS
|
|
begin
|
|
state <= `SEQ_PREPULL;
|
|
k_pp_regs <= 8'h80; // Pull PC (RTS)all regs
|
|
end
|
|
8'b001101x0: // PUSH S&U
|
|
begin
|
begin
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
next_state <= `SEQ_PREPUSH;
|
next_state <= `SEQ_PREPUSH;
|
next_push_state <= `SEQ_FETCH;
|
next_push_state <= `SEQ_FETCH;
|
end
|
end
|
8'b001101x1: // PULL S&U
|
else if (op_PULL) // PULL S&U
|
begin
|
begin
|
next_state <= `SEQ_PREPULL;
|
next_state <= `SEQ_PREPULL;
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
end
|
end
|
8'h3B: // RTI
|
else /* we ignore unknown opcodes */
|
begin
|
|
state <= `SEQ_PREPULL;
|
|
k_pp_regs <= 8'hff; // all regs
|
|
end
|
|
default: /* we ignore unknown opcodes */
|
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
endcase
|
|
end
|
end
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
begin
|
begin
|
if (dec_o_alu_size)
|
if (dec_o_alu_size)
|
state <= `SEQ_PC_READ_H;
|
state <= `SEQ_PC_READ_H;
|
else
|
else
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
next_state <= `SEQ_GRAL_ALU;
|
next_state <= `SEQ_GRAL_ALU;
|
end
|
end
|
`INHERENT:
|
`INHERENT:
|
begin
|
begin
|
case (k_opcode)
|
if (op_RTI) // RTI
|
8'h3d: begin k_mul_cnt <= 1'h1; state <= `SEQ_GRAL_ALU; end // counter for mul
|
begin
|
8'h3f: state <= `SEQ_SWI;
|
state <= `SEQ_PREPULL;
|
default: state <= `SEQ_GRAL_ALU;
|
k_pp_regs <= 8'hff; // all regs
|
endcase
|
end
|
|
else if (op_RTS)
|
|
begin
|
|
state <= `SEQ_PREPULL;
|
|
k_pp_regs <= 8'h80; // Pull PC (RTS)all regs
|
|
end
|
|
else if (op_MUL)
|
|
begin k_mul_cnt <= 1'h1; state <= `SEQ_GRAL_ALU; end // counter for mul
|
|
else if (op_SWI)
|
|
state <= `SEQ_SWI;
|
|
else
|
|
state <= `SEQ_GRAL_ALU;
|
end
|
end
|
`DIRECT:
|
`DIRECT:
|
begin
|
begin
|
state <= `SEQ_PC_READ_L; // loads address
|
state <= `SEQ_PC_READ_L; // loads address
|
case (dec_o_p1_optype)
|
if (op_JSR) next_state <= `SEQ_JSR_PUSH;
|
`OP_JSR: next_state <= `SEQ_JSR_PUSH;
|
else if (op_JMP) next_state <= `SEQ_JMP_LOAD_PC;
|
`OP_JMP: next_state <= `SEQ_JMP_LOAD_PC;
|
else
|
default:
|
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
next_state <= `SEQ_MEM_READ_H;
|
next_state <= `SEQ_MEM_READ_H;
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
end
|
end
|
else
|
else
|
next_state <= `SEQ_GRAL_ALU; // no read
|
next_state <= `SEQ_GRAL_ALU; // no read
|
k_eahi <= regs_o_dp;
|
k_eahi <= regs_o_dp;
|
end
|
end
|
endcase
|
|
end
|
end
|
`INDEXED:
|
`INDEXED:
|
state <= `SEQ_IND_READ_EA;
|
state <= `SEQ_IND_READ_EA;
|
`EXTENDED:
|
`EXTENDED:
|
begin
|
begin
|
state <= `SEQ_PC_READ_H; // loads address
|
state <= `SEQ_PC_READ_H; // loads address
|
case (dec_o_p1_optype)
|
if (op_JSR) next_state <= `SEQ_JSR_PUSH;
|
`OP_JSR: next_state <= `SEQ_JSR_PUSH;
|
else if (op_JMP) next_state <= `SEQ_JMP_LOAD_PC;
|
`OP_JMP: next_state <= `SEQ_JMP_LOAD_PC;
|
else
|
default:
|
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
next_state <= `SEQ_MEM_READ_H;
|
next_state <= `SEQ_MEM_READ_H;
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
end
|
end
|
else
|
else
|
next_state <= `SEQ_GRAL_ALU; // no read
|
next_state <= `SEQ_GRAL_ALU; // no read
|
end
|
end
|
endcase
|
|
end
|
end
|
`REL8:
|
`REL8:
|
begin
|
begin
|
state <= `SEQ_PC_READ_L; // loads address
|
state <= `SEQ_PC_READ_L; // loads address
|
if (dec_o_p1_optype == `OP_JSR) // bsr
|
if (op_JSR) // bsr
|
next_state <= `SEQ_JSR_PUSH;
|
next_state <= `SEQ_JSR_PUSH;
|
else
|
else
|
next_state <= `SEQ_JMP_LOAD_PC; // offset loaded in this cycle, jump if needed
|
next_state <= `SEQ_JMP_LOAD_PC; // offset loaded in this cycle, jump if needed
|
end
|
end
|
`REL16:
|
`REL16:
|
begin
|
begin
|
state <= `SEQ_PC_READ_H; // loads address
|
state <= `SEQ_PC_READ_H; // loads address
|
if (dec_o_p1_optype == `OP_JSR) // lbsr
|
if (op_JSR) // lbsr
|
next_state <= `SEQ_JSR_PUSH;
|
next_state <= `SEQ_JSR_PUSH;
|
else
|
else
|
next_state <= `SEQ_JMP_LOAD_PC;
|
next_state <= `SEQ_JMP_LOAD_PC;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`SEQ_DECODE_P23:
|
`SEQ_DECODE_P23:
|
begin // has prefix 10 or 11
|
begin // has prefix 10 or 11
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE: // unknown k_opcode... re-fetch ?
|
`NONE: // unknown k_opcode... re-fetch ?
|
|
if (op_EXG) begin k_write_exg <= 1; state <= `SEQ_TFREXG; end
|
|
else if (op_TFR) begin k_write_tfr <= 1; state <= `SEQ_TFREXG; end
|
|
else
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
begin
|
begin
|
case (k_opcode)
|
|
8'h1e: begin k_write_exg <= 1; state <= `SEQ_TFREXG; end
|
|
8'h1f: begin k_write_tfr <= 1; state <= `SEQ_TFREXG; end
|
|
default:
|
|
begin
|
|
next_state <= `SEQ_GRAL_ALU;
|
next_state <= `SEQ_GRAL_ALU;
|
if (dec_o_alu_size)
|
if (dec_o_alu_size)
|
state <= `SEQ_PC_READ_H;
|
state <= `SEQ_PC_READ_H;
|
else
|
else
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
end
|
end
|
endcase
|
|
end
|
|
`INHERENT:
|
`INHERENT:
|
case (k_opcode)
|
if (op_SWI) state <= (k_p2_valid) ? `SEQ_SWI2:`SEQ_SWI3;
|
8'h3f: if (k_p2_valid) state <= `SEQ_SWI2;
|
else state <= `SEQ_GRAL_ALU;
|
else state <= `SEQ_SWI3;
|
|
default: state <= `SEQ_GRAL_ALU;
|
|
endcase
|
|
`DIRECT:
|
`DIRECT:
|
begin
|
begin
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
next_state <= `SEQ_MEM_READ_H;
|
next_state <= `SEQ_MEM_READ_H;
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
end
|
end
|
else
|
else
|
next_state <= `SEQ_GRAL_ALU; // no read
|
next_state <= `SEQ_GRAL_ALU; // no read
|
k_eahi <= regs_o_dp;
|
k_eahi <= regs_o_dp;
|
end
|
end
|
`INDEXED:
|
`INDEXED:
|
state <= `SEQ_IND_READ_EA;
|
state <= `SEQ_IND_READ_EA;
|
`EXTENDED:
|
`EXTENDED:
|
begin
|
begin
|
state <= `SEQ_PC_READ_H; // loads address
|
state <= `SEQ_PC_READ_H; // loads address
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
next_state <= `SEQ_MEM_READ_H;
|
next_state <= `SEQ_MEM_READ_H;
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
end
|
end
|
else
|
else
|
next_state <= `SEQ_GRAL_ALU; // no read
|
next_state <= `SEQ_GRAL_ALU; // no read
|
end
|
end
|
`REL16:
|
`REL16:
|
begin // long branches only
|
begin // long branches only
|
state <= `SEQ_PC_READ_H; // loads address
|
state <= `SEQ_PC_READ_H; // loads address
|
next_state <= `SEQ_JMP_LOAD_PC;
|
next_state <= `SEQ_JMP_LOAD_PC;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`SEQ_GRAL_ALU:
|
`SEQ_GRAL_ALU:
|
begin
|
begin
|
if (!k_mul_cnt)
|
if (!k_mul_cnt)
|
begin
|
begin
|
state <= `SEQ_GRAL_WBACK;
|
state <= `SEQ_GRAL_WBACK;
|
k_write_dest <= 1; /* write destination on wback */
|
k_write_dest <= 1; /* write destination on wback */
|
end
|
end
|
k_mul_cnt <= 1'h0;
|
k_mul_cnt <= 1'h0;
|
end
|
end
|
`SEQ_GRAL_WBACK:
|
`SEQ_GRAL_WBACK:
|
begin
|
begin
|
next_mem_state <= `SEQ_FETCH;
|
next_mem_state <= `SEQ_FETCH;
|
casex (k_opcode)
|
if (op_CWAI) state <= `SEQ_CWAI_STACK; // CWAI
|
8'h3C: state <= `SEQ_CWAI_STACK; // CWAI
|
else
|
default:
|
|
case (dec_o_dest_reg_addr)
|
case (dec_o_dest_reg_addr)
|
`RN_MEM8: state <= `SEQ_MEM_WRITE_L;
|
`RN_MEM8: state <= `SEQ_MEM_WRITE_L;
|
`RN_MEM16: state <= `SEQ_MEM_WRITE_H;
|
`RN_MEM16: state <= `SEQ_MEM_WRITE_H;
|
default:
|
default:
|
begin
|
begin
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
k_write_post_incdec <= dec_o_ea_wpost & (dec_o_p1_mode == `INDEXED);
|
k_write_post_incdec <= dec_o_ea_wpost & (dec_o_p1_mode == `INDEXED);
|
end
|
end
|
endcase
|
endcase
|
endcase
|
|
end
|
end
|
`SEQ_CWAI_STACK:
|
`SEQ_CWAI_STACK:
|
begin
|
begin
|
k_pp_regs <= 8'hff;
|
k_pp_regs <= 8'hff;
|
k_set_e <= 1;
|
k_set_e <= 1;
|
state <= `SEQ_PREPUSH; // first stack the registers
|
state <= `SEQ_PREPUSH; // first stack the registers
|
next_push_state <= `SEQ_CWAI_WAIT; // wait for interrupts
|
next_push_state <= `SEQ_CWAI_WAIT; // wait for interrupts
|
end
|
end
|
`SEQ_CWAI_WAIT: /* waits for an interrupt and process it */
|
`SEQ_CWAI_WAIT: /* waits for an interrupt and process it */
|
begin
|
begin
|
k_forced_mem_size <= 1;
|
k_forced_mem_size <= 1;
|
next_mem_state <= `SEQ_FETCH; // then continue fetching instructions
|
next_mem_state <= `SEQ_FETCH; // then continue fetching instructions
|
k_eahi <= 8'hff;
|
k_eahi <= 8'hff;
|
k_ealo[7:4] <= 4'hf;
|
k_ealo[7:4] <= 4'hf;
|
if (k_nmi_req)
|
if (k_nmi_req)
|
begin
|
begin
|
k_reg_nmi <= 3'h0;
|
k_reg_nmi <= 3'h0;
|
k_ealo[3:0] <= 4'hc;
|
k_ealo[3:0] <= 4'hc;
|
state <= `SEQ_MEM_READ_H; // load new PC
|
state <= `SEQ_MEM_READ_H; // load new PC
|
end
|
end
|
else
|
else
|
if (k_firq_req & `FLAGF)
|
if (k_firq_req & `FLAGF)
|
begin
|
begin
|
k_reg_firq <= 3'h0;
|
k_reg_firq <= 3'h0;
|
k_ealo[3:0] <= 4'h6;
|
k_ealo[3:0] <= 4'h6;
|
state <= `SEQ_MEM_READ_H; // load new PC
|
state <= `SEQ_MEM_READ_H; // load new PC
|
end
|
end
|
else
|
else
|
if (k_irq_req & `FLAGI)
|
if (k_irq_req & `FLAGI)
|
begin
|
begin
|
k_reg_irq <= 3'h0;
|
k_reg_irq <= 3'h0;
|
k_ealo[3:0] <= 4'h8;
|
k_ealo[3:0] <= 4'h8;
|
state <= `SEQ_MEM_READ_H; // load new PC
|
state <= `SEQ_MEM_READ_H; // load new PC
|
end
|
end
|
end
|
end
|
`SEQ_SYNC: /* sync works like this:
|
`SEQ_SYNC: /* sync works like this:
|
* waits for an interrupt request
|
* waits for an interrupt request
|
* we recognize an interrupt if the level was kept for 2 cycles
|
* we recognize an interrupt if the level was kept for 2 cycles
|
* then we don't call the service routine
|
* then we don't call the service routine
|
* if it was 3 or more cycles, then we call the service routine
|
* if it was 3 or more cycles, then we call the service routine
|
*/
|
*/
|
begin
|
begin
|
if (k_nmi_req)
|
if (k_nmi_req)
|
begin
|
begin
|
if (k_reg_nmi == 3'b111) // at least 3 cycles long
|
if (k_reg_nmi == 3'b111) // at least 3 cycles long
|
state <= `SEQ_NMI;
|
state <= `SEQ_NMI;
|
else
|
else
|
begin
|
begin
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
k_reg_nmi <= 3'h0;
|
k_reg_nmi <= 3'h0;
|
end
|
end
|
end
|
end
|
else
|
else
|
if (k_firq_req & `FLAGF)
|
if (k_firq_req & `FLAGF)
|
begin
|
begin
|
if (k_reg_firq == 3'b111) // at least 3 cycles long
|
if (k_reg_firq == 3'b111) // at least 3 cycles long
|
state <= `SEQ_FIRQ;
|
state <= `SEQ_FIRQ;
|
else
|
else
|
begin
|
begin
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
k_reg_firq <= 3'h0;
|
k_reg_firq <= 3'h0;
|
end
|
end
|
end
|
end
|
else
|
else
|
if (k_irq_req & `FLAGI)
|
if (k_irq_req & `FLAGI)
|
begin
|
begin
|
if (k_reg_irq == 3'b111) // at least 3 cycles long
|
if (k_reg_irq == 3'b111) // at least 3 cycles long
|
state <= `SEQ_IRQ;
|
state <= `SEQ_IRQ;
|
else
|
else
|
begin
|
begin
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
k_reg_irq <= 3'h0;
|
k_reg_irq <= 3'h0;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= `SEQ_FETCH_1;
|
state <= `SEQ_FETCH_1;
|
k_cpu_addr <= regs_o_pc;
|
k_cpu_addr <= regs_o_pc;
|
end
|
end
|
end
|
end
|
`SEQ_TFREXG:
|
`SEQ_TFREXG:
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
`SEQ_IND_READ_EA: // reads EA byte
|
`SEQ_IND_READ_EA: // reads EA byte
|
begin
|
begin
|
k_cpu_addr <= regs_o_pc;
|
k_cpu_addr <= regs_o_pc;
|
state <= `SEQ_IND_READ_EA_1;
|
state <= `SEQ_IND_READ_EA_1;
|
k_inc_pc <= 1;
|
k_inc_pc <= 1;
|
end
|
end
|
`SEQ_IND_READ_EA_1:
|
`SEQ_IND_READ_EA_1:
|
begin
|
begin
|
k_cpu_oe <= 1; // read
|
k_cpu_oe <= 1; // read
|
state <= `SEQ_IND_READ_EA_2;
|
state <= `SEQ_IND_READ_EA_2;
|
end
|
end
|
`SEQ_IND_READ_EA_2:
|
`SEQ_IND_READ_EA_2:
|
begin
|
begin
|
k_ind_ea <= cpu_data_i;
|
k_ind_ea <= cpu_data_i;
|
state <= `SEQ_IND_DECODE;
|
state <= `SEQ_IND_DECODE;
|
end
|
end
|
`SEQ_IND_DECODE: // here we have to see what we need for indexed...
|
`SEQ_IND_DECODE: // here we have to see what we need for indexed...
|
begin
|
begin
|
k_indirect_loaded <= 1'b0;
|
k_indirect_loaded <= 1'b0;
|
if (dec_o_ea_ofs8)
|
if (dec_o_ea_ofs8)
|
begin // load 1 byte offset
|
begin // load 1 byte offset
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
end
|
end
|
else
|
else
|
if (dec_o_ea_ofs16)
|
if (dec_o_ea_ofs16)
|
begin // load 2 bytes offset
|
begin // load 2 bytes offset
|
state <= `SEQ_PC_READ_H;
|
state <= `SEQ_PC_READ_H;
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
end
|
end
|
else
|
else
|
if (dec_o_p1_optype == `OP_JSR) // jsr
|
if (op_JSR) // jsr
|
begin
|
|
next_state <= `SEQ_JSR_PUSH;
|
next_state <= `SEQ_JSR_PUSH;
|
end
|
|
else
|
else
|
begin // no extra load...
|
begin // no extra load...
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH; // operand lands in k_memhi/lo
|
k_mem_dest <= `MEMDEST_MH; // operand lands in k_memhi/lo
|
next_mem_state <= `SEQ_GRAL_ALU;
|
next_mem_state <= `SEQ_GRAL_ALU;
|
state <= `SEQ_MEM_READ_H;
|
state <= `SEQ_MEM_READ_H;
|
if (dec_o_ea_indirect)
|
if (dec_o_ea_indirect)
|
k_forced_mem_size <= 1; // to load indirect address
|
k_forced_mem_size <= 1; // to load indirect address
|
end
|
end
|
else
|
else
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
end
|
end
|
end
|
end
|
`SEQ_IND_DECODE_OFS: // loads argument if needed
|
`SEQ_IND_DECODE_OFS: // loads argument if needed
|
begin
|
begin
|
if (dec_o_p1_optype == `OP_JSR) // jsr
|
if (op_JSR) // jsr
|
begin
|
|
next_state <= `SEQ_JSR_PUSH;
|
next_state <= `SEQ_JSR_PUSH;
|
end
|
|
else
|
else
|
begin
|
begin
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH; // operand land in k_memhi/lo
|
k_mem_dest <= `MEMDEST_MH; // operand land in k_memhi/lo
|
next_mem_state <= `SEQ_GRAL_ALU;
|
next_mem_state <= `SEQ_GRAL_ALU;
|
state <= `SEQ_MEM_READ_H;
|
state <= `SEQ_MEM_READ_H;
|
if (dec_o_ea_indirect)
|
if (dec_o_ea_indirect)
|
k_forced_mem_size <= 1; // to load indirect address
|
k_forced_mem_size <= 1; // to load indirect address
|
end
|
end
|
else
|
else
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
end
|
end
|
end
|
end
|
`SEQ_JMP_LOAD_PC:
|
`SEQ_JMP_LOAD_PC:
|
begin
|
begin
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
end
|
end
|
`SEQ_JSR_PUSH:
|
`SEQ_JSR_PUSH:
|
begin
|
begin
|
k_pp_active_reg <= `RN_PC; // push PC
|
k_pp_active_reg <= `RN_PC; // push PC
|
state <= `SEQ_PUSH_WRITE_L;
|
state <= `SEQ_PUSH_WRITE_L;
|
next_state <= `SEQ_JMP_LOAD_PC;
|
next_state <= `SEQ_JMP_LOAD_PC;
|
end
|
end
|
`SEQ_PREPUSH:
|
`SEQ_PREPUSH:
|
begin
|
begin
|
next_state <= `SEQ_PREPUSH;
|
next_state <= `SEQ_PREPUSH;
|
if (k_pp_regs > 0)
|
if (k_pp_regs > 0)
|
begin
|
begin
|
state <= `SEQ_PUSH_WRITE_L;
|
state <= `SEQ_PUSH_WRITE_L;
|
end
|
end
|
else
|
else
|
state <= next_push_state;
|
state <= next_push_state;
|
if (k_pp_regs[7]) begin k_pp_regs[7] <= 0; k_pp_active_reg <= `RN_PC; end
|
if (k_pp_regs[7]) begin k_pp_regs[7] <= 0; k_pp_active_reg <= `RN_PC; end
|
else
|
else
|
if (k_pp_regs[6]) begin k_pp_regs[6] <= 0; k_pp_active_reg <= (dec_o_use_s) ? `RN_U:`RN_S; end
|
if (k_pp_regs[6]) begin k_pp_regs[6] <= 0; k_pp_active_reg <= (dec_o_use_s) ? `RN_U:`RN_S; end
|
else
|
else
|
if (k_pp_regs[5]) begin k_pp_regs[5] <= 0; k_pp_active_reg <= `RN_IY; end
|
if (k_pp_regs[5]) begin k_pp_regs[5] <= 0; k_pp_active_reg <= `RN_IY; end
|
else
|
else
|
if (k_pp_regs[4]) begin k_pp_regs[4] <= 0; k_pp_active_reg <= `RN_IX; end
|
if (k_pp_regs[4]) begin k_pp_regs[4] <= 0; k_pp_active_reg <= `RN_IX; end
|
else
|
else
|
if (k_pp_regs[3]) begin k_pp_regs[3] <= 0; k_pp_active_reg <= `RN_DP; end
|
if (k_pp_regs[3]) begin k_pp_regs[3] <= 0; k_pp_active_reg <= `RN_DP; end
|
else
|
else
|
if (k_pp_regs[2]) begin k_pp_regs[2] <= 0; k_pp_active_reg <= `RN_ACCB; end
|
if (k_pp_regs[2]) begin k_pp_regs[2] <= 0; k_pp_active_reg <= `RN_ACCB; end
|
else
|
else
|
if (k_pp_regs[1]) begin k_pp_regs[1] <= 0; k_pp_active_reg <= `RN_ACCA; end
|
if (k_pp_regs[1]) begin k_pp_regs[1] <= 0; k_pp_active_reg <= `RN_ACCA; end
|
else
|
else
|
if (k_pp_regs[0]) begin k_pp_regs[0] <= 0; k_pp_active_reg <= `RN_CC; end
|
if (k_pp_regs[0]) begin k_pp_regs[0] <= 0; k_pp_active_reg <= `RN_CC; end
|
end
|
end
|
`SEQ_PREPULL:
|
`SEQ_PREPULL:
|
begin
|
begin
|
if (k_pp_regs != 8'h0)
|
if (k_pp_regs != 8'h0)
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH;
|
k_mem_dest <= `MEMDEST_MH;
|
next_mem_state <= `SEQ_PREPULL;
|
next_mem_state <= `SEQ_PREPULL;
|
end
|
end
|
else
|
else
|
state <= `SEQ_FETCH; // end of sequence
|
state <= `SEQ_FETCH; // end of sequence
|
if (k_pp_regs[0]) begin k_pp_active_reg <= `RN_CC; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
|
if (k_pp_regs[0]) begin k_pp_active_reg <= `RN_CC; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
|
else
|
else
|
if ((k_opcode == 8'h3B) && (!`FLAGE)) // not all registers have to be pulled
|
if (op_RTI && (!`FLAGE)) // not all registers have to be pulled
|
begin
|
begin
|
k_pp_active_reg <= `RN_PC; k_pp_regs <= 0; state <= `SEQ_MEM_READ_H;
|
k_pp_active_reg <= `RN_PC; k_pp_regs <= 0; state <= `SEQ_MEM_READ_H;
|
end
|
end
|
else
|
else
|
if (k_pp_regs[1]) begin k_pp_active_reg <= `RN_ACCA; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
|
if (k_pp_regs[1]) begin k_pp_active_reg <= `RN_ACCA; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
|
else
|
else
|
if (k_pp_regs[2]) begin k_pp_active_reg <= `RN_ACCB; k_pp_regs[2] <= 0; state <= `SEQ_MEM_READ_L; end
|
if (k_pp_regs[2]) begin k_pp_active_reg <= `RN_ACCB; k_pp_regs[2] <= 0; state <= `SEQ_MEM_READ_L; end
|
else
|
else
|
if (k_pp_regs[3]) begin k_pp_active_reg <= `RN_DP; k_pp_regs[3] <= 0; state <= `SEQ_MEM_READ_L; end
|
if (k_pp_regs[3]) begin k_pp_active_reg <= `RN_DP; k_pp_regs[3] <= 0; state <= `SEQ_MEM_READ_L; end
|
else
|
else
|
if (k_pp_regs[4]) begin k_pp_active_reg <= `RN_IX; k_pp_regs[4] <= 0; state <= `SEQ_MEM_READ_H;end
|
if (k_pp_regs[4]) begin k_pp_active_reg <= `RN_IX; k_pp_regs[4] <= 0; state <= `SEQ_MEM_READ_H;end
|
else
|
else
|
if (k_pp_regs[5]) begin k_pp_active_reg <= `RN_IY; k_pp_regs[5] <= 0; state <= `SEQ_MEM_READ_H;end
|
if (k_pp_regs[5]) begin k_pp_active_reg <= `RN_IY; k_pp_regs[5] <= 0; state <= `SEQ_MEM_READ_H;end
|
else
|
else
|
if (k_pp_regs[6]) begin k_pp_active_reg <= (dec_o_use_s) ? `RN_U:`RN_S; k_pp_regs[6] <= 0; state <= `SEQ_MEM_READ_H; end
|
if (k_pp_regs[6]) begin k_pp_active_reg <= (dec_o_use_s) ? `RN_U:`RN_S; k_pp_regs[6] <= 0; state <= `SEQ_MEM_READ_H; end
|
else
|
else
|
if (k_pp_regs[7]) begin k_pp_active_reg <= `RN_PC; k_pp_regs[7] <= 0; state <= `SEQ_MEM_READ_H; end
|
if (k_pp_regs[7]) begin k_pp_active_reg <= `RN_PC; k_pp_regs[7] <= 0; state <= `SEQ_MEM_READ_H; end
|
end
|
end
|
`SEQ_PUSH_WRITE_L: // first low byte push
|
`SEQ_PUSH_WRITE_L: // first low byte push
|
begin
|
begin
|
k_cpu_data_o <= regs_o_left_path_data[7:0];
|
k_cpu_data_o <= regs_o_left_path_data[7:0];
|
state <= `SEQ_PUSH_WRITE_L_1;
|
state <= `SEQ_PUSH_WRITE_L_1;
|
k_cpu_we <= 1; // write
|
k_cpu_we <= 1; // write
|
k_cpu_addr <= regs_o_su - 16'h1;
|
k_cpu_addr <= regs_o_su - 16'h1;
|
k_dec_su <= 1;
|
k_dec_su <= 1;
|
end
|
end
|
`SEQ_PUSH_WRITE_L_1:
|
`SEQ_PUSH_WRITE_L_1:
|
begin
|
begin
|
if (k_pp_active_reg < `RN_ACCA)
|
if (k_pp_active_reg < `RN_ACCA)
|
state <= `SEQ_PUSH_WRITE_H;
|
state <= `SEQ_PUSH_WRITE_H;
|
else
|
else
|
if (k_pp_regs[3:0] > 0)
|
if (k_pp_regs[3:0] > 0)
|
state <= `SEQ_PREPUSH;
|
state <= `SEQ_PREPUSH;
|
else
|
else
|
state <= next_push_state;
|
state <= next_push_state;
|
k_cpu_addr <= k_cpu_addr - 16'h1; // when pushing 16 bits the second decrement comes too late
|
k_cpu_addr <= k_cpu_addr - 16'h1; // when pushing 16 bits the second decrement comes too late
|
end
|
end
|
`SEQ_PUSH_WRITE_H: // reads high byte
|
`SEQ_PUSH_WRITE_H: // reads high byte
|
begin
|
begin
|
k_cpu_data_o <= regs_o_left_path_data[15:8];
|
k_cpu_data_o <= regs_o_left_path_data[15:8];
|
state <= `SEQ_PUSH_WRITE_H_1;
|
state <= `SEQ_PUSH_WRITE_H_1;
|
k_cpu_we <= 1; // write
|
k_cpu_we <= 1; // write
|
if (k_pp_active_reg >= `RN_ACCA)
|
if (k_pp_active_reg >= `RN_ACCA)
|
k_cpu_addr <= regs_o_su; // address for 8 bit register
|
k_cpu_addr <= regs_o_su; // address for 8 bit register
|
k_dec_su <= 1; // decrement stack pointer
|
k_dec_su <= 1; // decrement stack pointer
|
end
|
end
|
`SEQ_PUSH_WRITE_H_1:
|
`SEQ_PUSH_WRITE_H_1:
|
begin
|
begin
|
if (next_state == `SEQ_JMP_LOAD_PC)
|
if (next_state == `SEQ_JMP_LOAD_PC)
|
k_write_pc <= 1; // load PC in the next cycle, the mux output will have the right source
|
k_write_pc <= 1; // load PC in the next cycle, the mux output will have the right source
|
state <= next_state;
|
state <= next_state;
|
end
|
end
|
`SEQ_PC_READ_H: // reads high byte for [PC], used by IMM, DIR, EXT
|
`SEQ_PC_READ_H: // reads high byte for [PC], used by IMM, DIR, EXT
|
begin
|
begin
|
k_cpu_addr <= regs_o_pc;
|
k_cpu_addr <= regs_o_pc;
|
state <= `SEQ_PC_READ_H_1;
|
state <= `SEQ_PC_READ_H_1;
|
k_inc_pc <= 1;
|
k_inc_pc <= 1;
|
end
|
end
|
`SEQ_PC_READ_H_1:
|
`SEQ_PC_READ_H_1:
|
begin
|
begin
|
k_cpu_oe <= 1; // read
|
k_cpu_oe <= 1; // read
|
state <= `SEQ_PC_READ_H_2;
|
state <= `SEQ_PC_READ_H_2;
|
end
|
end
|
`SEQ_PC_READ_H_2:
|
`SEQ_PC_READ_H_2:
|
begin
|
begin
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`REL16, `IMMEDIATE: k_memhi <= cpu_data_i;
|
`REL16, `IMMEDIATE: k_memhi <= cpu_data_i;
|
`EXTENDED: k_eahi <= cpu_data_i;
|
`EXTENDED: k_eahi <= cpu_data_i;
|
`INDEXED: k_ofshi <= cpu_data_i;
|
`INDEXED: k_ofshi <= cpu_data_i;
|
endcase
|
endcase
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
end
|
end
|
`SEQ_PC_READ_L: // reads low byte [PC]
|
`SEQ_PC_READ_L: // reads low byte [PC]
|
begin
|
begin
|
k_cpu_addr <= regs_o_pc;
|
k_cpu_addr <= regs_o_pc;
|
state <= `SEQ_PC_READ_L_1;
|
state <= `SEQ_PC_READ_L_1;
|
k_inc_pc <= 1;
|
k_inc_pc <= 1;
|
end
|
end
|
`SEQ_PC_READ_L_1:
|
`SEQ_PC_READ_L_1:
|
begin
|
begin
|
k_cpu_oe <= 1; // read
|
k_cpu_oe <= 1; // read
|
state <= `SEQ_PC_READ_L_2;
|
state <= `SEQ_PC_READ_L_2;
|
end
|
end
|
`SEQ_PC_READ_L_2:
|
`SEQ_PC_READ_L_2:
|
begin
|
begin
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE: k_pp_regs <= cpu_data_i; // push & pull
|
`NONE: k_pp_regs <= cpu_data_i; // push & pull
|
`REL8, `REL16, `IMMEDIATE: k_memlo <= cpu_data_i;
|
`REL8, `REL16, `IMMEDIATE: k_memlo <= cpu_data_i;
|
`DIRECT, `EXTENDED: k_ealo <= cpu_data_i;
|
`DIRECT, `EXTENDED: k_ealo <= cpu_data_i;
|
`INDEXED: k_ofslo <= cpu_data_i;
|
`INDEXED: k_ofslo <= cpu_data_i;
|
endcase
|
endcase
|
if ((next_state == `SEQ_JMP_LOAD_PC) & (dec_o_cond_taken))
|
if ((next_state == `SEQ_JMP_LOAD_PC) & (dec_o_cond_taken))
|
k_write_pc <= 1; // load PC in the next cycle, the mux output will have the right source
|
k_write_pc <= 1; // load PC in the next cycle, the mux output will have the right source
|
state <= next_state;
|
state <= next_state;
|
end
|
end
|
`SEQ_MEM_READ_H: // reads high byte
|
`SEQ_MEM_READ_H: // reads high byte
|
begin
|
begin
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
|
|
`INDEXED:
|
`INDEXED:
|
if (k_indirect_loaded)
|
if (k_indirect_loaded)
|
k_cpu_addr <= { k_memhi, k_memlo };
|
k_cpu_addr <= { k_memhi, k_memlo };
|
else
|
else
|
k_cpu_addr <= regs_o_eamem_addr;
|
k_cpu_addr <= regs_o_eamem_addr;
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
default:
|
|
if (op_PULL | op_RTI | op_RTS)
|
|
begin
|
|
k_cpu_addr <= regs_o_su;
|
|
k_inc_su <= 1;
|
|
end
|
|
else
|
|
k_cpu_addr <= { k_eahi, k_ealo };
|
endcase
|
endcase
|
if (k_forced_mem_size | dec_o_source_size | (k_pp_active_reg < `RN_ACCA))
|
if (k_forced_mem_size | dec_o_source_size | (k_pp_active_reg < `RN_ACCA))
|
state <= `SEQ_MEM_READ_H_1;
|
state <= `SEQ_MEM_READ_H_1;
|
else
|
else
|
state <= `SEQ_MEM_READ_L_1;
|
state <= `SEQ_MEM_READ_L_1;
|
k_forced_mem_size <= 0; // used for vector fetch
|
k_forced_mem_size <= 0; // used for vector fetch
|
end
|
end
|
`SEQ_MEM_READ_H_1:
|
`SEQ_MEM_READ_H_1:
|
begin
|
begin
|
k_cpu_oe <= 1; // read
|
k_cpu_oe <= 1; // read
|
state <= `SEQ_MEM_READ_H_2;
|
state <= `SEQ_MEM_READ_H_2;
|
end
|
end
|
`SEQ_MEM_READ_H_2:
|
`SEQ_MEM_READ_H_2:
|
begin
|
begin
|
case (k_mem_dest)
|
case (k_mem_dest)
|
`MEMDEST_PC,//: k_new_pc[15:8] <= cpu_data_i;
|
`MEMDEST_PC,//: k_new_pc[15:8] <= cpu_data_i;
|
`MEMDEST_MH: k_memhi <= cpu_data_i;
|
`MEMDEST_MH: k_memhi <= cpu_data_i;
|
`MEMDEST_AH: k_eahi <= cpu_data_i;
|
`MEMDEST_AH: k_eahi <= cpu_data_i;
|
endcase
|
endcase
|
state <= `SEQ_MEM_READ_L_1;
|
state <= `SEQ_MEM_READ_L_1;
|
k_cpu_addr <= k_cpu_addr + 16'h1;
|
k_cpu_addr <= k_cpu_addr + 16'h1;
|
case (dec_o_p1_mode)
|
if (op_PULL | op_RTI | op_RTS)
|
`NONE: begin k_inc_su <= 1; end // pull, rts, rti
|
k_inc_su <= 1;
|
endcase
|
|
end
|
end
|
`SEQ_MEM_READ_L: // reads low byte
|
`SEQ_MEM_READ_L: // reads low byte
|
begin
|
begin
|
// falls through from READ_MEM_H with the right address
|
// falls through from READ_MEM_H with the right address
|
case (dec_o_p1_mode)
|
if (op_PULL | op_RTI | op_RTS)
|
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
|
begin
|
endcase
|
k_cpu_addr <= regs_o_su;
|
|
k_inc_su <= 1;
|
|
end
|
state <= `SEQ_MEM_READ_L_1;
|
state <= `SEQ_MEM_READ_L_1;
|
end
|
end
|
`SEQ_MEM_READ_L_1:
|
`SEQ_MEM_READ_L_1:
|
begin
|
begin
|
k_cpu_oe <= 1; // read
|
k_cpu_oe <= 1; // read
|
state <= `SEQ_MEM_READ_L_2;
|
state <= `SEQ_MEM_READ_L_2;
|
end
|
end
|
`SEQ_MEM_READ_L_2:
|
`SEQ_MEM_READ_L_2:
|
begin
|
begin
|
case (k_mem_dest)
|
case (k_mem_dest)
|
`MEMDEST_PC,
|
`MEMDEST_PC,
|
`MEMDEST_MH: k_memlo <= cpu_data_i;
|
`MEMDEST_MH: k_memlo <= cpu_data_i;
|
`MEMDEST_AH: k_ealo <= cpu_data_i;
|
`MEMDEST_AH: k_ealo <= cpu_data_i;
|
endcase
|
endcase
|
case (dec_o_p1_mode)
|
if (op_PULL | op_RTI | op_RTS) k_write_dest <= 1; // FIXME: which other opcode is inherent and needs write-back ?
|
`NONE, `INHERENT: k_write_dest <= 1; // pull, rts, rti
|
|
endcase
|
|
if (next_mem_state == `SEQ_LOADPC)
|
if (next_mem_state == `SEQ_LOADPC)
|
k_write_pc <= 1;
|
k_write_pc <= 1;
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`INDEXED: // address loaded, load argument
|
`INDEXED: // address loaded, load argument
|
if (k_indirect_loaded | (!dec_o_ea_indirect))
|
if (k_indirect_loaded | (!dec_o_ea_indirect))
|
state <= next_mem_state;
|
state <= next_mem_state;
|
else
|
else
|
begin
|
begin
|
state <= `SEQ_MEM_READ_H;
|
state <= `SEQ_MEM_READ_H;
|
k_indirect_loaded <= 1'b1;
|
k_indirect_loaded <= 1'b1;
|
end
|
end
|
default:
|
default:
|
state <= next_mem_state;
|
state <= next_mem_state;
|
endcase
|
endcase
|
end
|
end
|
`SEQ_MEM_WRITE_H: // writes high byte
|
`SEQ_MEM_WRITE_H: // writes high byte
|
begin
|
begin
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
endcase
|
endcase
|
k_cpu_data_o <= datamux_o_dest[15:8];
|
k_cpu_data_o <= datamux_o_dest[15:8];
|
state <= `SEQ_MEM_WRITE_H_1;
|
state <= `SEQ_MEM_WRITE_H_1;
|
k_cpu_we <= 1; // read
|
k_cpu_we <= 1; // read
|
end
|
end
|
`SEQ_MEM_WRITE_H_1:
|
`SEQ_MEM_WRITE_H_1:
|
begin
|
begin
|
state <= `SEQ_MEM_WRITE_L;
|
state <= `SEQ_MEM_WRITE_L;
|
k_cpu_addr <= k_cpu_addr + 16'h1;
|
k_cpu_addr <= k_cpu_addr + 16'h1;
|
end
|
end
|
`SEQ_MEM_WRITE_L: // reads high byte
|
`SEQ_MEM_WRITE_L: // reads high byte
|
begin
|
begin
|
if (!dec_o_alu_size) // only if it is an 8 bit write
|
if (!dec_o_alu_size) // only if it is an 8 bit write
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
endcase
|
endcase
|
k_cpu_data_o <= datamux_o_dest[7:0];
|
k_cpu_data_o <= datamux_o_dest[7:0];
|
state <= `SEQ_MEM_WRITE_L_1;
|
state <= `SEQ_MEM_WRITE_L_1;
|
k_cpu_we <= 1; // write
|
k_cpu_we <= 1; // write
|
end
|
end
|
`SEQ_MEM_WRITE_L_1:
|
`SEQ_MEM_WRITE_L_1:
|
begin
|
begin
|
k_write_post_incdec <= dec_o_ea_wpost;
|
k_write_post_incdec <= dec_o_ea_wpost;
|
state <= next_mem_state;
|
state <= next_mem_state;
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
initial
|
initial
|
begin
|
begin
|
k_cpu_oe = 0;
|
k_cpu_oe = 0;
|
k_cpu_we = 0;
|
k_cpu_we = 0;
|
k_mem_dest = 0;
|
k_mem_dest = 0;
|
k_new_pc = 16'hffff;
|
k_new_pc = 16'hffff;
|
k_write_tfr = 0;
|
k_write_tfr = 0;
|
k_write_exg = 0;
|
k_write_exg = 0;
|
k_mul_cnt = 0;
|
k_mul_cnt = 0;
|
k_write_dest = 0;
|
k_write_dest = 0;
|
k_indirect_loaded = 0;
|
k_indirect_loaded = 0;
|
end
|
end
|
endmodule
|
endmodule
|
|
|
