/*
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/*
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* Synthesis top Module for the MC6809/HD6309 compatible core.
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* Synthesis top Module for the MC6809/HD6309 compatible core.
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* This top module has been tested in the MachXO2-7000HE breakout board
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* This top module has been tested in the MachXO2-7000HE breakout board
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* (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com
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* (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com
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* Distributed under the terms of the Lesser GPL
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* Distributed under the terms of the Lesser GPL
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*
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*
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* Implemented using diamond 2.1
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* Implemented using diamond 2.1
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*/
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*/
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module CC3_top(
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module CC3_top(
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input wire clk40_i,
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input wire clk40_i,
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/* CPU Bus */
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/* CPU Bus */
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output wire cpuclk_o,
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output wire cpuclk_o,
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output wire reset_o,
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output wire reset_o,
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output wire [15:0] addr_o,
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output wire [15:0] addr_o,
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output wire oen_o,
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output wire oen_o,
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output wire wen_o,
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output wire wen_o,
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output wire cen_o,
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output wire cen_o,
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output wire [7:0] data_io,
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output wire [7:0] data_io,
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output wire [5:0] state_o,
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output wire [5:0] state_o,
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/* Debug */
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/* Debug */
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output wire [7:0] leds_o,
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output wire [7:0] leds_o,
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/* VGA output */
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/* VGA output */
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output wire hsync_o,
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output wire hsync_o,
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output wire vsync_o,
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output wire vsync_o,
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output wire red_o,
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output wire red_o,
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output wire green_o,
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output wire green_o,
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output wire blue_o
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output wire blue_o
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);
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);
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reg cpu_clk, clk_div2;
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reg cpu_clk, clk_div2;
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reg [3:0] reset_cnt;
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reg [3:0] reset_cnt;
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reg [7:0] leds_r;
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reg [7:0] leds_r;
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/* CPU IO */
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/* CPU IO */
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wire [15:0] cpu0_addr_o, cpu1_addr_o;
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wire [15:0] cpu0_addr_o, cpu1_addr_o;
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wire [7:0] cpu0_data_in, cpu0_data_out, cpu1_data_in, cpu1_data_out;
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wire [7:0] cpu0_data_in, cpu0_data_out, cpu1_data_in, cpu1_data_out;
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wire cpu0_we, cpu0_oe, cpu1_we, cpu1_oe, cpu_reset;
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wire cpu0_we, cpu0_oe, cpu1_we, cpu1_oe, cpu_reset;
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wire [5:0] cpu0_state;
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wire [5:0] cpu0_state;
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/* Module io */
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/* Module io */
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assign addr_o = cpu0_addr_o;
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assign addr_o = cpu0_addr_o;
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assign data_io = cpu0_we ? cpu0_data_out:cpu0_data_in;
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assign data_io = cpu0_we ? cpu0_data_out:cpu0_data_in;
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/*
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assign hsync_o = 0;
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assign hsync_o = 0;
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assign vsync_o = 0;
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assign vsync_o = 0;
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assign red_o = 0;
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assign red_o = 0;
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assign green_o = 0;
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assign green_o = 0;
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assign blue_o = 0;
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assign blue_o = 0;
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*/
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assign leds_o = leds_r;
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assign leds_o = leds_r;
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assign oen_o = !cpu0_oe;
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assign oen_o = !cpu0_oe;
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assign wen_o = !cpu0_we;
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assign wen_o = cpu0_we & (cpu0_addr_o[15:12] == 4'h0);
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assign cen_o = !(cpu0_oe | cpu0_we);
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assign cen_o = !(cpu0_oe | cpu0_we);
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assign cpuclk_o = cpu_clk;
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assign cpuclk_o = cpu_clk;
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assign reset_o = cpu_reset;
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assign reset_o = cpu_reset;
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assign state_o = cpu0_state;
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assign state_o = cpu0_state;
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always @(posedge clk40_i)
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always @(posedge clk40_i)
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cpu_clk <= !cpu_clk;
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cpu_clk <= !cpu_clk;
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assign cpu_reset = reset_cnt != 4'd14;
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assign cpu_reset = reset_cnt != 4'd14;
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always @(posedge cpu_clk)
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always @(posedge cpu_clk)
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begin
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begin
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if (reset_cnt != 4'd14)
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if (reset_cnt != 4'd14)
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reset_cnt <= reset_cnt + 4'h1;
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reset_cnt <= reset_cnt + 4'h1;
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if (cpu0_we)
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if (cpu0_we)
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leds_r <= cpu0_data_out;
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leds_r <= cpu0_data_out;
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end
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end
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MC6809_cpu cpu0(
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MC6809_cpu cpu0(
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.cpu_clk(cpu_clk),
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.cpu_clk(cpu_clk),
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.cpu_reset(cpu_reset),
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.cpu_reset(cpu_reset),
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.cpu_nmi_n(1'b0),
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.cpu_nmi_n(1'b0),
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.cpu_irq_n(1'b0),
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.cpu_irq_n(1'b0),
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.cpu_firq_n(1'b0),
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.cpu_firq_n(1'b0),
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.cpu_state_o(cpu0_state),
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.cpu_state_o(cpu0_state),
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.cpu_we_o(cpu0_we),
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.cpu_we_o(cpu0_we),
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.cpu_oe_o(cpu0_oe),
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.cpu_oe_o(cpu0_oe),
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.cpu_addr_o(cpu0_addr_o),
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.cpu_addr_o(cpu0_addr_o),
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.cpu_data_i(cpu0_data_in),
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.cpu_data_i(cpu0_data_in),
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.cpu_data_o(cpu0_data_out)
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.cpu_data_o(cpu0_data_out)
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);
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);
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/* Memory */
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/* Memory */
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wire bios_en, video_en;
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wire [7:0] data_from_bios, data_from_video;
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assign bios_en = cpu0_addr_o[15:12] == 4'hf;
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assign video_en = cpu0_addr_o[15:12] == 4'h0;
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assign cpu0_data_in = bios_en ? data_from_bios:
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video_en ? data_from_video:8'hzz;
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bios2k bios(
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bios2k bios(
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.DataInA(cpu0_data_out[7:0]),
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.DataInA(cpu0_data_out[7:0]),
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.DataInB(cpu1_data_out[7:0]),
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.DataInB(cpu1_data_out[7:0]),
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.AddressA(cpu0_addr_o[10:0]),
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.AddressA(cpu0_addr_o[10:0]),
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.AddressB(cpu1_addr_o[10:0]),
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.AddressB(cpu1_addr_o[10:0]),
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.ClockA(clk40_i),
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.ClockA(clk40_i),
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.ClockB(clk40_i),
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.ClockB(clk40_i),
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.ClockEnA((cpu0_we | cpu0_oe)),
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.ClockEnA((cpu0_oe | cpu_we) & bios_en),
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.ClockEnB(1'b0),
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.ClockEnB(1'b0),
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.WrA(cpu0_we),
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.WrA(cpu0_we & bios_en),
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.WrB(1'b0),//cpu1_we),
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.WrB(1'b0),//cpu1_we),
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.ResetA(1'b0),
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.ResetA(1'b0),
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.ResetB(1'b0),
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.ResetB(1'b0),
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.QA(cpu0_data_in),
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.QA(data_from_bios),
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.QB()
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.QB()
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);
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);
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vgatext textctrl(
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.CLK(clk40_i),
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.RESET(cpu_reset),
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.HSYNC(hsync_o),
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.VSYNC(vsync_o),
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.RED(red_o),
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.GREEN(green_o),
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.BLUE(blue_o),
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.CPU_CLK(clk40_i),
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.CPU_ADDR(cpu0_addr_o[11:0]),
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.CPU_OE_EN(cpu0_oe & video_en),
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.CPU_WR_EN(cpu0_we & video_en),
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.CPU_DATA_O(cpu0_data_out),
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.CPU_DATA_I(data_from_video)
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);
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endmodule
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endmodule
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