2ܾ CC3_top RE xo2c00 LCMXO2-7000HE TQFP144 4 IOBUSIDX:10 IOBUSIDX:11 IOBUSIDX:12 IOBUSIDX:13 IOBUSIDX:14 IOBUSIDX:15 IOBUSIDX:16 IOBUSIDX:17 IOBUSIDX:18 IOBUSIDX:22 IOBUSIDX:23 IOBUSIDX:24 IOBUSIDX:25 IOBUSIDX:26 IOBUSIDX:27 IOBUSIDX:28 IOBUSIDX:29
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2ܾ CC3_top R xo2c00 LCMXO2-7000HE TQFP144 4 IOBUSIDX:10 IOBUSIDX:11
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IOBUSIDX:3 IOBUSIDX:30 IOBUSIDX:31 IOBUSIDX:32 IOBUSIDX:33 IOBUSIDX:34 IOBUSIDX:35 IOBUSIDX:36 IOBUSIDX:37 IOBUSIDX:38 IOBUSIDX:39
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IOBUSIDX:12 IOBUSIDX:13 IOBUSIDX:14 IOBUSIDX:15 IOBUSIDX:16 IOBUSIDX:17 IOBUSIDX:18 IOBUSIDX:19 IOBUSIDX:20 IOBUSIDX:21 IOBUSIDX:25 IOBUSIDX:26 IOBUSIDX:27
IOBUSIDX:28 IOBUSIDX:29
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IOBUSIDX:4 IOBUSIDX:40 IOBUSIDX:41 IOBUSIDX:42 IOBUSIDX:43
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IOBUSIDX:3 IOBUSIDX:30
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IOBUSIDX:5
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IOBUSIDX:31 IOBUSIDX:32 IOBUSIDX:33 IOBUSIDX:34 IOBUSIDX:35 IOBUSIDX:36 IOBUSIDX:37 IOBUSIDX:38 IOBUSIDX:39
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IOBUSIDX:6
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IOBUSIDX:4 IOBUSIDX:40 IOBUSIDX:41 IOBUSIDX:42 IOBUSIDX:43 IOBUSIDX:44 IOBUSIDX:45 IOBUSIDX:46 IOBUSIDX:47 IOBUSIDX:48 IOBUSIDX:49
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IOBUSIDX:7
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IOBUSIDX:5 IOBUSIDX:50 IOBUSIDX:51 IOBUSIDX:52 IOBUSIDX:53 IOBUSIDX:54
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IOBUSIDX:8
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IOBUSIDX:6 IOBUSIDX:60 IOBUSIDX:61 IOBUSIDX:62 IOBUSIDX:63 IOBUSIDX:64 IOBUSIDX:65 IOBUSIDX:69
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IOBUSIDX:7 IOBUSIDX:70 IOBUSIDX:71 IOBUSIDX:72 IOBUSIDX:73 IOBUSIDX:74 IOBUSIDX:75 IOBUSIDX:76
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IOBUSIDX:9 IOBUSNAME:10 addr_o[15:0] IOBUSNAME:11 addr_o[15:0] IOBUSNAME:12 addr_o[15:0] IOBUSNAME:13 addr_o[15:0] IOBUSNAME:14 addr_o[15:0] IOBUSNAME:15 addr_o[15:0] IOBUSNAME:16 addr_o[15:0] IOBUSNAME:17 addr_o[15:0] IOBUSNAME:18 addr_o[15:0] IOBUSNAME:22 data_io[7:0] IOBUSNAME:23 data_io[7:0] IOBUSNAME:24 data_io[7:0] IOBUSNAME:25 data_io[7:0] IOBUSNAME:26 data_io[7:0] IOBUSNAME:27 data_io[7:0] IOBUSNAME:28 data_io[7:0] IOBUSNAME:29 data_io[7:0] IOBUSNAME:3 addr_o[15:0] IOBUSNAME:30 state_o[5:0] IOBUSNAME:31 state_o[5:0] IOBUSNAME:32 state_o[5:0] IOBUSNAME:33 state_o[5:0] IOBUSNAME:34 state_o[5:0] IOBUSNAME:35 state_o[5:0] IOBUSNAME:36 leds_o[7:0] IOBUSNAME:37 leds_o[7:0] IOBUSNAME:38 leds_o[7:0] IOBUSNAME:39 leds_o[7:0] IOBUSNAME:4 addr_o[15:0] IOBUSNAME:40 leds_o[7:0] IOBUSNAME:41 leds_o[7:0] IOBUSNAME:42 leds_o[7:0] IOBUSNAME:43 leds_o[7:0] IOBUSNAME:5 addr_o[15:0] IOBUSNAME:6 addr_o[15:0] IOBUSNAME:7 addr_o[15:0] IOBUSNAME:8 addr_o[15:0] IOBUSNAME:9 addr_o[15:0] Operating Condition
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IOBUSIDX:8
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COMMERCIAL PINNAME:0 clk40_i PINNAME:1 cpuclk_o
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IOBUSIDX:9 IOBUSNAME:10 addr_o[18:0] IOBUSNAME:11 addr_o[18:0] IOBUSNAME:12 addr_o[18:0] IOBUSNAME:13 addr_o[18:0] IOBUSNAME:14 addr_o[18:0] IOBUSNAME:15 addr_o[18:0] IOBUSNAME:16 addr_o[18:0] IOBUSNAME:17 addr_o[18:0] IOBUSNAME:18 addr_o[18:0] IOBUSNAME:19 addr_o[18:0] IOBUSNAME:20 addr_o[18:0] IOBUSNAME:21 addr_o[18:0] IOBUSNAME:25
data_io[15:0] IOBUSNAME:26
data_io[15:0] IOBUSNAME:27
data_io[15:0] IOBUSNAME:28
data_io[15:0] IOBUSNAME:29
data_io[15:0] IOBUSNAME:3 addr_o[18:0] IOBUSNAME:30
data_io[15:0] IOBUSNAME:31
data_io[15:0] IOBUSNAME:32
data_io[15:0] IOBUSNAME:33
data_io[15:0] IOBUSNAME:34
data_io[15:0] IOBUSNAME:35
data_io[15:0] IOBUSNAME:36
data_io[15:0] IOBUSNAME:37
data_io[15:0] IOBUSNAME:38
data_io[15:0] IOBUSNAME:39
data_io[15:0] IOBUSNAME:4 addr_o[18:0] IOBUSNAME:40
data_io[15:0] IOBUSNAME:41 state_o[5:0] IOBUSNAME:42 state_o[5:0] IOBUSNAME:43 state_o[5:0] IOBUSNAME:44 state_o[5:0] IOBUSNAME:45 state_o[5:0] IOBUSNAME:46 state_o[5:0] IOBUSNAME:47 leds_o[7:0] IOBUSNAME:48 leds_o[7:0] IOBUSNAME:49 leds_o[7:0] IOBUSNAME:5 addr_o[18:0] IOBUSNAME:50 leds_o[7:0] IOBUSNAME:51 leds_o[7:0] IOBUSNAME:52 leds_o[7:0] IOBUSNAME:53 leds_o[7:0] IOBUSNAME:54 leds_o[7:0] IOBUSNAME:6 addr_o[18:0] IOBUSNAME:60 laddr_o[5:0] IOBUSNAME:61 laddr_o[5:0] IOBUSNAME:62 laddr_o[5:0] IOBUSNAME:63 laddr_o[5:0] IOBUSNAME:64 laddr_o[5:0] IOBUSNAME:65 laddr_o[5:0] IOBUSNAME:69
ldata_io[7:0] IOBUSNAME:7 addr_o[18:0] IOBUSNAME:70
ldata_io[7:0] IOBUSNAME:71
ldata_io[7:0] IOBUSNAME:72
ldata_io[7:0] IOBUSNAME:73
ldata_io[7:0] IOBUSNAME:74
ldata_io[7:0] IOBUSNAME:75
ldata_io[7:0] IOBUSNAME:76
ldata_io[7:0] IOBUSNAME:8 addr_o[18:0] IOBUSNAME:9 addr_o[18:0] Operating Condition
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PINNAME:10 addr_o[15:0](8)
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COMMERCIAL PINNAME:0 clk40_i PINNAME:1 cpuclk_o
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PINNAME:11 addr_o[15:0](7)
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PINNAME:10 addr_o[18:0](11)
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PINNAME:12 addr_o[15:0](6)
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PINNAME:11 addr_o[18:0](10)
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PINNAME:13 addr_o[15:0](5)
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PINNAME:12 addr_o[18:0](9)
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PINNAME:14 addr_o[15:0](4)
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PINNAME:13 addr_o[18:0](8)
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PINNAME:15 addr_o[15:0](3)
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PINNAME:14 addr_o[18:0](7)
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PINNAME:16 addr_o[15:0](2)
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PINNAME:15 addr_o[18:0](6)
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PINNAME:17 addr_o[15:0](1)
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PINNAME:16 addr_o[18:0](5)
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PINNAME:18 addr_o[15:0](0)
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PINNAME:17 addr_o[18:0](4)
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PINNAME:19 oen_o PINNAME:2 reset_o
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PINNAME:18 addr_o[18:0](3)
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PINNAME:20 wen_o
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PINNAME:19 addr_o[18:0](2) PINNAME:2 reset_o
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PINNAME:21 cen_o
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PINNAME:20 addr_o[18:0](1)
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PINNAME:22 data_io[7:0](7)
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PINNAME:21 addr_o[18:0](0)
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PINNAME:23 data_io[7:0](6)
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PINNAME:22 oen_o
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PINNAME:24 data_io[7:0](5)
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PINNAME:23 wen_o
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PINNAME:25 data_io[7:0](4)
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PINNAME:24 cen_o
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PINNAME:26 data_io[7:0](3)
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PINNAME:25 data_io[15:0](15)
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PINNAME:27 data_io[7:0](2)
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PINNAME:26 data_io[15:0](14)
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PINNAME:28 data_io[7:0](1)
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PINNAME:27 data_io[15:0](13)
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PINNAME:29 data_io[7:0](0) PINNAME:3 addr_o[15:0](15)
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PINNAME:28 data_io[15:0](12)
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PINNAME:30 state_o[5:0](5)
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PINNAME:29 data_io[15:0](11) PINNAME:3 addr_o[18:0](18)
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PINNAME:31 state_o[5:0](4)
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PINNAME:30 data_io[15:0](10)
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PINNAME:32 state_o[5:0](3)
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PINNAME:31 data_io[15:0](9)
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PINNAME:33 state_o[5:0](2)
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PINNAME:32 data_io[15:0](8)
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PINNAME:34 state_o[5:0](1)
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PINNAME:33 data_io[15:0](7)
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PINNAME:35 state_o[5:0](0)
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PINNAME:34 data_io[15:0](6)
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PINNAME:36 leds_o[7:0](7)
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PINNAME:35 data_io[15:0](5)
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PINNAME:37 leds_o[7:0](6)
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PINNAME:36 data_io[15:0](4)
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PINNAME:38 leds_o[7:0](5)
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PINNAME:37 data_io[15:0](3)
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PINNAME:39 leds_o[7:0](4) PINNAME:4 addr_o[15:0](14)
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PINNAME:38 data_io[15:0](2)
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PINNAME:40 leds_o[7:0](3)
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PINNAME:39 data_io[15:0](1) PINNAME:4 addr_o[18:0](17)
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PINNAME:41 leds_o[7:0](2)
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PINNAME:40 data_io[15:0](0)
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PINNAME:42 leds_o[7:0](1)
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PINNAME:41 state_o[5:0](5)
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PINNAME:43 leds_o[7:0](0)
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PINNAME:42 state_o[5:0](4)
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PINNAME:44 hsync_o
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PINNAME:43 state_o[5:0](3)
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PINNAME:45 vsync_o
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PINNAME:44 state_o[5:0](2)
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PINNAME:46 red_o
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PINNAME:45 state_o[5:0](1)
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PINNAME:47 green_o
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PINNAME:46 state_o[5:0](0)
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PINNAME:48 blue_o PINNAME:5 addr_o[15:0](13) PINNAME:6 addr_o[15:0](12) PINNAME:7 addr_o[15:0](11) PINNAME:8 addr_o[15:0](10) PINNAME:9 addr_o[15:0](9) PINTYPE:0 IN PINTYPE:1 OUT
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PINNAME:47 leds_o[7:0](7)
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PINTYPE:10 OUT
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PINNAME:48 leds_o[7:0](6)
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PINTYPE:11 OUT
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PINNAME:49 leds_o[7:0](5) PINNAME:5 addr_o[18:0](16)
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PINTYPE:12 OUT
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PINNAME:50 leds_o[7:0](4)
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PINTYPE:13 OUT
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PINNAME:51 leds_o[7:0](3)
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PINTYPE:14 OUT
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PINNAME:52 leds_o[7:0](2)
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PINTYPE:15 OUT
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PINNAME:53 leds_o[7:0](1)
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PINTYPE:16 OUT
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PINNAME:54 leds_o[7:0](0)
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PINTYPE:17 OUT
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PINNAME:55 hsync_o
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PINTYPE:18 OUT
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PINNAME:56 vsync_o
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PINTYPE:19 OUT PINTYPE:2 OUT
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PINNAME:57 red_o
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PINTYPE:20 OUT
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PINNAME:58 green_o
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PINTYPE:21 OUT
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PINNAME:59 blue_o PINNAME:6 addr_o[18:0](15)
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PINTYPE:22 OUT
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PINNAME:60 laddr_o[5:0](5)
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PINTYPE:23 OUT
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PINNAME:61 laddr_o[5:0](4)
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PINTYPE:24 OUT
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PINNAME:62 laddr_o[5:0](3)
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PINTYPE:25 OUT
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PINNAME:63 laddr_o[5:0](2)
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PINTYPE:26 OUT
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PINNAME:64 laddr_o[5:0](1)
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PINTYPE:27 OUT
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PINNAME:65 laddr_o[5:0](0)
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PINTYPE:28 OUT
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PINNAME:66 loen_o
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PINTYPE:29 OUT PINTYPE:3 OUT
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PINNAME:67 lwen_o
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PINTYPE:30 OUT
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PINNAME:68 lcen_o
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PINTYPE:31 OUT
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PINNAME:69 ldata_io[7:0](7) PINNAME:7 addr_o[18:0](14)
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PINTYPE:32 OUT
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PINNAME:70 ldata_io[7:0](6)
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PINTYPE:33 OUT
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PINNAME:71 ldata_io[7:0](5)
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PINTYPE:34 OUT
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PINNAME:72 ldata_io[7:0](4)
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PINTYPE:35 OUT
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PINNAME:73 ldata_io[7:0](3)
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PINTYPE:36 OUT
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PINNAME:74 ldata_io[7:0](2)
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PINTYPE:37 OUT
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PINNAME:75 ldata_io[7:0](1)
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PINTYPE:38 OUT
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PINNAME:76 ldata_io[7:0](0) PINNAME:8 addr_o[18:0](13) PINNAME:9 addr_o[18:0](12) PINTYPE:0 IN PINTYPE:1 OUT
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PINTYPE:39 OUT PINTYPE:4 OUT
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PINTYPE:10 OUT
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PINTYPE:40 OUT
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PINTYPE:11 OUT
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PINTYPE:41 OUT
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PINTYPE:12 OUT
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PINTYPE:42 OUT
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PINTYPE:13 OUT
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PINTYPE:43 OUT
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PINTYPE:14 OUT
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PINTYPE:44 OUT
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PINTYPE:15 OUT
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PINTYPE:45 OUT
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PINTYPE:16 OUT
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PINTYPE:46 OUT
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PINTYPE:17 OUT
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PINTYPE:47 OUT
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PINTYPE:18 OUT
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PINTYPE:48 OUT PINTYPE:5 OUT PINTYPE:6 OUT PINTYPE:7 OUT PINTYPE:8 OUT PINTYPE:9 OUT parHoldDone q//
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PINTYPE:19 OUT PINTYPE:2 OUT
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TOP t Q S U X Y \ ]
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PINTYPE:20 OUT
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PINTYPE:21 OUT
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PINTYPE:22 OUT
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PINTYPE:23 OUT
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PINTYPE:24 OUT
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PINTYPE:25 BI
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PINTYPE:26 BI
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PINTYPE:27 BI
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PINTYPE:28 BI
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PINTYPE:29 BI PINTYPE:3 OUT
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PINTYPE:30 BI
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PINTYPE:31 BI
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PINTYPE:32 BI
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PINTYPE:33 BI
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PINTYPE:34 BI
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PINTYPE:35 BI
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PINTYPE:36 BI
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PINTYPE:37 BI
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PINTYPE:38 BI
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PINTYPE:39 BI PINTYPE:4 OUT
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PINTYPE:40 BI
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PINTYPE:41 OUT
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PINTYPE:42 OUT
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PINTYPE:43 OUT
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PINTYPE:44 OUT
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PINTYPE:45 OUT
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PINTYPE:46 OUT
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PINTYPE:47 OUT
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PINTYPE:48 OUT
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PINTYPE:49 OUT PINTYPE:5 OUT
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PINTYPE:50 OUT
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PINTYPE:51 OUT
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PINTYPE:52 OUT
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PINTYPE:53 OUT
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PINTYPE:54 OUT
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PINTYPE:55 OUT
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PINTYPE:56 OUT
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PINTYPE:57 OUT
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PINTYPE:58 OUT
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PINTYPE:59 OUT PINTYPE:6 OUT
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PINTYPE:60 OUT
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PINTYPE:61 OUT
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PINTYPE:62 OUT
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PINTYPE:63 OUT
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PINTYPE:64 OUT
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PINTYPE:65 OUT
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PINTYPE:66 OUT
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PINTYPE:67 OUT
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PINTYPE:68 OUT
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PINTYPE:69 OUT PINTYPE:7 OUT
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PINTYPE:70 OUT
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PINTYPE:71 OUT
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PINTYPE:72 OUT
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PINTYPE:73 OUT
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PINTYPE:74 OUT
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PINTYPE:75 OUT
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PINTYPE:76 OUT PINTYPE:8 OUT PINTYPE:9 OUT parHoldDone p// TOP P ` a b c d g h j z
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ textctrl
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O C D G H K L O P e f i w x y { | / 0 1 2 n o
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@
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A
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B
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C
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D
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E
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F
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G
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H
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I
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J
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K
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L
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M
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N
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O
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P
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R
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T
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U
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V
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yptr_5_s_6_0 yptr_5_cry_4_0 yptr_5_cry_2_0 yptr_5_cry_1_0 yptr_4_cry_7_0 yptr_4_cry_5_0 yptr_4_cry_3_0 yptr_4_cry_2_0
yptr_cry_10_0 yptr_cry_8_0 yptr_cry_6_0 yptr_cry_5_0 x_cnt[5] x_cnt[6] x_cnt_cry_0[5] x_cnt[3] x_cnt[4] x_cnt_cry_0[3] x_cnt[1] x_cnt[2] x_cnt_cry_0[1] x_cnt[0] x_cnt_cry_0[0] y_cnt[5] y_cnt[6] y_cnt_cry_0[5] y_cnt[3] y_cnt[4] y_cnt_cry_0[3] y_cnt[1] y_cnt[2] y_cnt_cry_0[1] y_cnt[0] y_cnt_cry_0[0] vsync_cnt[9]
vsync_cnt[10] vsync_cnt_cry_0[9] vsync_cnt[7] vsync_cnt[8] vsync_cnt_cry_0[7] vsync_cnt[5] vsync_cnt[6] vsync_cnt_cry_0[5] vsync_cnt[3] vsync_cnt[4] vsync_cnt_cry_0[3] vsync_cnt[1] vsync_cnt[2] vsync_cnt_cry_0[1] vsync_cnt[0] vsync_cnt_cry_0[0] blink_cnt[5] blink_cnt_s_0[5] blink_cnt[3] blink_cnt[4] blink_cnt_cry_0[3] blink_cnt[1] blink_cnt[2] blink_cnt_cry_0[1] blink_cnt[0] blink_cnt_cry_0[0] hsync_cnt[9]
hsync_cnt[10] hsync_cnt_cry_0[9] hsync_cnt[7] hsync_cnt[8] hsync_cnt_cry_0[7] hsync_cnt[5] hsync_cnt[6] hsync_cnt_cry_0[5] hsync_cnt[3] hsync_cnt[4] hsync_cnt_cry_0[3] hsync_cnt[1] hsync_cnt[2] hsync_cnt_cry_0[1] hsync_cnt[0] hsync_cnt_cry_0[0] cpu0 Q R 8 9 : ; < = > ? @ A B C D E F G H J K L O P S T W X [ \ _ ` c d g h ! $ % ( ) , - 0 1 2 3 4 5 6 7 8 9 : < = > ? B E F I J M N Q R U W X Z [ ] ` a d e h k n q t w z } A C D F G I J L M O P R S U V X Y [ ^ m n o q r u v & ' h l ~ B P T ^ b d n p |
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* , 4 6 S T d e f
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! " $ + , ! " # $ % & ' ( ) [ d e g s u
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>
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?
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Q
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S
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m
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textctrl
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P S T V W Z [ j k l o p s t w x { |
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un1_k_cpu_addr_1_cry_0_0 P regs P S ] ^ ` a c d f g i j l m o p r s v w x y z { | } ~ N Z ~
/ @ _ ~
|
k
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = @ s " $ & ( * , . 0 2 4 6 8 : < > @ B D F H J L N P R T V X Z \ ^ ` b d f h j l n p r t v x z | ~ $ % ( ) 6 ^ p : h . 0 2 8 : < > @ B D F H N O P Q R U V W X Y Z [ \ ] ^ _ ` a b c g h i j k l m n o p q r s t u v w x y z { | } ~
# % & ' ( ) * - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ * + O P R h i
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l yptr_5_s_6_0 yptr_5_cry_4_0 yptr_5_cry_2_0 yptr_5_cry_1_0 yptr_4_cry_7_0 yptr_4_cry_5_0 yptr_4_cry_3_0 yptr_4_cry_2_0
yptr_cry_10_0 yptr_cry_8_0 yptr_cry_6_0 yptr_cry_5_0 x_cnt[5] x_cnt[6] x_cnt_cry_0[5] x_cnt[3] x_cnt[4] x_cnt_cry_0[3] x_cnt[1] x_cnt[2] x_cnt_cry_0[1] x_cnt[0] x_cnt_cry_0[0] y_cnt[5] y_cnt[6] y_cnt_cry_0[5] y_cnt[3] y_cnt[4] y_cnt_cry_0[3] y_cnt[1] y_cnt[2] y_cnt_cry_0[1] y_cnt[0] y_cnt_cry_0[0] vsync_cnt[9]
vsync_cnt[10] vsync_cnt_cry_0[9] vsync_cnt[7] vsync_cnt[8] vsync_cnt_cry_0[7] vsync_cnt[5] vsync_cnt[6] vsync_cnt_cry_0[5] vsync_cnt[3] vsync_cnt[4] vsync_cnt_cry_0[3] vsync_cnt[1] vsync_cnt[2] vsync_cnt_cry_0[1] vsync_cnt[0] vsync_cnt_cry_0[0] blink_cnt[5] blink_cnt_s_0[5] blink_cnt[3] blink_cnt[4] blink_cnt_cry_0[3] blink_cnt[1] blink_cnt[2] blink_cnt_cry_0[1] blink_cnt[0] blink_cnt_cry_0[0] hsync_cnt[9]
hsync_cnt[10] hsync_cnt_cry_0[9] hsync_cnt[7] hsync_cnt[8] hsync_cnt_cry_0[7] hsync_cnt[5] hsync_cnt[6] hsync_cnt_cry_0[5] hsync_cnt[3] hsync_cnt[4] hsync_cnt_cry_0[3] hsync_cnt[1] hsync_cnt[2] hsync_cnt_cry_0[1]
chars_data[0] hsync_cnt[0] hsync_cnt_cry_0[0] cpu0 R S + , - . / 0 1 2 5 6 9 : = > A B E F I J M N Q R ` q u
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# $ ' ( + . 1 4 5 8 9 < ? B E O R U W Y \ _ b c f g j k n o r s v w 5 7 8 : ; = > @ A C D F G I J L O R ` a d e h i ) z { e b c p q
I O S !
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}
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~ un1_k_cpu_addr_1_cry_0_0 Q regs Q T p q r s t u v w x y z { | } ~ ] r y
, 2 3 6 7 M ` a h | } ~
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" # % & ( ) + , . / 1 2 4 M N T
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" $ & ( * , . 0 2 4 6 8 : < > @ B D F H J L N P R T V X Z \ ^ ` b d f h j l n p r t v x z | ~ # % 7 W g h i j k l m n o p q r s t u v w x y | } ~ ' - 1 5 7 M W Y a k y { }
/ 7 C I K [ ^ _ ` a d e f g h j k l m n o r s t u v w x y z { | } ~
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! " # $ % & ( ) * , - . / 0 1 2 4 6 8 : < > @ B D E F G H J L M N P R T 1 ; j k l m n o p q r s t u v w x y z { | } ~
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o
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j
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m
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{
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| ea S U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o 8 < C G K x } N x d e f A C ! " # $ % & ' ( ) * + , - . 0 1 2 3 4 5 6 8 9 : ; < = > ? @ B D E F H J L M N P Q R S T U V W X Y Z \ ' 7 < > @ B C D E F G H I J K L N P Q R T U V X Z [ \ ] ^ _ ` a b c d e f g h
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s
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t
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x
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z eamem_addr_o_s_15_0 T eamem_addr_o_cry_13_0 T eamem_addr_o_cry_11_0 T eamem_addr_o_cry_9_0 T eamem_addr_o_cry_7_0 T eamem_addr_o_cry_5_0 T eamem_addr_o_cry_3_0 T eamem_addr_o_cry_1_0 T eamem_addr_o_cry_0_0 T ea_reg_post_o_s_15_0 T ea_reg_post_o_cry_13_0 T ea_reg_post_o_cry_11_0 T ea_reg_post_o_cry_9_0 T ea_reg_post_o_cry_7_0 T ea_reg_post_o_cry_5_0 T ea_reg_post_o_cry_3_0 T ea_reg_post_o_cry_1_0 T ea_reg_post_o_cry_0_0 T k_new_pc_4_s_15_0 T k_new_pc_4_cry_13_0 T k_new_pc_4_cry_11_0 T k_new_pc_4_cry_9_0 T k_new_pc_4_cry_7_0 T k_new_pc_4_cry_5_0 T k_new_pc_4_cry_3_0 T k_new_pc_4_cry_1_0 T k_new_pc_4_cry_0_0 T SU[14] S SU[15] S SU_cry_0[14] S SU[12] S SU[13] S SU_cry_0[12] S SU[10] S SU[11] S SU_cry_0[10] S SU[8] S SU[9] S SU_cry_0[8] S SU[6] S SU[7] S SU_cry_0[6] S SU[4] S SU[5] S SU_cry_0[4] S SU[2] S SU[3] S SU_cry_0[2] S SU[0] S SU[1] S SU_cry_0[0] S SU_lcry_0 S SS[14] S SS[15] S SS_cry_0[14] S SS[12] S SS[13] S SS_cry_0[12] S SS[10] S SS[11] S SS_cry_0[10] S SS[8] S SS[9] S SS_cry_0[8] S SS[6] S SS[7] S SS_cry_0[6] S SS[4] S SS[5] S SS_cry_0[4] S SS[2] S SS[3] S SS_cry_0[2] S SS[0] S SS[1] S SS_cry_0[0] S SS_lcry_0 S right_s_15_0 S right_cry_13_0 S right_cry_11_0 S
right_cry_9_0 S
right_cry_7_0 S
right_cry_5_0 S
right_cry_3_0 S
right_cry_1_0 S
right_cry_0_0 S alu Q Y 4 ; H O P z { ~ z {
% G O ' 7 ; ? w ? M S W
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V
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w alu16 K y q A W Y [ ] _ a c e g r s t u v x y z { | } ~ A
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c
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u a16 P y z } ~ V X Z \ ^ ` b d f
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ea R T U V W X Y Z [ \ _ b e h k n q t u I V Y a e j m " # & ' * l
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@ un8_q_out_cry_15_0 un8_q_out_cry_13_0 un8_q_out_cry_11_0 un8_q_out_cry_9_0 un8_q_out_cry_7_0 un8_q_out_cry_5_0 un8_q_out_cry_3_0 un8_q_out_cry_1_0 un8_q_out_cry_0_0 q_out_1_cry_15_0 q_out_1_cry_13_0 q_out_1_cry_11_0 q_out_1_cry_9_0 q_out_1_cry_7_0 q_out_1_cry_5_0 q_out_1_cry_3_0 q_out_1_cry_1_0 q_out_1_cry_0_0 q_out_2_cry_15_0 q_out_2_cry_13_0 q_out_2_cry_11_0 q_out_2_cry_9_0 q_out_2_cry_7_0 q_out_2_cry_5_0 q_out_2_cry_3_0 q_out_2_cry_1_0 q_out_2_cry_0_0 q_out_1_0_cry_15_0 q_out_1_0_cry_13_0 q_out_1_0_cry_11_0 q_out_1_0_cry_9_0 q_out_1_0_cry_7_0 q_out_1_0_cry_5_0 q_out_1_0_cry_3_0 q_out_1_0_cry_1_0 q_out_1_0_cry_0_0 mulu
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V W Z [ \ ^ _ b c d e f g i j k l m n o p s t w : = @ C F G H I J L V u v ! I w i + Q h i j k l m n o p q
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A
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C
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E
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eamem_addr_o_s_15_0 S eamem_addr_o_cry_13_0 S eamem_addr_o_cry_11_0 S eamem_addr_o_cry_9_0 S eamem_addr_o_cry_7_0 S eamem_addr_o_cry_5_0 S eamem_addr_o_cry_3_0 S eamem_addr_o_cry_1_0 S eamem_addr_o_cry_0_0 S IY_pipe_3 R
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G
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IY_pipe_15 R ea_reg_post_o_s_15_0 S
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I
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IY_pipe_13 R IY_pipe_8 R ea_reg_post_o_cry_13_0 S
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K
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IY_pipe_23 R
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M
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IY_pipe_18 R ea_reg_post_o_cry_11_0 S
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O
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IY_pipe_33 R
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Q
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IY_pipe_28 R ea_reg_post_o_cry_9_0 S
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S
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IY_pipe_43 R
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T
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IY_pipe_38 R ea_reg_post_o_cry_7_0 S
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e
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IY_pipe_53 R
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f
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IY_pipe_48 R ea_reg_post_o_cry_5_0 S
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i pipe1_1_6_cry_8_0 Ҁ pipe1_1_6_cry_7_0 Ҁ pipe1_1_6_cry_5_0 Ҁ pipe1_1_6_cry_3_0 Ҁ pipe1_1_6_cry_1_0 Ҁ pipe1_1_6_cry_0_0 Ҁ pipe1[15] Ҁ pipe1[0] Ҁ pipe1_1_s_15_0 Ҁ pipe1[13] Ҁ pipe1[14] Ҁ pipe1_1_cry_13_0 Ҁ pipe1[11] Ҁ pipe1[12] Ҁ pipe1_1_cry_11_0 Ҁ pipe1[9] Ҁ pipe1[10] Ҁ pipe1_1_cry_9_0 Ҁ pipe1[7] Ҁ pipe1[8] Ҁ pipe1_1_cry_7_0 Ҁ pipe1[5] Ҁ pipe1[6] Ҁ pipe1_1_cry_5_0 Ҁ pipe1[3] Ҁ pipe1[4] Ҁ pipe1_1_cry_3_0 Ҁ pipe1[1] Ҁ pipe1[2] Ҁ pipe1_1_cry_1_0 Ҁ pipe1_1_cry_0_0 Ҁ pipe1_1_4_cry_8_0 Ҁ pipe1_1_4_cry_6_0 Ҁ pipe1_1_4_cry_4_0 Ҁ pipe1_1_4_cry_2_0 Ҁ pipe1_1_4_cry_1_0 Ҁ pipe0_1_4_cry_8_0 Ҁ pipe0_1_4_cry_6_0 Ҁ pipe0_1_4_cry_4_0 Ҁ pipe0_1_4_cry_2_0 Ҁ pipe0_1_4_cry_1_0 Ҁ pipe0_1_5_cry_8_0 Ҁ pipe0_1_5_cry_6_0 Ҁ pipe0_1_5_cry_4_0 Ҁ pipe0_1_5_cry_2_0 Ҁ pipe0_1_5_cry_1_0 Ҁ pipe0[11] Ҁ pipe0_1_s_11_0 Ҁ pipe0[9] Ҁ pipe0[10] Ҁ pipe0_1_cry_9_0 Ҁ pipe0[7] Ҁ pipe0[8] Ҁ pipe0_1_cry_7_0 Ҁ pipe0[5] Ҁ pipe0[6] Ҁ pipe0_1_cry_5_0 Ҁ pipe0[3] Ҁ pipe0[4] Ҁ pipe0_1_cry_3_0 Ҁ pipe0_1_cry_2_0 Ҁ alu8 u & ' ( ) * 3 7 ? @ L | m n r i ] 3 5 9 = A U = O Y i
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IY_pipe_63 R
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IY_pipe_58 R ea_reg_post_o_cry_3_0 S
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L
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IY_pipe_73 R
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W
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IY_pipe_68 R ea_reg_post_o_cry_1_0 S ea_reg_post_o_cry_0_0 S SU[14] R SU[15] R SU_cry_0[14] R SU[12] R SU[13] R SU_cry_0[12] R SU[10] R SU[11] R SU_cry_0[10] R SU[8] R SU[9] R SU_cry_0[8] R SU[6] R SU[7] R SU_cry_0[6] R SU[4] R SU[5] R SU_cry_0[4] R SU[2] R SU[3] R SU_cry_0[2] R SU[0] R SU[1] R SU_cry_0[0] R SU_lcry_0 R SS[14] R SS[15] R SS_cry_0[14] R SS[12] R SS[13] R SS_cry_0[12] R SS[10] R SS[11] R SS_cry_0[10] R SS[8] R SS[9] R SS_cry_0[8] R SS[6] R SS[7] R SS_cry_0[6] R SS[4] R SS[5] R SS_cry_0[4] R SS[2] R SS[3] R SS_cry_0[2] R SS[0] R SS[1] R SS_cry_0[0] R SS_lcry_0 R PC_pipe_2 R
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X
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PC_pipe_18 R right_s_15_0 R
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Y
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PC_pipe_12 R PC_pipe_7 R right_cry_13_0 R
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[
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PC_pipe_22 R
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]
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PC_pipe_17 R right_cry_11_0 R
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_
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PC_pipe_32 R
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a
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PC_pipe_27 R
right_cry_9_0 R eflag_pipe_3 R eflag_pipe_2 R
right_cry_7_0 R hflag_pipe_2 R fflag_pipe_2 R
right_cry_5_0 R
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b a8 ; ! " # $ % D C
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nff_pipe_2 R intff_pipe_2 R
right_cry_3_0 R
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vff_pipe_2 R
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zff_pipe_2 R
right_cry_1_0 R
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$
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cff_pipe_2 R
right_cry_0_0 R alu P N ' H b j l m
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&
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(
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alu16 h A \ \ v x " $ & J L 9 Z \ ]
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*
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2
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4
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4
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6
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8
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c
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a16 X | 6 7
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D
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F
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H
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J
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*
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N
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,
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R
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U un8_q_out_cry_7_0 un8_q_out_cry_5_0 un8_q_out_cry_3_0 un8_q_out_cry_1_0 un8_q_out_cry_0_0 q_out_1_cry_7_0 q_out_1_cry_5_0 q_out_1_cry_3_0 q_out_1_cry_1_0 q_out_1_cry_0_0 q_out_2_cry_7_0 q_out_2_cry_5_0 q_out_2_cry_3_0 q_out_2_cry_1_0 q_out_2_cry_0_0 q_out_1_0_cry_7_0 q_out_1_0_cry_5_0 q_out_1_0_cry_3_0 q_out_1_0_cry_1_0 q_out_1_0_cry_0_0 neg8_w_s_7_0 neg8_w_cry_5_0 neg8_w_cry_3_0 neg8_w_cry_1_0 neg8_w_cry_0_0 un1_k_cpu_addr_1_s_15_0 Q un1_k_cpu_addr_1_cry_13_0 Q un1_k_cpu_addr_1_cry_11_0 Q un1_k_cpu_addr_1_cry_9_0 Q un1_k_cpu_addr_1_cry_7_0 Q un1_k_cpu_addr_1_cry_5_0 Q un1_k_cpu_addr_1_cry_3_0 Q un1_k_cpu_addr_1_cry_1_0 Q k_cpu_addr_28_iv[0] k_cpu_addr_28_iv[1]
k_cpu_addr[0] Q
k_cpu_addr[1] Q k_cpu_addr_28_iv[2] k_cpu_addr_28_iv[3] T
k_cpu_addr[2] Q
k_cpu_addr[3] Q k_cpu_addr_28_iv[4] k_cpu_addr_28_iv[5] T
k_cpu_addr[4] Q
k_cpu_addr[5] Q k_cpu_addr_28_iv[6] k_cpu_addr_28_iv[7]
k_cpu_addr[6] Q
k_cpu_addr[7] Q k_cpu_addr_28_iv[8] T k_cpu_addr_28_iv[9]
k_cpu_addr[8] Q
k_cpu_addr[9] Q k_cpu_addr_28_iv[10] T k_cpu_addr_28_iv[11] k_cpu_addr[10] Q k_cpu_addr[11] Q k_cpu_addr_28_iv[12] T k_cpu_addr_28_iv[13] k_cpu_addr[12] Q k_cpu_addr[13] Q k_cpu_addr_28_iv[14] k_cpu_addr_28_iv[15] k_cpu_addr[14] Q k_cpu_addr[15] Q cpu0_data_in_1_0_0_a2[0] chars U X Y ! " % & textmem4k_0_0_3_RNIEU4M1 T k_pp_regs_pipe_15 Ҁ k_pp_regs_pipe_17 Ҁ textmem4k_0_1_2_RNIE06M1 T textmem4k_0_1_2_RNIE06M1_0 T k_pp_regs_pipe_19 Ҁ k_pp_regs_pipe_21 Ҁ k_pp_regs_cnsts2 Ҁ un1_state_27 S k_pp_regs_pipe_14 Ҁ k_pp_regs_pipe_RNO Ҁ dec_op Q a - / 0 K d e l m p t u P Q " $ & ( * , . / 0 1 2 3 4 5 6 8 9 : ; < = > ? @ B C D E
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" $ & ( ) * + , . 0 2 4 6 8 : < > ? @ B D F H J K L N O P Q R S T U V X Z [ \ ^ ` b c d f g h j l n p r t v x z | ~ K % ( * + un1_k_pp_regs_7_sqmuxa ` k_pp_regs_pipe Ҁ k_pp_regs_pipe_8_RNO Ҁ k_pp_regs_5_sqmuxa_RNILBF43 Ҁ k_pp_regs_pipe_8 Ҁ k_pp_regs_pipe_10 Ҁ k_pp_regs_25[2] h GATE g k_pp_regs_pipe_9 Ҁ un6_pipe0[0] Ҁ pipe0_1_4_axb_1 Ҁ pipe0[0] Ҁ pipe0[1] Ҁ
pipe0_1_axb_2 Ҁ
pipe1_1_6_0_a Ҁ pipe0[2] Ҁ k_pp_regs_cnst_sn.m9 Q un1_state_83_i_o4_0 S k_pp_regs_pipe_1 Ҁ un1_state_12_1_RNIIENC1 Ҁ dec_regs Q v ) * P Q S T Z [ ] ^ i q ^ _ b c f g ! ' + - A F G H I J K L M N O P Q R S T U V X Y Z [ \ ] ^ _ ` a b c # / 3 9 ; = E G ] _ m o q s u
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# ) , - . / 0 2 3 4 5 6 8 9 :
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g
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h k_new_pc29_0_o2_0_RNI939S3 u k_pp_regs_pipe_16 Ҁ eamem_addr_o_axb_0_RNI78HM1 T path_left_data_RNICONT1[1] S ra_in[0] ra_in[1] "datamux_o_alu_in_left_path_data[2] eamem_addr_o_cry_3_0_RNII0QT1 T ra_in[2] ra_in[3] eamem_addr_o_cry_3_0_RNIK2QT1 T eamem_addr_o_cry_5_0_RNIO8ST1 T ra_in[4] ra_in[5] "datamux_o_alu_in_left_path_data[6] eamem_addr_o_cry_7_0_RNIUGUT1 T ra_in[6] ra_in[7] "datamux_o_alu_in_left_path_data[8] T GATE ra_in[8] "datamux_o_alu_in_left_path_data[9] GATE ra_in[9] #datamux_o_alu_in_left_path_data[10] T GATE ra_in[10] #datamux_o_alu_in_left_path_data[11] GATE ra_in[11] #datamux_o_alu_in_left_path_data[12] S GATE ra_in[12] #datamux_o_alu_in_left_path_data[13] S GATE ra_in[13] #datamux_o_alu_in_left_path_data[14] GATE ra_in[14] #datamux_o_alu_in_left_path_data[15] GATE ra_in[15] #datamux_o_alu_in_right_path_data[0] u #datamux_o_alu_in_right_path_data[1] S rb_in[0] rb_in[1] #datamux_o_alu_in_right_path_data[2] #datamux_o_alu_in_right_path_data[3] T rb_in[2] rb_in[3] #datamux_o_alu_in_right_path_data[4] S #datamux_o_alu_in_right_path_data[7] S rb_in[4] rb_in[7] #datamux_o_alu_in_right_path_data[8] S GATE rb_in[8] #datamux_o_alu_in_right_path_data[9] GATE rb_in[9] $datamux_o_alu_in_right_path_data[10] GATE rb_in[10] $datamux_o_alu_in_right_path_data[11] S GATE rb_in[11] $datamux_o_alu_in_right_path_data[12] S GATE rb_in[12] $datamux_o_alu_in_right_path_data[13] S GATE rb_in[13] $datamux_o_alu_in_right_path_data[14] GATE rb_in[14] $datamux_o_alu_in_right_path_data[15] GATE rb_in[15] dec_alu Q 9 " $ alu_opcode_1_f0[0] Ā alu_opcode_1_f0[1] Ā rop_in[0] rop_in[1] alu_opcode_1_f0[2] Ā alu_opcode_1_f0[3] Ā rop_in[2] rop_in[3] alu_opcode_4_m[4] Ā un3_dest_flags_2 Ā rop_in[4]
dest_reg_3[0] u GATE Ѐ
dest_reg_o[0] u
dest_reg_3[1] u GATE Ӏ
dest_reg_o[1] u
dest_reg_3[2] u GATE ր
dest_reg_o[2] u
dest_reg_3[3] u GATE ـ
dest_reg_o[3] u path_left_addr_1[0] u GATE ܀ path_left_addr_o[0] u path_left_addr_1[1] u GATE ߀ path_left_addr_o[1] u path_left_addr_1[2] u GATE path_left_addr_o[2] u path_left_addr_1[3] u GATE path_left_addr_o[3] u path_right_addr[0] u GATE path_right_addr_o[0] u path_right_addr_0[1] u path_right_addr_0[2] u path_right_addr_o[1] u path_right_addr_o[2] u path_right_addr[3] u GATE path_right_addr_o[3] u k_clear_e_3 S
k_clear_e_3_3 u k_clear_e Q k_cpu_we_3_1 ` un1_state_40 ` k_dec_su Q N_1918_i T N_1935_i k_eahi[0] Q k_eahi[1] Q N_1952_i T N_1969_i k_eahi[2] Q k_eahi[3] Q N_1986_i T N_2003_i k_eahi[4] Q k_eahi[5] Q N_2020_i T N_2037_i k_eahi[6] Q k_eahi[7] Q k_ealo_9_6_606 S k_ealo_9_5_627 ` k_ealo[0] Q k_ealo[1] Q N_1797_i Ҁ k_ealo_9_3_674 S k_ealo[2] Q k_ealo[3] Q N_1835_i S N_1849_i S k_ealo[4] Q k_ealo[5] Q N_1863_i S N_1877_i S k_ealo[6] Q k_ealo[7] Q k_forced_mem_size_2_iv_i S un1_state_48_0_a2 S k_forced_mem_size Q
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k_inc_pc_3 T un1_state_29 ` k_inc_pc Q
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k_inc_su_5 ` un1_state_50 ` k_inc_su Q textmem4k_0_2_1_RNIE48M1 T textmem4k_0_2_1_RNIE48M1_0 T k_ind_ea[4] Q k_ind_ea[5] Q textmem4k_0_3_0_RNIE69M1 T textmem4k_0_3_0_RNIE69M1_0 T k_ind_ea[6] Q k_ind_ea[7] Q state_7_sqmuxa_1_RNI1JN92 u state_7_sqmuxa_1 u k_mul_cnt Q k_p2_valid_3_f0 S k_p2_valid6 `
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k_p2_valid Q k_p3_valid_3_f0 ` k_p2_valid7 `
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k_p3_valid Q k_pp_active_reg_7[0] S k_pp_active_reg_7[1] S k_pp_active_reg[0] Q k_pp_active_reg[1] Q k_pp_active_reg_7[2] S k_pp_active_reg_cnst_0[3] S k_pp_active_reg[2] Q k_pp_active_reg[3] Q k_pp_regs_25[4] ; GATE : k_pp_regs[4] Q k_pp_regs_25[5] > GATE = k_pp_regs[5] Q k_pp_regs_25[6] A GATE @ k_pp_regs[6] Q k_pp_regs_25[7] D GATE C k_pp_regs[7] Q k_pp_regs_6_sqmuxa_1_1_RNI6UDNC Ҁ k_pp_regs_pipe_3_RNO Ҁ k_pp_regs_pipe_2 Ҁ k_pp_regs_pipe_3 Ҁ k_pp_regs_pipe_11_RNO Ҁ un1_k_pp_regs_6_i_a2 ` k_pp_regs_pipe_11 Ҁ k_set_e_3 S un1_state_9 T k_set_e Q k_write_dest_5 u un1_state_50_1_i_o2_RNIQ1O21 u k_write_dest Q k_write_exg_1_sqmuxa u k_write_exg_1_sqmuxa_RNO u k_write_exg Q k_write_pc_6 Ҁ test_cond Q X
cond_taken_17 W
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k_write_pc Q k_write_post_incdec_7 u k_write_post_incdec_7_1 u k_write_post_incdec Q k_write_tfr_1_sqmuxa u k_write_tfr_1_sqmuxa_RNO u k_write_tfr Q un1_state_104_1_o7_RNI48N01 S N_1890_i S next_mem_state[0] Q next_mem_state[3] Q un1_state_33_RNIELC85 ` un1_state_32 ` next_mem_state[4] Q next_mem_state[5] Q N_1559_i S k_clear_e_3_3_RNIH0VI u next_push_state[1] Q next_push_state[2] Q next_state_10[0] ` next_state_10[1] `
next_state[0] Q
next_state[1] Q next_state_10[2] ` un1_state_7_2_i_o2_RNIJDTFB u
next_state[2] Q
next_state[3] Q next_state_cnst_0_a2[4] ` next_state_10[5] `
next_state[4] Q
next_state[5] Q #datamux_o_alu_in_right_path_data[5] T #datamux_o_alu_in_right_path_data[6] rb_in[5] rb_in[6] ACCA_RNO[0] S ACCA_RNO[1] S ACCA[0] S ACCA[1] S ACCA_RNO[2] S ACCA_RNO[3] S ACCA[2] S ACCA[3] S ACCA_RNO[4] S ACCA_RNO[5] S ACCA[4] S ACCA[5] S ACCA_RNO[6] S ACCA_RNO[7] S ACCA[6] S ACCA[7] S ACCB_9[0] S ACCB_9[1] S ACCB[0] S ACCB[1] S ACCB_9[2] S ACCB_9[3] S ACCB[2] S ACCB[3] S ACCB_9[4] S ACCB_9[5] S ACCB[4] S ACCB[5] S ACCB_9[6] S ACCB_9[7] S ACCB[6] S ACCB[7] S IX_10[0] S IX_10[1] S IX[0] S IX[1] S IX_10[2] S IX_10[3] S IX[2] S IX[3] S IX_10[4] S IX_10[5] S IX[4] S IX[5] S IX_10[6] S IX_10[7] S IX[6] S IX[7] S IX_10[8] S IX_10[9] S IX[8] S IX[9] S IX_10[10] S IX_10[11] S IX[10] S IX[11] S IX_10[12] S IX_10[13] S IX[12] S IX[13] S IX_10[14] S IX_10[15] S IX[14] S IX[15] S IY_10[0] S IY_10[1] S IY[0] S IY[1] S IY_10[2] S IY_10[3] S IY[2] S IY[3] S IY_10[4] S IY_10[5] S IY[4] S IY[5] S IY_10[6] S IY_10[7] S IY[6] S IY[7] S IY_10[8] S IY_10[9] S IY[8] S IY[9] S IY_10[10] S IY_10[11] S IY[10] S IY[11] S IY_10[12] S IY_10[13] S IY[12] S IY[13] S IY_10[14] S IY_10[15] S IY[14] S IY[15] S fflag_9_u S GATE ܀ fflag S DP_7[0] S DP_7[2] S DP[0] S DP[2] S DP_7[4] S path_left_data_RNIFUG11[4] S DP[4] S PC_9[3] S GATE PC[3] S PC_9[5] S GATE PC[5] S PC_9[8] S GATE PC[8] S PC_9[10] S GATE PC[10] S PC_9[12] S GATE PC[12] S cff_9_u S GATE cff S vff_9_u S GATE vff S zff_9_u S GATE zff S nff_9_u S GATE nff S intff_9_u S GATE intff S hflag_9_u S GATE hflag S eflag_11 S eflag S DP_7[1] S DP_7[3] S DP[1] S DP[3] S DP_7[5] S DP_7[6] S DP[5] S DP[6] S DP_7[7] S path_left_data_RNIOEVA1[7] S DP[7] S PC_9[0] S PC_9_0[0] S PC[0] S PC_9[1] S GATE PC[1] S PC_9[2] S GATE PC[2] S PC_9[4] S GATE PC[4] S PC_9[6] S ! GATE PC[6] S PC_9[7] S $ GATE # PC[7] S PC_9[9] S ' GATE & PC[9] S PC_9[11] S * GATE ) PC[11] S PC_9[13] S - GATE , PC[13] S PC_9[14] S 0 GATE / PC[14] S PC_9[15] S 3 GATE 2 PC[15] S k_cpu_data_o_7[0] Q 6 GATE 5 k_cpu_data_o[0] Q k_cpu_data_o_7[1] Q 9 GATE 8 k_cpu_data_o[1] Q k_cpu_data_o_7[2] Q < GATE ; k_cpu_data_o[2] Q k_cpu_data_o_7[3] Q ? GATE > k_cpu_data_o[3] Q k_cpu_data_o_7[4] Q B GATE A k_cpu_data_o[4] Q k_cpu_data_o_7[5] Q E GATE D k_cpu_data_o[5] Q k_cpu_data_o_7[6] Q H GATE G k_cpu_data_o[6] Q k_cpu_data_o_7[7] Q K GATE J k_cpu_data_o[7] Q
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k_cpu_oe_3 S un1_state_17_0 S k_cpu_oe Q
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k_cpu_we_3 ` k_cpu_we_3_RNO ` k_cpu_we Q cpu_clk_RNI1SG4 PC_1_sqmuxa_2_RNIDL992 S cpu_clk N_38_i SUM1_0_x2 reset_cnt[0] reset_cnt[1] N_90_i_i SUM3_0 reset_cnt[2] reset_cnt[3] state_32_iv[0] u state_32_iv[1] u state[0] Q state[1] Q state_32_0_iv[2] u state_32_0_iv[3] u state[2] Q state[3] Q state_cnst_i_8_RNI9EVN2[4] u state_32_iv_i[5] u state[4] Q state[5] Q bluer_RNO[0] redr_4_i_0_a3[0] bluer[0] cneg8_r_5 CCRo_bm_1[2]
chars_data[2]
chars_data[3] c16_u CCRo_4_3[2]
chars_data[4]
chars_data[5] k_pp_regs_25_4[0] Ҁ
pipe0_1_5_1_a Ҁ
chars_data[6]
chars_data[7] un8_q_out_cry_9_0_RNO un8_q_out_cry_7_0_RNO font_data[0] font_data[1] un8_q_out_cry_11_0_RNO un8_q_out_cry_9_0_RNO_0 font_data[2] font_data[3] un8_q_out_cry_13_0_RNO un8_q_out_cry_11_0_RNO_0 font_data[4] font_data[5]
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un1_pc[14] T path_right_data_0[3] S font_data[6] font_data[7] line_cnt_n0_i_a3 line_cnt_RNO[1] line_cnt[0] line_cnt[1] line_cnt_RNO[2] line_cnt_RNO[3] line_cnt[2] line_cnt[3] shift_RNO[0] shift_7_i_m2[1] shift[0] shift[1] shift_7_i_m2[2] shift_7_i_m2[3] shift[2] shift[3] shift_7_i_m2[4] shift_7_i_m2[5] shift[4] shift[5] shift_7_i_m2[6] shift_7_i_m2[7] shift[6] shift[7]
cond_taken_13 W path_left_addr14 u tshift[0] tshift[1] yptr_4_axb_2 un6_visiblelto10_0_o2_1 tshift[2] tshift[3] redr9_9
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un5_RED[0] tshift[4] tshift[5] un1_data_io_i_o2 shift_7_0_o2[0] tshift[6] tshift[7] visible_RNO bluerc_4 visible cond_taken_15_0 W GATE cond_taken_8 W GATE alu_opcode_2_4_0_.m20 GATE alu_opcode_2_4_0_.m60 GATE alu_opcode_2_4_0_.m30 GATE alu_opcode_2_4_0_.m41 GATE alu_opcode_2_4_0_.m9 GATE alu_opcode_2_4_0_.m47 GATE alu_opcode_2_4_0_.m54 GATE Ā alu_opcode_2_4_0_.m33 GATE ƀ un1_mode93_RNIC8563 ` GATE Ȁ un1_mode93_RNIMJAL1 ` GATE ʀ optype_3_2_0_.m10 ` GATE ̀ mode_cnst_1_0_a2_RNIOV3S[0] ` GATE path_left_addr_cnst_0_2[0] u GATE Ѐ
k_new_pc_5[0] T GATE Ҁ un1_eapostbyte_16_6[5] T GATE Ԁ un1_eapostbyte_16_6[2] T GATE ր ea_reg_3[15] T GATE ea_reg_3_i_m2[14] T GATE ڀ ea_reg_3[13] T GATE ܀ ea_reg_3[12] T GATE ހ ea_reg_3[11] T GATE ea_reg_3[10] T GATE ea_reg_3[9] T GATE ea_reg_3[8] T GATE ea_reg_3[7] T GATE ea_reg_3[6] T GATE ea_reg_3[5] T GATE ea_reg_3[4] T GATE ea_reg_3[3] T GATE ea_reg_3[2] T GATE ea_reg_3_i_m2[1] T GATE ea_reg_3[0] T GATE SS_16[0] S GATE SU_16[0] S GATE path_left_data[7] S GATE path_left_data[0] S GATE path_left_data[1] S GATE path_left_data[2] S GATE path_left_data[3] S GATE path_left_data[4] S GATE path_left_data[5] S GATE path_left_data[6] S GATE
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path_left_data_6[15] S
GATE path_left_data_7[15] S GATE path_left_data_6[9] S GATE path_left_data_7[9] S GATE path_left_data_6[8] S GATE path_left_data_7[8] S GATE path_left_data_6[14] S GATE path_left_data_6[12] S GATE path_left_data_7[14] S GATE path_left_data_7[10] S GATE path_left_data_6[10] S ! GATE path_left_data_7[12] S # GATE " path_left_data_7[11] S % GATE $ path_left_data_6[11] S ' GATE & path_left_data_7[13] S ) GATE ( path_left_data_6[13] S + GATE * path_left_data_6[7] S - GATE , path_left_data_7[7] S / GATE . path_left_data_7[0] S 1 GATE 0 path_left_data_6[0] S 3 GATE 2 path_left_data_7[1] S 5 GATE 4 path_left_data_6[1] S 7 GATE 6 path_left_data_7[2] S 9 GATE 8 path_left_data_6[2] S ; GATE : path_left_data_7[3] S = GATE < path_left_data_6[3] S ? GATE > path_left_data_7[4] S A GATE @ path_left_data_6[4] S C GATE B path_left_data_7[5] S E GATE D path_left_data_6[5] S G GATE F path_left_data_7[6] S I GATE H path_left_data_6[6] S K GATE J path_right_data[5] S M GATE L path_right_data[2] S O GATE N path_right_data[1] S Q GATE P path_right_data[7] S S GATE R path_right_data[6] S U GATE T path_right_data_6[8] S W GATE V path_right_data_7[8] S Y GATE X path_right_data_6[15] S [ GATE Z path_right_data_7[15] S ] GATE \ path_right_data_7[14] S _ GATE ^ path_right_data_6[14] S a GATE ` path_right_data_7[10] S c GATE b path_right_data_7[11] S e GATE d path_right_data_6[11] S g GATE f path_right_data_7[9] S i GATE h path_right_data_6[9] S k GATE j path_right_data_6[10] S m GATE l path_right_data_7[13] S o GATE n path_right_data_6[13] S q GATE p path_right_data_7[12] S s GATE r path_right_data_6[12] S u GATE t path_right_data_7[5] S w GATE v path_right_data_6[0] S y GATE x path_right_data_7[0] S { GATE z path_right_data_6[4] S } GATE | path_right_data_7[4] S GATE ~ path_right_data_6[3] S GATE path_right_data_7[3] S GATE path_right_data_6[2] S GATE path_right_data_7[2] S GATE path_right_data_6[1] S GATE path_right_data_7[1] S GATE path_right_data_6[7] S GATE path_right_data_7[7] S GATE path_right_data_6[6] S GATE path_right_data_7[6] S GATE path_right_data_6[5] S GATE overflow_out GATE q_out_3[14] GATE q_out_3[13] GATE q_out_3[12] GATE q_out_3[11] GATE q_out_3[10] GATE
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q_out_3[9] GATE
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q_out_3[8] GATE q_out_3[15] GATE q_out[7] GATE q_out[0] GATE q_out[1] GATE q_out[2] GATE q_out[3] GATE q_out[4] GATE q_out[5] GATE q_out[6] GATE datamux_o_dest[4] GATE datamux_o_dest[5] GATE datamux_o_dest[6] GATE l8 datamux_o_dest[7] GATE datamux_o_dest[0] GATE datamux_o_dest[1] GATE À v8_0 GATE ŀ CCRo[2] GATE ǀ CCRo[3] GATE ɀ CCRo[1] GATE ˀ
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q_out_5[7] GATE ̀
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q_out_5[5] GATE π CCRo[0] GATE р
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q_out_5[6] GATE Ӏ
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q_out_5[1] GATE Հ
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q_out_5[2] GATE ׀
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q_out_5[3] GATE ـ
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q_out_4[1] GATE ۀ
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q_out_4[2] GATE ݀
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q_out_4[3] GATE ߀
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q_out_4[5] GATE
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q_out_4[6] GATE
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q_out_4[7] GATE CCRo[4] GATE
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q_out_1[0] GATE
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q_out_1_cry_15_0 Ā q_out_1_cry_13_0 Ā q_out_1_cry_11_0 Ā q_out_1_cry_9_0 Ā q_out_1_cry_7_0 Ā q_out_1_cry_5_0 Ā q_out_1_cry_3_0 Ā q_out_1_cry_1_0 Ā q_out_1_cry_0_0 Ā un8_q_out_cry_15_0 Ā un8_q_out_cry_13_0 Ā un8_q_out_cry_11_0 Ā un8_q_out_cry_9_0 Ā un8_q_out_cry_7_0 Ā un8_q_out_cry_5_0 Ā un8_q_out_cry_3_0 Ā un8_q_out_cry_1_0 Ā un8_q_out_cry_0_0 Ā q_out_1_0_cry_15_0 Ā q_out_1_0_cry_13_0 Ā q_out_1_0_cry_11_0 Ā q_out_1_0_cry_9_0 Ā q_out_1_0_cry_7_0 Ā q_out_1_0_cry_5_0 Ā q_out_1_0_cry_3_0 Ā q_out_1_0_cry_1_0 Ā q_out_1_0_cry_0_0 Ā q_out_2_cry_15_0 Ā q_out_2_cry_13_0 Ā q_out_2_cry_11_0 Ā q_out_2_cry_9_0 Ā q_out_2_cry_7_0 Ā q_out_2_cry_5_0 Ā q_out_2_cry_3_0 Ā q_out_2_cry_1_0 Ā q_out_2_cry_0_0 Ā mulu |
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q_out_1[4] GATE c8_1 GATE q_out[0] GATE q_out[4] GATE datamux_o_dest[2] GATE datamux_o_dest[3] GATE state_cnst_i_1_RNO[4] u state_cnst_i_1[4] u dest_reg7_0 u un1_postbyte0_16 u path_left_addr14_0 u un1_postbyte0_14 u dest_reg_cnst_i_0[2] u dest_reg_cnst_i_1[2] u un1_dest_reg53_2_7_1 u un1_dest_reg53_2_1 u ACCB22_RNIJAPT1 S ACCB22_RNIH4141 S
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! " # $ % & l n p q r w x y z { } ^ b c S T U V W X Y
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k_ofshi[2] Q
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0
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k_ofshi[3] Q "datamux_o_dest_reg_addr_RNIQG5Q[3] S un1_write_reg_addr_5 S s8
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1
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2
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, q_out[4]
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3
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q_out_2[4] $vsync_cnt_2_sqmuxa_i_0_a2_2_RNIL27G2 vsync_cnt_RNI9VFR[0] vsync_cnt_0_sqmuxa_0_a2_RNIVRSJ vsync_cnt_0_sqmuxa_0_a3_4 visible_2_i_a2 visible_2_i_a2_3 vsync_cnt_RNIO6BM[7] un2_vsyncrlto10_i_a2
op_RNIKUMT[5] W op[5] W alu_opcode103_2_RNI73811[0] Ā alu_opcode103_2_RNIFR7U1[0] Ā un1_postbyte0_2_1_RNISF8B1[0] Ā alu_opcode_1_f0_RNO[1] Ā alu_opcode_4_1_f0[1] Ā alu_opcode_4_1_f0_0[1] Ā alu_opcode_4_1_f0[2] Ā alu_opcode_4_1_f0_0[2] Ā alu_opcode_2_4_0_.m65 Ā alu_opcode_4_m_1[4] Ā dec_alu_right_path_mod_i[0] Ā -datamux_o_alu_in_right_path_data_cnst_i_o2[1] u state_cnst_i_a2[5] ` state_cnst_i_2_RNO[5] u un1_state_81_1_RNO ` k_clear_e_3_2_RNI08HV S un1_state_16_1_RNIIJ103 ` un1_state_35 S mode88_1_RNIGJO42[0] ` k_new_pc29_0_o2_0 u
un1_state_122 ` un1_k_cpu_addr_1_axb_0 Q next_state_2_sqmuxa_1_RNIN07NC ` dest_reg43_RNI8MJ1L u mode_cnst_1_i_a2_RNI984A3[1] ` k_new_pc26_1 u un1_k_pp_regs_4_sqmuxa ` k_pp_regs_4_sqmuxa_1 ` un1_k_pp_regs_6_sqmuxa ` k_pp_regs_2_sqmuxa_2 ` mode_4_i[0] `
mode_4_i_0[0] ` optype_3_2_0_.m16 ` optype_3_2_0_.m17 ` un1_state_82_1 ` un1_state_80_1_a5 S
mode_4_0_1[1] ` mode_4_0_a5_3[1] ` un1_state_104_1_0 ` un1_state_104_1_a7_1 ` un1_state_104_1_1 ` un1_state_104_1_a7 ` mode_4_i_0_RNO[0] ` mode_4_i_a5_2_0[0] ` mode78 ` path_left_addr13 u mode_4_0_1_1[2] `
mode_4_0_1[2] ` un1_state_79_RNIB4EN3 ` k_pp_regs60_RNIHUUP8 ` dest_reg_cnst_i_a2_2[1] u dest_reg_cnst_i_3[1] u path_left_addr_cnst_i_a5_0[3] u dest_reg_3_bm_RNO[3] u un1_state_7_2_i_o2_RNIFDCC1 u un1_state_50_1_i_o2_RNI9F4F2 u %datamux_o_alu_in_right_path_data_1[0] u )datamux_o_alu_in_right_path_data_0_sqmuxa u %path_right_addr_cnst_0_o3_RNIC5P61[0] u
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dest_reg43 u un1_postbyte0_33_1 u un1_postbyte0_33_1_2 u state_cnst_0_2[1] u state_cnst_0_1[1] u state_cnst_i_2[4] u state_cnst_i_2_RNO[4] u state_cnst_0_o15[1] u state_cnst_i_a2_3[0] S path_right_addr_3_1[3] u path_right_addr_3_0[3] u dest_reg_cnst_i_2[1] u dest_reg_cnst_i_0[1] u dest_reg_cnst_i_0[0] u dest_reg_cnst_i_a5_2[0] u state_32_0_iv_RNO_3[3] u state_cnst_i_a2_11[0] u path_right_addr_cnst_i_o2_0[1] u path_right_addr_cnst_i_m3[1] u path_right_addr_3_1_1[0] u path_right_addr_3_1[0] u un1_eapostbyte_16_0_a2_0[3] T un1_eapostbyte_16_0_o2[6] T un1_state_45 T un1_k_cpu_addr_2_sqmuxa_tz_2 S un1_state_10 S
k_set_e_3_2_0 S "datamux_o_dest_reg_addr_RNIO0RQ[0] S un1_k_pp_active_reg S "datamux_o_dest_reg_addr_RNIQ2RQ[2] S datamux_o_dest_reg_addr[2] S SU_1_sqmuxa_3_RNO S datamux_o_dest_reg_addr[0] S un1_k_pp_active_reg_RNIV11C1 S "datamux_o_alu_in_left_path_addr[2] S %k_pp_active_reg_cnst_0_o3_RNIFUE31[1] S k_pp_active_reg_cnst_0_o3[1] S un1_k_pp_regs_1_sqmuxa_RNO S un1_k_pp_regs_1_sqmuxa S eflag_11_m1 S eflag_11_m0 S
ACCA_RNO_0[3] S ACCB46_RNITQSA1 S
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k_memlo[0] Q
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k_memlo[1] Q un1_k_opcode_3_3_RNIC8F8I S un1_state_37_1_RNIT268D S k_cpu_addr_6_sqmuxa_0_a2 S un1_k_cpu_addr_0_sqmuxa_1 S un1_state_12_1_RNI4SF91 Ҁ un1_state_12_1_RNIHV122 Ҁ z16_2_12_RNO q_out[13] q_out[0]
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q_out_2[0] overflow_out
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q_out_3[7] v8_2 v8_2_RNO q_out_sn_m13 v8_sn_m8 daa8h_r un3_daa8h_r_ac0_5 c8_0 cneg8_r_4 k_pp_regs_cnst_sn.m5 Q k_pp_regs_cnst_sn.m2 Q k_ind_ea[2] Q k_ind_ea[3] Q un1_bios_en_0_a2_0_RNIL3PK un1_bios_en_0_a2_0 visible_2_i_o3_RNIUTDU visible_2_i_o3 visible_2_i_a2_0_i_o2_RNIN8NS visible_2_i_a2_0_i_o2 $vsync_cnt_2_sqmuxa_i_0_a2_2_RNI5MEF1 vsync_cnt_2_sqmuxa_i_0_o3 visible_2_i_o3_2_RNI1OT71 un6_visiblelto10_0_o2 line_cnt_RNIBSNG3[3] line_cnt_RNINHCO[2] un7_hsyncrlto10_i_a2_1_RNIP3GM un7_hsyncrlto10_i_a2_1 $vsync_cnt_2_sqmuxa_i_0_a2_2_RNIC3NK1 vsync_cnt_2_sqmuxa_i_0_a2_2 vsync_cnt_2_sqmuxa_i_0 visible_2_i_a2_0_i_o2_RNIN8NS_0 vsync_cnt_0_sqmuxa_0_a3_1 vsync_cnt_0_sqmuxa_0_a2 visible_2_i_a2_2 visible_2_i_a2_5 redr9_15 redr9_12 un1_CPU_OE_EN_0_a2 un1_CPU_OE_EN_0_a2_0 un1_data_from_video_1_i_m3[0] un1_data_from_video_i_m3[0] un1_data_from_video_1_i_m3[2] un1_data_from_video_i_m3[2] un1_data_from_video_1_i_m3[4] un1_data_from_video_i_m3[4] un1_data_from_video_1_i_m3[7] un1_data_from_video_i_m3[7] un1_data_from_video_1_i_m3[6] un1_data_from_video_i_m3[6] un1_data_from_video_1_i_m3[5] un1_data_from_video_i_m3[5] un1_data_from_video_1_i_m3[3] un1_data_from_video_i_m3[3] un1_data_from_video_1_i_m3[1] un1_data_from_video_i_m3[1] visible_2_i_a3 visible_2_i_o2_1 redr9_14 redr9_3 hsync_cnt_RNIK3ND[0] visible_2_i_o3_RNIOF8B2
chars_data[1] un1_op_3 W op[7] W un1_op_4 W op[3] W cond_taken67 W op[6] W
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un1_op_3_2 W op[4] W
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un1_op_4_3 W op[2] W cond_taken_9_0 W op[0] W alu_opcode_2_4_0_.m35 Ā alu_opcode_2_4_0_.m38 Ā un1_postbyte0_2_1_RNIIN9I[0] Ā un1_postbyte0_2_1[0] Ā un1_postbyte0_1_1_RNIBCVN[0] Ā path_left_addr_2_sqmuxa u alu_opcode102_1_RNI7TQL[0] Ā optype_0_f0[0] ` alu_opcode_2_4_0_.m50 Ā alu_opcode_2_4_0_.m55 Ā alu_opcode103_2_RNIG1N22[0] Ā mode79_5 ` alu_opcode_2_4_0_.m25 Ā alu_opcode_2_4_0_.m24 Ā un1_postbyte0_1_1[0] Ā path_left_addr13_RNIJPVT u alu_opcode102_1[0] Ā mode80 ` alu_opcode103_1[0] Ā mode77 ` alu_opcode103_2[0] Ā dest_reg_2_i_a2[0] u dec_alu_right_path_mod_i_o3[0] Ā path_right_addr_cnst_0_0[0] u alu_opcode_2_4_0_.m15 Ā un1_dest_reg44_1_0 u dec_ea Q & ofs16_0_a2_RNID08V9 un1_state_36 Ҁ ofs16_0_a2_RNINFOI2 k_cpu_oe_cnv Q ofs16_0_a2_RNINFOI2_0 un1_state_81_1_RNI30VC4 `
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ofs16_0_a2 un1_state_79 ` noofs7[0] state_cnst_i_a15_7[0] ` ofs16_0_a2_1_i_a2_0 un1_eapostbyte_16_0_a2[6] T isind datamux_o_dest_0[11] noofs10_0_a2_0[0] un1_eapostbyte_16_0_a2[7] T mode76_5 ` un1_path_left_addr15_2_0 u state_3_sqmuxa_2_RNO ` state_3_sqmuxa_2 ` un1_state_104_1_2_RNO ` un1_state_104_1_2 ` state_cnst_i_a15_11_0[0] ` state_cnst_i_8_RNO[4] u un1_mode89_1 `
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un1_mode93 ` state_cnst_i_m15[5] ` un1_state_13_1 S use_s_1_RNO ` mode_4_i_o5_1[0] ` state59_0_RNI8BA41 ` mode53_1 ` un1_state_44 ` k_eahi_11_iv_0_3_i_a4_0_0 un1_state_51 ` un1_state_104_1_o7 S state_cnst_i_a15_4_2[0] ` state_32_iv_RNO_5[0] u state59_0_RNIMU761 ` k_pp_regs_25_RNIBJP61[1] Ҁ k_ofshi_1_sqmuxa ` state_cnst_i_o2[4] u un1_state_56_0_a2_0_RNIJQ681 ` un1_k_cpu_addr_2_sqmuxa_1_0 S k_cpu_addr_4_sqmuxa_i_o2 ` k_cpu_addr_28_iv_RNO[1] k_pp_active_reg_cnst_0_a5_0[3] ` k_pp_regs_25[0] Ҁ state59_0_RNI63IO1 ` un1_state_37_1 S state59_0_RNIPIKK1 ` k_pp_regs_25[1] Ҁ un1_k_pp_regs_6_i_a2_0_RNIJNCQ1 ` k_pp_regs_25[3] Ҁ un1_k_p2_valid6_1_RNI9EP02 ` state_32_iv_RNO_0[0] u un1_mode109_RNIM5S12 `
k_new_pc_2[8] un1_mode109_RNIU4L34 `
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state57[0] S un1_cpu_reset_11 ` k_cpu_addr_1_sqmuxa ` k_memhi_0_sqmuxa_RNIGVP52 ` k_memhi_0_sqmuxa ` mode53_0_RNIULGBO ` next_state_0_sqmuxa_1 S un1_next_state_3_sqmuxa ` un1_state_7_2_i_o2_RNIFDCC1_0 u state_cnst_i_a15_10[0] ` state_cnst_0_o2_0[2] S k_eahi_0_sqmuxa_2_RNI9C57A ` un1_state_7_2_i_o2_RNISBCE9 u un1_state_82_1_RNI3MDV1 ` k_clear_e_3_2_RNIJ8QU S state_cnst_i_a15_4[3] ` state_cnst_0_a15_2_0[2] S next_state_cnst_i_1[0] ` k_clear_e_3_3_RNIB22O5 u state_cnst_i_a15_9[4] ` state_cnst_i_a2[4] u state_cnst_i_a15_11[0] ` dest_reg44_3 u next_state21 ` next_state_10_1[1] ` optype_3_2_0_.N_19_m ` %datamux_o_alu_in_left_path_data_sn_m1 T optype_0_f0[1] ` datamux_o_dest_sn_m1 T un1_k_p2_valid6_1 ` state_cnst_0_12[1] u un1_mode109 ` k_new_pc29_0_o2_0_RNIGJO42 u un1_state59_8_i_a2 ` k_pp_regs_5_sqmuxa_1 Ҁ optype_3_2_0_.m12 ` optype_3_2_0_.m11 ` un1_state_79_RNI666H ` next_state10 S un1_cpu_reset_11_1 ` un1_cpu_reset_11_0 ` un1_state_81_1 ` un1_state_81_1_a6 ` mode79_RNIHRCD ` mode79 ` optype_3_2_0_.m9 ` optype_3_2_0_.m7 ` un1_k_pp_regs_10 ` state_cnst_0_a2_i_1[2] S un1_state_80_1 ` state_cnst_i_a2_2_RNIGCMP[0] S mode77_RNICA18 ` mode76 ` mode_cnst_1_i_a2[1] ` k_new_pc25_1 u optype_3_2_0_.m4 ` state_cnst_i_o2_3[3] u use_s_1 `
SU_lcry_0_RNO S mode_4_0_a5_0[1] ` mode_4_0_a5_0_1[1] ` un1_state_100_i_o4_RNI60VG1 ` state_RNI79CU[3] Q optype_3_2_0_.m15 ` state_cnst_i_o2_2_1[5] ` state_cnst_i_o2[0] ` state_cnst_0_a15_4_1[2] un1_state_33 ` un1_state_33_3 S mode_4_i_a2[0] ` un1_dest_reg56_1_1 u state128 ` state_cnst_0_o2_2[1] u mode88_1[0] ` state82_0 u mode79_3 ` path_left_addr_2_1_.m5 u un1_state_104_1_a2_0 ` state_32_0_iv_RNO_6[3] u state192lto7_4_i_a2 ` k_pp_regs_3_sqmuxa Ҁ un1_state_100_i_o4 ` un1_state_100_i_a4_2_RNIBNII1 S un1_state_16_1 ` un1_k_cpu_addr_2_sqmuxa_tz_1 S un1_k_pp_regs_6_i_a2_0 ` k_pp_active_reg_cnst_0_1[3] S un1_state_40_0 ` state_cnst_0_0[2] u state_cnst_i_o2_2[5] ` state_cnst_i_RNO[5] u state192lto7 ` un1_state_83_i_o4_0_RNIE4AG1 S state59_0_RNI06A03 ` un1_state_37_1_RNIGAKI3 S
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state133_0 u state133_4_RNIMCL03 u state_cnst_i_o15_RNO[0] u state_cnst_i_o15[0] u state_cnst_0_a2_9[1] u state_cnst_i_5[4] u dest_reg_cnst_i_a2_5[0] u path_left_addr50_1_RNIHISU1 u state_cnst_i_a2_5[0] u state_cnst_i_a15_3[0] S un1_state_17_2_RNI54PR1 u un1_state_17_2 u un1_state_23 u k_mul_cnt_RNI6QASC Q un1_state_1_sqmuxa_2_RNO u un1_state_1_sqmuxa_2 u state_cnst_i_a2_14[0] u state_cnst_0_o2[1] u dest_reg_cnst_i_a2_3[0] u dest_reg_cnst_i_2[0] u state_cnst_i_a15_1_0_RNI7NDU[5] u state_cnst_i_a15_1_0[5] u un1_state_7_2_i_o2_RNIECII2 u next_mem_state_8_0_a2_756_i_1 S state_32_iv_RNO_7[0] u state_cnst_i_a2_2[0] S state_cnst_0_13_RNO[1] u state_cnst_0_13[1] u state_32_0_iv_RNO_2[3] u state_32_0_iv_RNO_1[3] u un1_dest_reg44_1_2_RNIFJF71 u un1_dest_reg53_2 u state_cnst_0_10_RNO[1] u
k_clear_e_3_2 S state_cnst_0_8_0_RNO[2] u state_cnst_0_8_0[2] u state83_1 u state_32_iv_RNO_2[0] u state_cnst_i_7_RNO[5] u state_cnst_0_a2_2[1] S state82 u un1_next_state_1_sqmuxa_1 u k_new_pc29_0_o2_0_RNI46L31 u state_cnst_i_RNO_0[5] u k_memlo_1_sqmuxa u un1_state_50_1_i_o2_RNI0FLID u state_32_iv_2[1] u state_1_m state_32_0_iv_RNO[2] u
un1_state_118 u state_32_0_iv_RNO[3] u state_32_0_iv_RNO_0[3] u state_32_iv_RNO[0] u state_cnst_i_a15_2[0] u un1_dec_o_write_flags u cff_1_sqmuxa_2_RNI9H8F S result_size_ac0_5 u datamux_o_dest[15] state_cnst_i[5] u state_cnst_i_a15_0[5] state_cnst_i_8[4] u state_cnst_0_a2_11[1] S state_cnst_i_9[4] u state_cnst_i_o2_1[3] S state_cnst_0_a15_3[1] u state_cnst_0_a15_3_0[1] u state_cnst_i_7[5] u state_cnst_i_a2_2_RNIK9H11[0] S state_cnst_0_8[1] u un1_state_41_2 Ҁ state_cnst_0_6[2] u state_cnst_0_a2_i[2] S state_32_iv_RNO_1[0] u state_32_iv_RNO_3[0] u state_cnst_0_a15[1] u state_cnst_0_o2_4[1] u un1_state_1_sqmuxa_2_RNI58MD2 u state_32_0_iv_0_i_a5_2 u state_32_iv_2[5] u state_32_iv_0[5] u state_32_iv_2[0] u state_32_iv_0[0] u datamux_o_dest13 u datamux_o_dest_0[15] dest_reg_0_sqmuxa_2_RNIV3V9 u dest_reg_0_sqmuxa_2 u un1_dest_reg44_1 u path_left_addr_1_bm_1[3] u state_cnst_0_7[1] u state_cnst_0_a15_7[1] u un1_dest_reg44_1_2 u path_left_addr_0_sqmuxa u state_cnst_i_5[5] u un1_state_33_3_RNIJ6411 S state_cnst_0_5[1] u state_cnst_0_o2_3[1] u state_cnst_0_4[2] u state_cnst_0_2[2] u dest_reg_cnst_i_1[0] u
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state133_1 u state_cnst_i_3[5] u un1_state_11_1 u state_32_0_iv_RNO_4[3] u state_32_0_iv_RNO_5[3] u dest_reg_3_sqmuxa u path_left_addr_cnst_0_a2_0[0] u un1_dest_reg53_3_a5 u path_left_addr50_1 u state_cnst_i_a15_11[3] u un1_state_13_1_RNIEVTU S state_cnst_i_2[5] u un1_state_24_1 S state_32_iv_RNO_6[0] u un1_state_11_4 T k_write_pc9 u
k_write_pc9_3 u un1_postbyte0_6 u un1_postbyte0_6_RNO u state_7_sqmuxa_1_8 u k_pp_regs_cnst_sn.m17_4 Q state_cnst_0_0[1] u un1_state_36_1 u path_left_addr_cnst_i_o2[3] u path_left_addr_1_bm_1[2] u dest_reg_5_sqmuxa_1_0 u un1_dest_reg56_1 u
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pipe1_1_6_cry_8_0 pipe1_1_6_cry_7_0 pipe1_1_6_cry_5_0 pipe1_1_6_cry_3_0 pipe1_1_6_cry_1_0 pipe1_1_6_cry_0_0 pipe1[15] pipe1[0] pipe1_1_s_15_0 pipe1[13] pipe1[14] pipe1_1_cry_13_0 pipe1[11] pipe1[12] pipe1_1_cry_11_0 pipe1[9] pipe1[10] pipe1_1_cry_9_0 pipe1[7] pipe1[8] pipe1_1_cry_7_0 pipe1[5] pipe1[6] pipe1_1_cry_5_0 pipe1[3] pipe1[4] pipe1_1_cry_3_0 pipe1[1] pipe1[2] pipe1_1_cry_1_0 pipe1_1_cry_0_0 pipe1_1_4_cry_8_0 pipe1_1_4_cry_6_0 pipe1_1_4_cry_4_0 pipe1_1_4_cry_2_0 pipe1_1_4_cry_1_0 pipe0_1_4_cry_8_0 pipe0_1_4_cry_6_0 pipe0_1_4_cry_4_0 pipe0_1_4_cry_2_0 pipe0_1_4_cry_1_0 pipe0_1_5_cry_8_0 pipe0_1_5_cry_6_0 pipe0_1_5_cry_4_0 pipe0_1_5_cry_2_0 pipe0_1_5_cry_1_0 pipe0[11] pipe0_1_s_11_0 pipe0[9] pipe0[10] pipe0_1_cry_9_0 pipe0[7] pipe0[8] pipe0_1_cry_7_0 pipe0[5] pipe0[6] pipe0_1_cry_5_0 pipe0[3] pipe0[4] pipe0_1_cry_3_0 pipe0_1_cry_2_0 alu8 { ( 3 4 5 6 7 M Q R U ] ^ b f i k s u } ~
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state133_2 u un1_k_opcode_3_3_RNIG44F1 S
un1_state_7_3 u un1_k_cpu_addr_1_sqmuxa_0_a2_0_0 S un1_state_7_2_i_o2 u un1_k_cpu_addr_2_sqmuxa_tz_0 S un1_state_38_1 u k_cpu_data_o_1_sqmuxa_i_o2 S un1_state_10_1 u un1_state_100_i_a4_2_RNIAADB1 S un1_eapostbyte_16_1_a2_3[8] T un1_eapostbyte_16_1_0[15] T !un1_eapostbyte_16_sn_m13_0_0_a2_0 T un1_eapostbyte_16_0_2[1] T eamem_addr_o_cry_7_0_RNIRKDN T
k_new_pc_1[8] T eamem_addr_o_cry_9_0_RNIVQFN T k_new_pc_1[10] T eamem_addr_o_cry_11_0_RNIAJO8 T k_new_pc_1[12] S eamem_addr_o_cry_13_0_RNIDOQ8 T k_new_pc_1[13] S k_new_pc_1_RNO[7] T
k_new_pc_1[7] T k_new_pc_1_RNO[5] T
k_new_pc_1[5] T eamem_addr_o_cry_3_0_RNI4IKU T
k_new_pc_1[3] S un1_eapostbyte_16_0_2_RNO[0] T un1_eapostbyte_16_0_2[0] T un1_eapostbyte_16_0_1_RNO[6] T un1_eapostbyte_16_0_1[6] T un1_eapostbyte_16_0_3_RNO[1] T un1_eapostbyte_16_0_3[1] T un1_eapostbyte_16_0_1_RNO[4] T un1_eapostbyte_16_0_1[4] T un1_eapostbyte_16_0_a2_4[6] T un1_eapostbyte_16_0_2[3] T un1_eapostbyte_12_0_a2 T un1_pc[9] T un1_state_21_RNIMEOJ T un1_state_21 T eamem_addr_o_cry_7_0_RNI1T041 T !datamux_o_alu_in_left_path_data16 S un1_eapostbyte_16_0_a2[0] T un1_eapostbyte_16_sn_m13_0_0_a2 T ea_reg_3_RNI3RN9[0] T un1_eapostbyte_16_0_a2_3[6] T k_new_pc_1_RNO[0] T eamem_addr_o_axb_0 T k_cpu_addr_28_iv_1[3] T un1_k_cpu_addr_1_sqmuxa_0 S k_cpu_addr_28_iv_1[5] T k_cpu_addr_28_iv_0[5] T k_cpu_addr_28_iv_1[8] T k_cpu_addr_28_iv_0[8] T k_cpu_addr_28_iv_1[10] T k_cpu_addr_28_iv_0[10] T k_cpu_addr_28_iv_1[12] T k_cpu_addr_28_iv_0[12] T datamux_o_dest[8] T q_out[8] k_cpu_addr_28_iv_0[3] T un1_k_cpu_addr_0_sqmuxa S
k_new_pc_2[4] T
k_new_pc_1[4] T k_new_pc_4_s_15_0_RNO T k_new_pc_3[15] %datamux_o_alu_in_right_path_data_1[3] T path_right_data[3] S un1_regs_o_su_iv_0[0] T reg_su[0] S
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* , - . V
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un1_pc[12] T un1_eamem_addr63_3_i_0 T regs_o_su_m_i_m2[14] T k_cpu_addr_28_iv_0[14] un1_eapostbyte_16_0_a2[3] T un1_eapostbyte_16_0_a2_5[1] T un1_eapostbyte_16_0_a2[4] T un1_eapostbyte_16_0_a2_6[1] T un1_eapostbyte_16_0_1[7] T un1_eapostbyte_16_0_1_RNO[7] T un1_eapostbyte_16_sn_m13_0_0 T !un1_eapostbyte_16_sn_m13_0_0_a2_1 T un1_eapostbyte_16_1_0[13] T #un1_eapostbyte_16_0_a2_5_RNI3TR3[1] T k_eahi_11_iv_0_0_914_i_0 T un1_state_23_1 S datamux_o_dest_0[10] T datamux_o_dest[10] k_new_pc_1_RNO[1] S
k_new_pc_1[1] S ACCB_0_sqmuxa_1_RNO S ACCB_0_sqmuxa_1 S
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` a k
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k_ofshi[6] Q
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k_ofshi[7] Q PC_1_sqmuxa_2_RNO S
PC_1_sqmuxa_2 S k_cpu_oe_3_2_1_RNO S k_cpu_oe_3_2_1 S un1_state_104_1_o7_RNI1AO41 S k_pp_regs_6_sqmuxa_1_1 Ҁ un1_state_17 S un1_state_73 S state_cnst_0_a2_4[1] S state_cnst_0_a15_9[2] S IX_1_sqmuxa_1_2 S un1_right_reg_4 S k_opcode[4] Q k_opcode[5] Q SS_1_sqmuxa_2_2 S un1_right_reg_1 S cff_1_sqmuxa_2_2 S cff_1_sqmuxa_2 S un1_state_23_1_RNIE1OG2 S un1_state_86_4_RNIGS8I3 S right_reg_RNI75LO1 S right_reg S #datamux_o_dest_reg_addr_RNI4IS41[1] S datamux_o_dest_reg_addr[1] S k_pp_active_reg_cnst_0_1_RNO[1] S k_pp_active_reg_cnst_0_1[1] S #datamux_o_dest_reg_addr_RNI8NGO1[3] S datamux_o_dest_reg_addr[3] S k_pp_active_reg_cnst_i_o3[0] S k_pp_active_reg_cnst_0_a5[1] S path_left_data_RNIJ2H11[6] S
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"
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IY_10_0[6] S path_left_data_RNIH0H11[5] S
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$
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IX_10_0[5] S path_left_data_RNIU3J91[3] S
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5
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IX_10_0[3] S path_left_data_RNIS1J91[2] S
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7
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IX_10_0[2] S path_left_data_RNIC2VA1[1] S
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<
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IX_10_0[1] S path_left_data_RNIA0VA1[0] S
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=
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IY_10_0[0] S SU_205_m3 S SU_0_sqmuxa_2_RNI4AD61 S SU_206_m3 S SU_16[1] S SU_207_m3 S SU_16[2] S SU_208_m3 S SU_16[3] S SU_209_m3 S SU_16[4] S SU_210_m3 S SU_16[5] S SU_211_m3 S SU_16[6] S SU_212_m3 S SU_16[7] S SS_221_m3 S SS_0_sqmuxa_RNIGPUT S SS_222_m3 S SS_16[1] S SS_223_m3 S SS_16[2] S SS_224_m3 S SS_16[3] S SS_225_m3 S SS_16[4] S SS_226_m3 S SS_16[5] S SS_227_m3 S SS_16[6] S SS_228_m3 S SS_16[7] S SU_213_m3 S SU_16[8] S SU_214_m3 S SU_16[9] S SU_215_m3 S SU_16[10] S SU_216_m3 S SU_16[11] S SU_217_m3 S SU_16[12] S SU_218_m3 S SU_16[13] S SU_219_m3 S SU_16[14] S SU_220_m3 S SU_16[15] S SS_229_m3 S SS_16[8] S SS_230_m3 S SS_16[9] S SS_231_m3 S SS_16[10] S SS_232_m3 S SS_16[11] S SS_233_m3 S SS_16[12] S SS_234_m3 S SS_16[13] S SS_235_m3 S SS_16[14] S SS_236_m3 S SS_16[15] S
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u
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SU_16_0[1] S SU_2_sqmuxa S
|
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SS_16_0[1] S SS_3_sqmuxa S
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IX_10_0[0] S IX_0_sqmuxa S
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k_ofslo[6] Q
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k_ofslo[7] Q
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IY_10_0[1] S IY_1_sqmuxa S
ACCA_RNO_0[6] S
ACCA_RNO_1[6] S
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k_memlo[6] Q
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k_memlo[7] Q
ACCA_RNO_0[2] S
ACCA_RNO_1[2] S
|
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k_memhi[6] Q
|
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k_memhi[7] Q
ACCA_RNO_0[0] S
ACCA_RNO_1[0] S
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a8 ' ) * + , - . / 0 1 2 o t v c
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k_memhi[2] Q
|
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k_memhi[3] Q
ACCA_RNO_0[7] S
ACCA_RNO_1[7] S
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k_ofshi[0] Q
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k_ofshi[1] Q
ACCA_RNO_0[4] S
ACCA_RNO_1[4] S
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un9_q_out_cry_7_0 ( un9_q_out_cry_5_0 ( un9_q_out_cry_3_0 ( un9_q_out_cry_1_0 ( un9_q_out_cry_0_0 ( q_out_1_cry_7_0 ( q_out_1_cry_5_0 ( q_out_1_cry_3_0 ( q_out_1_cry_1_0 ( q_out_1_cry_0_0 ( neg8_w_s_7_0 ' neg8_w_cry_5_0 ' neg8_w_cry_3_0 ' neg8_w_cry_1_0 ' neg8_w_cry_0_0 ' un1_regs_o_pc_s_15_0 P un1_regs_o_pc_cry_13_0 P un1_regs_o_pc_cry_11_0 P un1_regs_o_pc_cry_9_0 P un1_regs_o_pc_cry_7_0 P un1_regs_o_pc_cry_5_0 P un1_regs_o_pc_cry_3_0 P un1_regs_o_pc_cry_1_0 P un1_regs_o_pc_cry_0_0 P un1_k_cpu_addr_1_s_15_0 P un1_k_cpu_addr_1_cry_13_0 P un1_k_cpu_addr_1_cry_11_0 P un1_k_cpu_addr_1_cry_9_0 P un1_k_cpu_addr_1_cry_7_0 P un1_k_cpu_addr_1_cry_5_0 P un1_k_cpu_addr_1_cry_3_0 P un1_k_cpu_addr_1_cry_1_0 P k_cpu_addr_28_iv[0] S k_cpu_addr_28_iv[1] P
k_cpu_addr[0] P
k_cpu_addr[1] P k_cpu_addr_28_iv[2] ' k_cpu_addr_28_iv[3] R
k_cpu_addr[2] P
k_cpu_addr[3] P k_cpu_addr_28_iv[4] ' k_cpu_addr_28_iv[5] '
k_cpu_addr[4] P
k_cpu_addr[5] P k_cpu_addr_28_iv[6] ' k_cpu_addr_28_iv[7] S
k_cpu_addr[6] P
k_cpu_addr[7] P k_cpu_addr_28_iv[8] S k_cpu_addr_28_iv[9] R
k_cpu_addr[8] P
k_cpu_addr[9] P k_cpu_addr_28_iv[10] ' k_cpu_addr_28_iv[11] ' k_cpu_addr[10] P k_cpu_addr[11] P k_cpu_addr_28_iv[12] S k_cpu_addr_28_iv[13] ' k_cpu_addr[12] P k_cpu_addr[13] P k_cpu_addr_28_iv[14] S k_cpu_addr_28_iv[15] ' k_cpu_addr[14] P k_cpu_addr[15] P PC_pipe_RNO ' datamux_o_dest_0[13] S PC_pipe ' k_new_pc_2[10] eamem_addr_o_cry_11_0_RNIAH777 S PC_pipe_1
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k_memlo[2] Q
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PC_pipe_15 ( PC_pipe_25_RNO datamux_o_dest_0[10]
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k_memlo[3] Q
ACCA_RNO_0[1] S
ACCA_RNO_1[1] S
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PC_pipe_25 k_new_pc_2[15] ' k_new_pc_2[12] ( PC_pipe_1 ' PC_pipe_1 ( un6_pipe0[0] pipe0_1_4_axb_1 pipe0[0] pipe0[1]
pipe0_1_axb_2 un8_q_out_cry_0_0_RNO Ā pipe0[2] zff_9_u R test_cond P U . T Y f i l o r u x { Z _ p 3 4 5 7 8 9 : ; < =
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k_memhi[4] Q
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8 : < p r t
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k_memhi[5] Q
ACCA_RNO_0[5] S
ACCA_RNO_1[5] S
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X
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k_memlo[4] Q
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Z
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k_memlo[5] Q
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\
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SU_16_0[8] S left_1[8] S
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^
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SU_16_0[9] S left_1[9] S SS_16_0[10] S
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` cond_taken_9_0 reg_z_in À eamem_addr_o_axb_0_RNIUR562 S eamem_addr_o_cry_1_0_RNI3CCD2 S ra_in[0] ra_in[1] "datamux_o_alu_in_left_path_data[2] GATE ra_in[2] path_left_data_RNI9KED2[3] R "datamux_o_alu_in_left_path_data[4] ' ra_in[3] ra_in[4] eamem_addr_o_cry_5_0_RNIFSGD2 S "datamux_o_alu_in_left_path_data[6] ' ra_in[5] ra_in[6] path_left_data_RNIL4JD2[7] R eamem_addr_o_cry_7_0_RNI2PSF1 S ra_in[7] "datamux_o_alu_in_left_path_data[8] S GATE ra_in[8] "datamux_o_alu_in_left_path_data[9] ' GATE ra_in[9] #datamux_o_alu_in_left_path_data[10] GATE ra_in[10] #datamux_o_alu_in_left_path_data[11] S GATE ra_in[11] #datamux_o_alu_in_left_path_data[12] GATE ra_in[12] #datamux_o_alu_in_left_path_data[13] S GATE ra_in[13] #datamux_o_alu_in_left_path_data[14] GATE ra_in[14] #datamux_o_alu_in_left_path_data[15] ' GATE ra_in[15] #datamux_o_alu_in_right_path_data[0] #datamux_o_alu_in_right_path_data[1] ( rb_in[0] rb_in[1] #datamux_o_alu_in_right_path_data[2] #datamux_o_alu_in_right_path_data[3] rb_in[2] rb_in[3] #datamux_o_alu_in_right_path_data[4] #datamux_o_alu_in_right_path_data[5] S rb_in[4] rb_in[5] #datamux_o_alu_in_right_path_data[6] ' #datamux_o_alu_in_right_path_data[7] rb_in[6] rb_in[7] #datamux_o_alu_in_right_path_data[8] S GATE rb_in[8] %datamux_o_alu_in_right_path_data_2[9] S (datamux_o_alu_in_right_path_data_2_m2[9] S rb_in[9] $datamux_o_alu_in_right_path_data[10] GATE rb_in[10] $datamux_o_alu_in_right_path_data[11] GATE ŀ rb_in[11] $datamux_o_alu_in_right_path_data[12] GATE Ȁ rb_in[12] $datamux_o_alu_in_right_path_data[13] GATE ˀ rb_in[13] $datamux_o_alu_in_right_path_data[14] GATE rb_in[14] $datamux_o_alu_in_right_path_data[15] GATE р rb_in[15] nff_9_u R nff_9_0 R reg_n_in À dec_alu P 7 ? ? @ A B C D E F G I J K L ! # % ' ( ) * + , - / 1 3 , . / 0 2 > v x z { |
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left_1[10] S SS_16_0[11] S
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b
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left_1[11] S SS_16_0[12] S
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d
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left_1[12] S SS_16_0[13] S
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f alu_opcode_1_f0[0] ׀ alu_opcode_1_f0_0[1] ׀ rop_in[0] rop_in[1] alu_opcode_1_f0_0[2] ׀ alu_opcode_1_f0_0[3] ׀ rop_in[2] rop_in[3] alu_opcode_4_m[4] ׀ un1_postbyte0_2_1_RNIF6SM1[0] ׀ rop_in[4] CCRo[0] c16_u À cff_pipe R CCRo[3] GATE nff_pipe R dec_regs P ; S V ] t ! > P R Z [ \ ] _ ` a b c d e f g i j k m n o q s t u w y z { | } & 0 2 4 D F H J R X f
- 1 3 ; ? A C E F G H I M Q f q y
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left_1[13] S SU_16_0[14] S
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]
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left_1[14] S SU_16_0[15] S
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_
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left_1[15] S eflag_RNO S eflag_0_sqmuxa_0_0 S datamux_o_dest[13] S datamux_o_dest_0[13] S IY_1_sqmuxa_2_1_0_RNISJTR1 S ACCB22_RNII5141 S IX_0_sqmuxa_1_1_RNIVGKH3 S IX_0_sqmuxa_1_1 S
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a
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k_ofslo[4] Q
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e
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k_ofslo[5] Q un1_right_reg_4_RNIM2L32 S ACCB22 S ACCB_0_sqmuxa_1_RNIIOBV S ACCB46 S
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g
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k_ofshi[4] Q
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i
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k_ofshi[5] Q un1_state_83_i_o4_0_RNIASUH6 S state_RNIAOMJ1[4] Q DP_1_sqmuxa_1_1_0_RNIFF9C1 S DP_1_sqmuxa_1_1_0 S
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l
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k_ofslo[2] Q
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k_ofslo[3] Q
IY_0_sqmuxa_1 S cff_1_sqmuxa_1 S k_opcode[6] Q k_opcode[7] Q %datamux_o_alu_in_right_path_data_1[4] S path_right_data[4] S right_cry_0_0_RNO S path_right_data[0] S SS_0_sqmuxa S SS_1_sqmuxa S
SU_0_sqmuxa_2 S
SU_1_sqmuxa_2 S un1_k_cpu_addr_2_sqmuxa S k_cpu_addr_28_iv_0[15] right_cry_7_0_RNO_0 S path_right_data_sn_m7 S k_pp_active_reg_cnst_i_0[0] S k_pp_regs_2_sqmuxa Ҁ +datamux_o_alu_in_left_path_addr_RNIUORB1[1] S "datamux_o_alu_in_left_path_addr[1] S k_pp_active_reg_cnst_0_2[2] S k_pp_active_reg_cnst_0_1[2] S path_right_data[15] S path_right_data_sn_m6 S reg_su_i_m2[15] S un1_regs_o_su_iv_0[15] reg_su[7] S k_cpu_addr_28_iv_0[7] reg_su[4] S k_cpu_addr_28_iv_0[4]
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dest_reg_3[0] GATE
dest_reg_o[0]
dest_reg_3[1] dest_reg_3_0[1]
dest_reg_o[1]
dest_reg_3[2] GATE
dest_reg_o[2]
dest_reg_3[3] GATE
dest_reg_o[3] path_left_addr_1[0] GATE path_left_addr_o[0] path_left_addr_1[1] GATE path_left_addr_o[1] path_left_addr_1[2] GATE path_left_addr_o[2] path_left_addr_1[3] GATE path_left_addr_o[3] path_right_addr[0] GATE path_right_addr_o[0] path_right_addr_0[1] path_right_addr_0[2] path_right_addr_o[1] path_right_addr_o[2] path_right_addr[3]
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reg_su[13] S k_cpu_addr_28_iv_0[13]
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GATE path_right_addr_o[3] eflag_11_m1 R
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reg_su[11] S k_cpu_addr_28_iv_0[11] reg_su[6] S k_cpu_addr_28_iv_0[6] reg_su_i_m2[1] S k_cpu_addr_28_iv_0[1] reg_su[2] S k_cpu_addr_28_iv_0[2] reg_su[9] S k_cpu_addr_28_iv_0[9] +datamux_o_alu_in_left_path_addr_RNI8SS01[1] S "datamux_o_alu_in_left_path_addr[3] S un1_state_86_4 S un1_state_86_1 S un1_state_83_i_o4_0_RNICQL73 S state_RNINS9B1[3] Q k_set_e_3_2 S un1_state_13_0 ` k_forced_mem_size_2_iv_i_RNO S k_forced_mem_size_2_iv_i_RNO_0 S state_cnst_0_a2_2_RNIR8OT1[1] S k_mul_cnt_RNIU7815 Q un1_state_20 S un1_state_12_1 Ҁ un1_k_opcode_3_3 S k_pp_regs_cnst_sn.m17_5 Q datamux_o_dest_0[12] S datamux_o_dest[12]
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eflag_pipe R eflag_pipe_1_RNO R eflag_pipe_1 R CCRo14_RNI301B1 ' hflag_9_u R
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q_out_3[8]
|
hflag_pipe R k_clear_e_3
k_clear_e_3_1 k_clear_e P k_cpu_we_3_1 un1_state_40 k_dec_su P N_1921_i S dec_ea P 5 + > k M N O Q S 5 7 9 ; < = > ? A C E G I K L M O Q S U W Y Z [ \ ] _ ` a c e g i k m o ~
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q_out_1[8]
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N_1938_i k_eahi[0] P k_eahi[1] P N_1955_i S N_1972_i S k_eahi[2] P k_eahi[3] P N_1989_i S N_2006_i S k_eahi[4] P k_eahi[5] P N_2023_i S N_2040_i S k_eahi[6] P k_eahi[7] P k_ealo_9_6_593 S k_ealo_9_5_614 k_ealo[0] P k_ealo[1] P N_1800_i k_ealo_9_3_661 R k_ealo[2] P k_ealo[3] P
k_ealo_RNO[4] P
k_ealo_RNO[5] P k_ealo[4] P k_ealo[5] P
k_ealo_RNO[6] P
k_ealo_RNO[7] P k_ealo[6] P k_ealo[7] P k_forced_mem_size_2_iv_i P un1_state_86_1_a3_0 k_forced_mem_size P
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q_out_3[9]
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k_inc_pc_3 P k_inc_pc_3_RNO P k_inc_pc P
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q_out_1[9] q_out_3[10] q_out_1[10] q_out_3[11] q_out_1[11] q_out_3[12] q_out_1[12] q_out_3[13] q_out_1[13] q_out_3[14] q_out_1[14] q_out_3[15] q_out_1[15] carry_out_3 c16_0 pipe1_1_6_23_0 Ҁ un20_pipe1[11] Ҁ
pipe1_1_6_8_0 Ҁ
un20_pipe1[8] Ҁ pipe1_1_6_18_0 Ҁ un20_pipe1[10] Ҁ
pipe1_1_6_3_0 Ҁ
un20_pipe1[7] Ҁ pipe1_1_6_13_0 Ҁ
un20_pipe1[9] Ҁ k_new_pc_1_RNO[6]
k_new_pc_1[6] q1620_2_RNIAA5M q1620_2 q1620_2_RNIL1TQ rb_in_RNIIQB52[7] z16 q1623 z16_2_13 q_out[11] z16_2_12 q_out[15] z16_2_7 q_out[12] z16_2_10 q_out[10] n16
un1_q1620_1_0 q_out[9] q1620_1_RNIGSVI q_out[14] datamux_o_dest[14] v16_u q812 q_out_sn_m11 q_out_sn_m9 q_out_sn_m6 q_out_sn_m5 q1621 q1621_1 q_out_RNO[7] q_out[7] carry_out c8_2 datamux_o_dest_6[9]
k_new_pc_1[9] datamux_o_dest[9] datamux_o_dest_0[9] half_c_out_2
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k_inc_su_5 R un1_state_48 À k_inc_su P cpu0_data_in[0] cpu0_data_in[1] k_ind_ea[0] P k_ind_ea[1] P cpu0_data_in[2] cpu0_data_in[3] k_ind_ea[2] P k_ind_ea[3] P cpu0_data_in[4] cpu0_data_in[5] k_ind_ea[4] P k_ind_ea[5] P cpu0_data_in[6] cpu0_data_in[7] k_ind_ea[6] P k_ind_ea[7] P k_clear_e_3_3_RNIRMBD k_ealo_9_4_639_i_a4
k_mem_dest[0] P k_mul_cnt_4_f0 k_mul_cnt P k_p2_valid_3_f0 P op[7]
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q_out_3[3] datamux_o_dest_6[14] k_new_pc_1[14] k_new_pc_1_RNO[2]
k_new_pc_1[2] k_cpu_addr_28_iv_1[0] k_cpu_addr_28_iv_0[0] daa_lnm9_ac0_5 daa_lnm9_ac0_5_RNIQS011 CCRo_bm_RNO[0] CCRo_bm_RNO_1[0] CCRo_bm_RNO_0[0] v8_sn_m10_0 vneg8_r_5 vneg8_r_2 datamux_o_dest_6[11] k_new_pc_1[11] datamux_o_dest_6[15] k_new_pc_1[15] k_pp_regs_cnst_sn.m17 Q k_pp_regs_cnst_sn.m17_2 Q k_ind_ea[0] Q k_ind_ea[1] Q alu_opcode_2_4_0_.m14 Ā path_left_addr_0_sqmuxa_6 u dec_alu_right_path_mod_i_o5[0] Ā mode_4_0_a5[1] ` alu_opcode_2_4_0_.m18 Ā path_right_addr_cnst_0_o3[0] u alu_opcode_2_4_0_.m5 Ā !path_left_addr_cnst_0_2_bm_RNO[0] u alu_opcode_2_4_0_.m63 Ā dec_alu_right_path_mod_i_1[1] Ā mode75[0] ` mode76_0 ` mode53_0 ` state59_0 ` path_left_addr_cnst_0_a5[1] u path_left_addr_cnst_0_1[0] u cff_1_sqmuxa S
SS_1_sqmuxa_1 S alu_opcode_1_f0_RNO[2] Ā un1_alu_opcode103 Ā alu_opcode_4_1_f1[0] Ā alu_opcode_4_1_f1[3] Ā alu_opcode_2_4_0_.m57 Ā state57_2[0] S alu_opcode_2_4_0_.m27 Ā dest_reg_cnst_i_a5[2] u mode_4_0_a5_1_1[1] ` mode52_1 ` k_pp_regs60 ` k_write_dest_5_RNO u k_eahi_0_sqmuxa_2 ` next_state_2_sqmuxa_1 `
k_p2_valid6_6 `
k_p2_valid8_4 ` optype32[0] ` path_left_addr13_RNO u mode_4_i_a2_2[0] ` dest_reg_3_bm_RNO_0[3] u mode77_1 ` un1_postbyte0_2_4 u mode80_1 ` un1_postbyte0_21_6 u un1_state_56_0_a2_0 ` un1_state_26_1_RNIMC401 S un1_state_14_1 u un1_state_122_RNO ` state_cnst_0_10[1] u state_cnst_0_a15_3[2] S state_32_0_iv_0[2] u state_32_iv_0[1] u state_cnst_i_RNO_1[5] u un1_dest_reg44_1_0_RNO u state_cnst_i_a15[4] u k_cpu_data_o_7_m0s2 Q un1_postbyte0_33_1_0 u path_left_addr_2_1_.m8 u regs_o_su_m_0[10] T
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k_p2_valid P k_p3_valid_3_f0 P un1_state_18_2_RNIB12C1 À
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reg_su[10] S regs_o_su_m_0[5] T reg_su[5] S un1_regs_o_su_iv_0_a2[8] T reg_su[8] S un1_regs_o_su_iv_0_a2[12] T
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k_p3_valid P k_pp_active_reg_7[0] k_pp_active_reg_7[1] R k_pp_active_reg[0] P k_pp_active_reg[1] P k_pp_active_reg_7[2] k_pp_active_reg_cnst_0[3] k_pp_active_reg[2] P k_pp_active_reg[3] P k_pp_regs_25[0] g GATE f k_pp_regs[0] P k_pp_regs_25[1] j GATE i k_pp_regs[1] P k_pp_regs_25[2] m GATE l k_pp_regs[2] P k_pp_regs_25[3] p GATE o k_pp_regs[3] P k_pp_regs_25[4] s GATE r k_pp_regs[4] P k_pp_regs_25[5] v GATE u k_pp_regs[5] P k_pp_regs_25[6] y GATE x k_pp_regs[6] P k_pp_regs_25[7] | GATE { k_pp_regs[7] P k_set_e_3 R un1_state_12_1_RNI1D621 k_set_e P k_write_dest_5 P k_write_dest_0_sqmuxa_1 P k_write_dest P k_write_exg_1_sqmuxa next_state_10_1[1] k_write_exg P k_write_pc_6
cond_taken_17
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reg_su[12] S k_cpu_addr_28_iv_RNO[10] T k_cpu_addr_28_iv_RNO[4] un1_eapostbyte_16_0_0[1] T un1_eapostbyte_16_sn_m13_0_0_1 T k_eahi_11_iv_0_4_830_i_0 T k_eahi_11_iv_0_3_851_i_0 k_eahi_11_iv_0_6_788_i_0 T k_eahi_11_iv_0_935_i_0
SS_lcry_0_RNO S SU_3_sqmuxa S state_cnst_i_a2_7[0] S un1_state_82_1_RNO ` DP_1_sqmuxa S
SU_1_sqmuxa_3 S
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k_write_pc P k_write_post_incdec_7 state_cnst_0_o2[2] k_write_post_incdec P k_write_tfr_1_sqmuxa state82 k_write_tfr P next_mem_state_RNO[0] P next_mem_state_RNO[3] P next_mem_state[0] P next_mem_state[3] P un1_state_33_RNISUNI4 un1_state_15_2_RNI30NR1 next_mem_state[4] P next_mem_state[5] P N_1561_i À un1_state_7_1_RNIRT79 next_push_state[1] P next_push_state[2] P next_state_10[0] next_state_10[1]
next_state[0] P
next_state[1] P next_state_10[2] un1_state_23_1_RNIAOS95
next_state[2] P
next_state[3] P next_state_cnst_0_a2[4] P next_state_10[5]
next_state[4] P
next_state[5] P ACCA_RNO[0] R ACCA_RNO[1] R ACCA[0] R ACCA[1] R ACCA_RNO[2] R ACCA_RNO[3] R ACCA[2] R ACCA[3] R ACCA_RNO[4] R ACCA_RNO[5] R ACCA[4] R ACCA[5] R ACCA_RNO[6] R ACCA_RNO[7] R ACCA[6] R ACCA[7] R DP_1_sqmuxa R DP_1_sqmuxa_1_1_0_RNIIANF1 R
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k_ofslo[0] Q
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DP_pipe_11 R DP_pipe R IX_0_sqmuxa_1_1 R
SU_1_sqmuxa_3 R IX_pipe_1 R IX_pipe R IX_0_sqmuxa R
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k_ofslo[1] Q reg_su[3] S regs_o_su_m_0[3] IY_1_sqmuxa_2_1_0 S SU_1_sqmuxa_4_1 S k_eahi_11_iv_0_5_809_i_0 k_eahi_11_iv_0_1_893_i_0 pipe1_1_6_cry_5_RNO_1 Ҁ pipe1_1_6_cry_5_RNO_0 Ҁ pipe1_1_6_cry_5_0_RNO Ҁ pipe1_1_6_cry_3_RNO_0 Ҁ pipe1_1_6_cry_3_0_RNO Ҁ pipe1_1_6_cry_1_0_RNO Ҁ q_out[3] q_out[1] k_cpu_addr_28_iv_RNO[9] k_cpu_addr_28_iv_RNO[15] CCRo14 q_out_sn_m8 k_cpu_addr_28_iv_RNO[0] un1_k_cpu_addr_1_m[3] k_cpu_addr_28_iv_RNO[13] un1_k_cpu_addr_1_m[5] k_cpu_addr_28_iv_RNO[7] un1_k_cpu_addr_1_m[8] k_cpu_addr_28_iv_RNO[6] k_cpu_addr_28_iv_RNO[11] k_cpu_addr_28_iv_RNO[2] un1_k_cpu_addr_1_m[12] visible_2_i_o3_2 hsync_cnt_RNIQHQC1[3] k_pp_regs_cnst_sn.m7 Q state_cnst_i_o2_1_RNIHE0C1[3] S
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IX_pipe_14 R
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k_memhi[0] Q
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IX_pipe_10 R
IY_0_sqmuxa_1 R IY_1_sqmuxa_2_1_0_RNIVEBV1 R IY_pipe_1 R IY_pipe R IY_1_sqmuxa R
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k_memhi[1] Q alu_opcode_2_4_0_.m1 Ā dest_reg43_4 u alu_opcode_2_4_0_.m22 Ā mode_4_0_x2[1] ` ofs16_0_a2_0 un1_eapostbyte_16_0_a2_3[7] T k_cpu_we_3_RNI4P5E ` k_new_pc29_0_o2_0_RNIRRPH4 u un1_state_104_1_a2 ` un1_state_81_1_a6_RNO ` state_cnst_0_12_RNO[1] u un1_state_50_1_i_o2 u dest_reg_3_bm_RNO[0] u dest_reg_cnst_i_a5_0[2] u k_new_pc29_0_o2_0_RNIHMIG1 u k_cpu_oe_3_1_tz S path_left_addr_1_sqmuxa_2 u !path_left_addr_1_sqmuxa_2_RNI4I6J u path_right_addr_3_sqmuxa u path_right_addr_am_RNO[0] u state_cnst_0_a15_1[1] u un1_state_24 T dest_reg_cnst_i_a2[2] u
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IY_pipe_14 R
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state133_4 u un1_postbyte0_3_3 u SS_1_sqmuxa_2_1 S eamem_addr_o_cry_5_0_RNITMU31 T $datamux_o_alu_in_left_path_data_0[2] eamem_addr_o_cry_3_0_RNIQHS31 T datamux_o_dest_6[4] eamem_addr_o_cry_3_0_RNIPGS31 T $datamux_o_alu_in_left_path_data_0[6] eamem_addr_o_cry_1_0_RNILAQ31 T eamem_addr_o_axb_0_RNIHRJS T eamem_addr_o_cry_1_0_RNO T eamem_addr_o_cry_7_0_RNO_0 T eamem_addr_o_cry_1_0_RNO_0 T eamem_addr_o_cry_7_0_RNO T eamem_addr_o_cry_3_0_RNO T eamem_addr_o_cry_5_0_RNO_0 T eamem_addr_o_cry_3_0_RNO_0 T eamem_addr_o_cry_5_0_RNO T un1_regs_o_su_iv_0_a2[7] T regs_o_su_m_0[11] un1_regs_o_su_iv_0_a2[4] T un1_regs_o_su_iv_0_a2[13]
k_new_pc_1[0] T
k_new_pc_3[0] T
k_new_pc_3[7] T un1_k_memlo[11] k_new_pc_3_i_m2[8] T un1_k_memlo[8] T un1_k_memlo[10] T un1_k_memlo[15] %datamux_o_alu_in_right_path_data_1[5] T %datamux_o_alu_in_right_path_data_1[1]
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IY_pipe_10 R PC_1_sqmuxa R
PC_1_sqmuxa_1 R
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un1_pc[15] T
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PC_pipe_14 R PC_pipe_1 R k_new_pc_2[13] S
PC_pipe_5_RNO R PC_pipe_3 S PC_pipe_5 R k_new_pc_2[11] S
k_new_pc_2[8] S PC_pipe_6 S PC_pipe_8 S k_new_pc_2_i_m2[9] S PC_pipe_20_RNO S
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un1_pc[10] T
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PC_pipe_10 R
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un1_pc[13] T
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PC_pipe_20 S PC_pipe_35_RNO S )datamux_o_alu_in_left_path_data_am_RNO[8] S
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un1_pc[11] T un1_eapostbyte_16_1_0[12] T un1_eapostbyte_16_1_0[14] T un1_eapostbyte_16_1_0[10] T un1_eapostbyte_16_1_0[8] T un1_eapostbyte_16_1_0[9] T un1_eapostbyte_16_1_0[11] T un1_eapostbyte_16_0_0[3] T un1_eamem_addr63_3_i_0_0 T un1_eapostbyte_16_3[5] T un1_eapostbyte_16_3[2] T datamux_o_dest_0[8] T datamux_o_dest_0[14]
k_set_e_3_RNO S un1_state_26_1 S un1_state_18 S un1_state_100_i_a4_2 S un1_k_cpu_addr_1_sqmuxa_0_RNO S un1_k_cpu_addr_2_sqmuxa_1_0_0 S
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PC_pipe_35 S PC_pipe_10_RNO S k_new_pc_sn_m3_e R
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SS_16_0[2] S
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PC_pipe_10 S k_new_pc_2[14] S k_new_pc_0[14] S PC_pipe_1 S
PC_pipe_5_RNO S isind PC_pipe_5 S CCRo[1] v16_u À vff_pipe R CCRo[2] GATE zff_pipe R CCRo[4] result_size_ac0_5
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SU_16_0[2] S
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intff_pipe R eflag_pipe_4_RNO R cff_1_sqmuxa_1 R eflag_pipe_4 R cff_1_sqmuxa R cff_0_sqmuxa R
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SS_16_0[3] S
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cff_pipe_4 R
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SU_16_0[3] S
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cff_pipe_3 R ea_reg_post_o_axb_0 S noofs7_2[0]
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SU_16_0[4] S
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IY_pipe_78 R
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SS_16_0[4] S
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IY_pipe_20 R CCRo14_RNI2H891 ' fflag_9_u R
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SS_16_0[5] S
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fflag_pipe R k_new_pc_sn_m7 dec_op P ; U V W X Y $ . N q r s t u v w x y z { } ~ 4 5 = @ B D w }
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SU_16_0[5] S
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h
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SS_16_0[6] S
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j
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SU_16_0[6] S
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k
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SU_16_0[7] S
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mode76_RNISG8E3
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SS_16_0[7] S
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PC_pipe_15 R
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IY_10_0[4] S
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PC_pipe_13 R k_new_pc[0] R GATE
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IX_10_0[4] S
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PC_pipe_75 R k_new_pc[1] S GATE
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IY_10_0[7] S
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PC_pipe_70 R k_new_pc[2] GATE
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IX_10_0[7] S
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PC_pipe_65 R k_new_pc[3] R GATE
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IY_10_0[8] S
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PC_pipe_60 R k_new_pc[4] ' GATE
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IX_10_0[8] S
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PC_pipe_55 R k_new_pc[5] S GATE
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IY_10_0[9] S
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PC_pipe_50 R k_new_pc[6] ' GATE
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IX_10_0[9] S IY_10_0[10] S IX_10_0[10] S
k_postbyte[0] Q
k_postbyte[1] Q IY_10_0[11] S IX_10_0[11] S
k_postbyte[2] Q
k_postbyte[3] Q IY_10_0[12] S IX_10_0[12] S
k_postbyte[4] Q
k_postbyte[5] Q IY_10_0[13] S IX_10_0[13] S
k_postbyte[6] Q
k_postbyte[7] Q IX_10_0[14] S IY_10_0[14] S k_opcode[0] Q k_opcode[1] Q IY_10_0[15] S IX_10_0[15] S next_push_state[0] Q k_new_pc_3[12] S un1_k_memlo[12] S k_new_pc_3[13] S un1_k_memlo[13] S k_pp_active_reg_cnst_i_a5[0] S k_pp_regs_5_sqmuxa Ҁ %datamux_o_alu_in_right_path_data_1[7] S %datamux_o_alu_in_right_path_data_1[2] right_cry_9_0_RNO S right_cry_13_0_RNO_0 S right_cry_9_0_RNO_0 S right_cry_13_0_RNO S right_cry_11_0_RNO S right_cry_11_0_RNO_0 S
SU_1_sqmuxa_1 S SS_4_sqmuxa S SU_0_sqmuxa S SU_1_sqmuxa S .datamux_o_alu_in_right_path_data_0_sqmuxa_1059 S path_right_data_sn_m4 S un1_regs_o_su_iv_0_a2[1] un1_regs_o_su_iv_0_a2[14] q_out_2_cry_1_0_RNO q_out_3_0[1] q_out_2_cry_1_0_RNO_0 q_out_3_0[2] q_out_2_cry_3_0_RNO q_out_3_0[3] q_out_2_cry_3_0_RNO_0 q_out_2_cry_3_0_RNO_0 q_out_2_cry_5_0_RNO q_out_3_0[5] q_out_2_cry_5_0_RNO_0 q_out_3_0[6] q_out_2_cry_7_0_RNO q_out_3_0[7] k_pp_regs_25_4[3] Ҁ k_pp_regs_25_4[1] Ҁ un20_pipe1[13] Ҁ pipe1_1_6_cry_7_0_RNO Ҁ un1_regs_o_su_iv_0_a2[6] regs_o_su_m_0[2] reg_n_in reg_z_in q1624_1 q_out_sn_m2 q_out[6] CCRo14_1 q_out[2] q_out_5_bm_RNO[1]
k_new_pc_3[9] un1_k_memlo[9] q_out_2_285
q_out_1_0_353 q_out_sn_m4
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PC_pipe_45 R k_new_pc[7] R GATE
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CCRo_sn_m1 k_new_pc_3[14] un1_k_memlo[14]
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PC_pipe_40 R left_1[0] R left_1[1] R
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wen_o_0_a2 k_cpu_we_RNIKJPB Q un1_bios_en_0_a2 cpu0_oe_i Q un1_cpu0_we_0_a2 N_68_i redr9_11
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IY_pipe_77 R
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yptr_axb_5 op[1] W state_32_iv_RNO_4[0] u un1_postbyte0_2_2[0] Ā dest_reg_2_i_o2[0] u optype_3_2_0_.m18 ` un1_k_opcode_3_1 S
k_p2_valid8_3 ` k_ealo_9_3_674_m3 S
k_p2_valid6_2 ` k_ealo_9_4_652_i_a4_0 Ҁ k_ealo_9_5_627_a4_0_0 ` state_cnst_0_a15_0_0[2] S state_cnst_i_a15_10_0[4] u k_new_pc_2[11] state_cnst_i_6[4] u state_cnst_i_a2_9[0] S state_cnst_i_4[4] u state_32_0_iv_0_i_a5_1 u state_32_0_iv_0[3] u un1_state_118_0 u dest_reg_cnst_i_a5_1[0] u un1_opcode_11_1[0] u state_cnst_0_1[2] u un1_state_32_3 S k_ealo_9_5_627_a4_1 u un1_state_33_3_RNIH5Q61 S un1_state_1_sqmuxa_2_1 u k_pp_active_reg_cnst_0_a5_1[2] S
k_new_pc_2[5] T k_new_pc_2[15]
k_new_pc_2[7] T k_new_pc_2[14] k_new_pc_2[10] T
k_new_pc_2[2]
k_new_pc_3[4] T k_new_pc_3[11]
k_new_pc_3[5] T
k_new_pc_3[2] un1_eapostbyte_16_0_0[0] T path_right_data_0[0] S
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IY_pipe_72 R left_1[2] R left_1[3] R
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IY_10_0[2] S
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IY_pipe_67 R
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IY_10_0[5] S
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IY_pipe_62 R left_1[4] R left_1[5] R
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SS_16_0[8] S SS_16_0[15] S
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IY_pipe_57 R
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SS_16_0[9] S SS_16_0[14] S SU_16_0[10] S SU_16_0[13] S SU_16_0[11] S
ACCA_RNO_1[3] S
k_new_pc_2[1] S
k_new_pc_2[9]
k_new_pc_2[3] S
k_new_pc_2[6] k_new_pc_2[13] S k_new_pc_2[12] S
k_new_pc_3[1] S
k_new_pc_3[6]
k_new_pc_3[3] S k_new_pc_3[10] S right_cry_1_0_RNO S right_cry_7_0_RNO S right_cry_1_0_RNO_0 S right_cry_5_0_RNO_0 S right_cry_3_0_RNO S right_cry_5_0_RNO S
SU_0_sqmuxa_1 S regs_o_su_m_0[9] path_right_data_0[4] S next_state10_1 S
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IY_pipe_52 R left_1[6] R left_1[7] R
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q_out_3[0]
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IY_pipe_47 R
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q_out_3[6]
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IY_pipe_42 R left_1[8] R left_1[9] R
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q_out_3[1]
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IY_pipe_37 R
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q_out_3[5]
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IY_pipe_32 R
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q_out_3[2]
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left_1[10] R
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q_out_3[2]
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left_1[11] R
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q_out_3[3]
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IY_pipe_27 R
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q_out_3[1]
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IY_pipe_22 R
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q_out_3[4] q_out[5]
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left_1[12] R
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q_out_3[5] q1620_1
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left_1[13] R
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q_out_3[6]
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IY_pipe_17 R
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q_out_3[7] q_out_2_cry_7_0_RNO_0 q_out_2_cry_7_0_RNO q_out_2_cry_9_0_RNO q_out_2_cry_5_0_RNO_0 q_out_2_cry_9_0_RNO_0 q_out_2_cry_5_0_RNO q_out_2_cry_11_0_RNO q_out_2_cry_3_0_RNO q_out_2_cry_11_0_RNO_0 q_out_2_cry_1_0_RNO_0 q_out_2_cry_13_0_RNO q_out_2_cry_1_0_RNO q_out_2_cry_13_0_RNO_0 un8_q_out_cry_13_0_RNO_0 q_out_2_cry_15_0_RNO un8_q_out_cry_15_0_RNO pipe1_1_6_4 Ҁ un8_q_out_cry_1_0_RNO_0 pipe1_1_6_9 Ҁ un8_q_out_cry_3_0_RNO pipe1_1_6_14 Ҁ un8_q_out_cry_3_0_RNO_0 pipe1_1_6_19 Ҁ un8_q_out_cry_5_0_RNO pipe1_1_6_0 Ҁ un8_q_out_cry_1_0_RNO un20_pipe1[12] Ҁ neg8_w_s_7_0_RNO un15_pipe1[13] Ҁ un8_q_out_cry_7_0_RNO un15_pipe1[12] Ҁ un8_q_out_cry_5_0_RNO_0
pipe1_1_4_1_a Ҁ un8_q_out_cry_0_0_RNO
pipe1_1_4_1_b Ҁ
pipe0_1_5_1_b Ҁ k_cpu_addr_28_iv_1[9] k_cpu_addr_28_iv_1[15] v8_sn_m10 c8_3 k_cpu_addr_28_iv_1[2] k_cpu_addr_28_iv_1[14] k_cpu_addr_28_iv_1[6] k_cpu_addr_28_iv_1[11] k_cpu_addr_28_iv_1[7] k_cpu_addr_28_iv_1[4] k_cpu_addr_28_iv_1[13] k_cpu_addr_28_iv_1[1] q_out_5_RNIRSTD1[7] daa8h_r_RNIUU4I z16_2_1 datamux_o_dest[11] k_pp_regs_3_sqmuxa_RNIJ91Q3 Ҁ k_pp_regs_25_sn_m12_0 Ҁ dest_reg7 u un1_postbyte0_14_5 u k_pp_regs_6_sqmuxa_1_1_RNIQHNA3 Ҁ k_pp_active_reg_cnst_0_2[1] S vsync_cnt_0_sqmuxa_0_o2 y_cnt4_i left S SU_16_0[12] S un1_write_reg_addr_2 S "datamux_o_alu_in_left_path_addr[0] S un1_state_73_RNI7H5S5 S k_pp_active_reg_cnst_0_1_RNO[3] S un1_eapostbyte_16_1_o2[8] T un1_eapostbyte_16_sn_m6_0_0 T %datamux_o_alu_in_right_path_data_1[6] right_cry_3_0_RNO_0 S k_cpu_addr_28_iv_RNO[14] k_inc_pc_3_1 T state57_RNI9L0F7[0] S k_eahi_11_iv_0_2_872_i_0 T
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IY_pipe_12 R
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IX_10_0[6] S
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left_1[14] R
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IY_10_0[3] S k_opcode[2] Q k_opcode[3] Q data_io_pad[0]
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left_1[15] R IY_pipe_7 R IY_pipe_2 R un1_write_reg_addr_5 R un1_write_reg_addr_1 R ACCB_pipe_11 R ACCB_pipe R un1_dec_o_write_flags un3_dest_flags_1 ׀
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data_io[0] cpuclk_o_pad cpuclk_o clk40_i_pad clk40_i
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cff_pipe_1 R k_cpu_data_o_7[0] P B GATE A k_cpu_data_o[0] P k_cpu_data_o_7[1] P E GATE D k_cpu_data_o[1] P k_cpu_data_o_7[2] P H GATE G k_cpu_data_o[2] P k_cpu_data_o_7[3] P K GATE J k_cpu_data_o[3] P k_cpu_data_o_7[4] P N GATE M k_cpu_data_o[4] P k_cpu_data_o_7[5] P Q GATE P k_cpu_data_o[5] P k_cpu_data_o_7[6] P T GATE S k_cpu_data_o[6] P k_cpu_data_o_7[7] P W GATE V k_cpu_data_o[7] P
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blue_o_pad blue_o green_o_pad green_o red_o_pad red_o vsync_o_pad vsync_o textctrl_vsyncrio hsync_o_pad hsync_o textctrl_hsyncrio
leds_o_pad[7] leds_o[7]
leds_r_0io[7]
leds_o_pad[6] leds_o[6]
leds_r_0io[6]
leds_o_pad[5] leds_o[5]
leds_r_0io[5]
leds_o_pad[4] leds_o[4]
leds_r_0io[4]
leds_o_pad[3] leds_o[3]
leds_r_0io[3]
leds_o_pad[2] leds_o[2]
leds_r_0io[2]
leds_o_pad[1] leds_o[1]
leds_r_0io[1]
leds_o_pad[0] leds_o[0]
leds_r_0io[0] state_o_pad[5]
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k_cpu_oe_3 P un1_state_17 k_cpu_oe P un1_state_7_3_RNIHI4S2 À un1_state_50_1_RNIM28F1 k_cpu_we P
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state_o[5] state_o_pad[4]
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cpu_clk_mx cpu_clk div_RNO div reset_cnt_RNO[0] reset_cnt[0] SUM1_0_x2 N_73_i_i reset_cnt[1] reset_cnt[2] SUM3_0 reset_cnt[3] state_32_iv[0] state_32_iv[1] S state[0] P state[1] P state_32_0_iv[2] P state_32_0_iv[3] state[2] P state[3] P state_cnst_i_7_RNIJ9TU4[4] R state_32_iv_i[5] state[4] P state[5] P bluer_RNO[0] redr_4_i_0_a3[0] bluer[0] GND
chars_data[6]
chars_data[7] state_1_m ' CCRo_4_4[2] ' font_data[0] font_data[1]
pipe1_1_4_1_b z16_2_1 À font_data[2] font_data[3] ACCB_9[3] R un8_q_out_cry_3_0_RNO_0 Ā font_data[4] font_data[5] eflag_11_m0 R zff_9_0 R font_data[6] font_data[7] line_cnt_n0_i_a3 line_cnt_RNO[1] line_cnt[0] line_cnt[1] line_cnt_RNO[2] line_cnt_RNO[3] line_cnt[2] line_cnt[3] shift_RNO[0] shift_7_i_m3[1] shift[0] shift[1] shift_7_i_m3[2] shift_7_i_m3[3] shift[2] shift[3] shift_7_i_m3[4] shift_7_i_m3[5] shift[4] shift[5] shift_7_i_m3[6] shift_7_i_m3[7] shift[6] shift[7] state239 R reg_su[0] R tshift[0] tshift[1]
k_write_pc9_3 un1_k_memlo[11] R tshift[2] tshift[3] line_cnt_RNO_0[3] yptr_4_axb_2 tshift[4] tshift[5] redr9_9
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state_o[4] state_o_pad[3]
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un5_RED[0] tshift[6] tshift[7] visible_RNO bluerc_4 visible cond_taken4 GATE cond_taken_15_0 GATE cond_taken_8 GATE alu_opcode_2_4_0_.m54 GATE alu_opcode_1_f0_0_m2_0[2] GATE alu_opcode_2_4_0_.m19 GATE mode_4_0[2] GATE Ā un1_mode93_RNIC8563 GATE ƀ optype_3_2_0_.m17 GATE Ȁ datamux_o_dest[5] S GATE ʀ un1_eapostbyte_16_6[2] S GATE ̀ un1_eapostbyte_16_6[15] S GATE un1_eapostbyte_16_i_m2[9] S GATE Ѐ un1_eapostbyte_16_6[12] S GATE Ҁ ea_reg_3[15] S GATE Ԁ ea_reg_3[14] S GATE ր ea_reg_3[13] S GATE ea_reg_3[12] S GATE ڀ ea_reg_3[11] S GATE ܀ ea_reg_3[10] S GATE ހ ea_reg_3_i_m2[9] S GATE ea_reg_3[8] S GATE ea_reg_3[7] S GATE ea_reg_3[6] S GATE ea_reg_3[5] S GATE ea_reg_3[4] S GATE ea_reg_3[3] S GATE ea_reg_3_i_m2[1] S GATE un1_eapostbyte_16_6[14] S GATE un1_eapostbyte_16_6[13] S GATE un1_eapostbyte_16_6[11] S GATE un1_eapostbyte_16_6[10] S GATE un1_eapostbyte_16_6[8] S GATE un1_eapostbyte_16_i_m2[1] S GATE un1_eapostbyte_16_6[3] S GATE un1_eapostbyte_16_6[6] S GATE un1_eapostbyte_16_6[5] S GATE un1_eapostbyte_16_6[4] S GATE un1_eapostbyte_16_6[0] S GATE un1_eapostbyte_16_6[7] S GATE ea_reg_3[2] S GATE ea_reg_3[0] S GATE
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state_o[3] state_o_pad[2]
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datamux_o_dest[0] S
GATE SU_16[0] R GATE SS_16[0] R GATE path_left_data[6] R GATE path_left_data[5] R GATE path_left_data[4] R GATE path_left_data[3] R GATE path_left_data[1] R GATE path_left_data[0] R GATE path_left_data[7] R GATE path_right_data[6] R ! GATE path_right_data[5] R # GATE " path_right_data[3] R % GATE $ path_right_data[1] R ' GATE & path_right_data[0] R ) GATE ( path_right_data[7] R + GATE * path_left_data_7[6] R - GATE , path_left_data_7[5] R / GATE . path_left_data_7[4] R 1 GATE 0 path_left_data_7[3] R 3 GATE 2 path_left_data_7[1] R 5 GATE 4 path_left_data_7[0] R 7 GATE 6 path_left_data_7[8] R 9 GATE 8 path_left_data_6[8] R ; GATE : path_left_data_7[12] R = GATE < path_left_data_6[12] R ? GATE > path_left_data_7[13] R A GATE @ path_left_data_6[13] R C GATE B path_left_data_7[10] R E GATE D path_left_data_7[9] R G GATE F path_left_data_7[14] R I GATE H path_left_data_7[11] R K GATE J path_left_data_6[11] R M GATE L path_left_data_7[15] R O GATE N path_left_data_6[0] R Q GATE P path_left_data_6[1] R S GATE R path_left_data_6[2] R U GATE T path_left_data_6[3] R W GATE V path_left_data_6[4] R Y GATE X path_left_data_6[5] R [ GATE Z path_left_data_6[6] R ] GATE \ path_left_data_7[7] R _ GATE ^ path_left_data_6[7] R a GATE ` path_right_data_6[12] R c GATE b path_right_data_6[4] R e GATE d path_right_data_7[6] R g GATE f path_right_data_7[5] R i GATE h path_right_data_7[4] R k GATE j path_right_data_7[3] R m GATE l path_right_data_7[1] R o GATE n path_right_data_7[0] R q GATE p path_right_data_7[12] R s GATE r path_right_data_6[6] R u GATE t path_right_data_6[5] R w GATE v path_right_data_6[2] R y GATE x path_right_data_6[1] R { GATE z path_right_data_6[0] R } GATE | path_right_data_7[7] R GATE ~ path_right_data_6[7] R GATE path_right_data_7[14] R GATE path_right_data_6[14] R GATE path_right_data_7[11] R GATE path_right_data_6[11] R GATE path_right_data_7[13] R GATE path_right_data_6[13] R GATE path_right_data_7[15] R GATE path_right_data_6[15] R GATE right_0_m2_1[9] R GATE right_0_m2_2[9] R GATE path_right_data_6[8] R GATE path_right_data_7[8] R GATE PC_9[12] R GATE PC_9[14] R GATE PC_9[11] R GATE PC_9[13] R GATE PC_9[15] R GATE PC_9[10] R GATE PC_9[9] R GATE PC_9[8] R GATE path_left_data_7[2] R GATE path_left_data_6[10] R GATE path_left_data_6[9] R GATE path_left_data_6[14] R GATE path_left_data_6[15] R GATE path_right_data_7[2] R GATE path_right_data_6[3] R GATE path_right_data_7[10] R GATE path_right_data_6[10] R GATE overflow_out GATE q_out_3[14] GATE q_out_3[13] GATE q_out_3[12] GATE q_out_3[11] GATE Ā q_out_3[10] GATE ƀ
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state_o[2] state_o_pad[1]
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q_out_3[9] GATE Ȁ
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state_o[1] state_o_pad[0]
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q_out_3[8] GATE ʀ q_out_3[15] GATE ̀ q_out[0] GATE q_out[1] GATE Ѐ q_out[2] GATE Ҁ q_out[3] GATE Ԁ q_out[4] GATE ր q_out[5] GATE q_out[6] GATE ڀ q_out[7] GATE ܀ un1_state_104_i_o4_RNI188S5 ' GATE ހ datamux_o_dest[1] ' GATE datamux_o_dest[2] ' GATE datamux_o_dest[3] ' GATE datamux_o_dest[6] ' GATE datamux_o_dest[7] ' GATE datamux_o_dest[15] ' GATE CCRo[1] ' GATE
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state_o[0] data_io_pad[7]
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q_out_4[7] ' GATE
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data_io[7] data_io_pad[6]
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q_out_5[5] ' GATE
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data_io[6] data_io_pad[5]
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q_out_5[6] ' GATE CCRo[0] ' GATE
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data_io[5] data_io_pad[4]
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q_out_5[7] ' GATE
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data_io[4] data_io_pad[3]
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q_out_4[0] ' GATE
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data_io[3] data_io_pad[2]
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q_out_5[1] ' GATE
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data_io[2] data_io_pad[1]
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q_out_5[2] ' GATE
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data_io[1] cen_o_pad cen_o wen_o_pad wen_o oen_o_pad oen_o addr_o_pad[15]
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q_out_5[3] ' GATE
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addr_o[15] addr_o_pad[14]
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q_out_4[1] ' GATE
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addr_o[14] addr_o_pad[13]
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q_out_4[2] ' GATE
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addr_o[13] addr_o_pad[12]
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q_out_4[3] ' GATE
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addr_o[12] addr_o_pad[11]
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q_out_4[5] ' GATE
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addr_o[11] addr_o_pad[10]
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q_out_4[6] ' GATE CCRo[4] ' GATE
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addr_o[10]
addr_o_pad[9] addr_o[9]
addr_o_pad[8] addr_o[8]
addr_o_pad[7] addr_o[7]
addr_o_pad[6] addr_o[6]
addr_o_pad[5] addr_o[5]
addr_o_pad[4] addr_o[4]
addr_o_pad[3] addr_o[3]
addr_o_pad[2] addr_o[2]
addr_o_pad[1] addr_o[1]
addr_o_pad[0] addr_o[0] reset_o_pad reset_o textctrl/SLICE_0 SLICE R23C26D )
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v8_0 '
GATE
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! " # $ % & ' ( MMODE:CCU2 F0:F CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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q_out_1[4] ' GATE c8_1 ' GATE q_out[4] ' GATE datamux_o_dest[4] ' GATE k_pp_regs_cnsts2 k_pp_regs_cnst_sn_m9 mode_4_i_a5_2_0[0] mode_4_i_RNO[0] state_cnst_i_5_RNO_3[5] state_cnst_i_5_RNO_1[5] dest_reg7_0 un1_postbyte0_16 path_left_addr14_0 un1_postbyte0_14 dest_reg_cnst_i_1[0] dest_reg_cnst_i_a2[0] un1_eapostbyte_12 S un1_eapostbyte_16_sn_m13_0 S ACCB22_RNIJAPT1 R ACCB22_RNIH4141 R
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textctrl/SLICE_1 SLICE R23C26C KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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k_ofslo[0] P
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textctrl/SLICE_2 SLICE R23C26B )
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k_ofslo[1] P right_reg_1_RNI2TRT_0[0] R right_reg_1_RNIBIAC2[0] R s8 '
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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+ ^ _
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textctrl/SLICE_3 SLICE R23C26A KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x5006::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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6
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textctrl/SLICE_4 SLICE R22C27D )
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8
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! " # $ % & ' ( RMODE:CCU2 F1:F F0:F CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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:
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textctrl/SLICE_5 SLICE R22C27C KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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;
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textctrl/SLICE_6 SLICE R22C27B )
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q_out[4] *
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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q_out_2[4] ' CCRo_am_RNO[0] ' CCRo_am_RNO_0[0] ' visible_2_i_a2 visible_2_i_a2_3 vsync_cnt_RNIO6BM[7] un2_vsyncrlto10_i_a2 un1_state_47 un1_state_66
cond_taken_13 vff_9_u R next_state_2_sqmuxa_1_RNIQV8I8 next_state_2_sqmuxa_1 un1_k_pp_regs_4_sqmuxa k_pp_regs_4_sqmuxa_1 un1_state59_4_RNIP1BA3 un1_k_pp_regs_8_RNIP83O2 state_32_0_iv_RNO_4[3] un1_state_24_1_RNIQHT21 un1_postbyte0_2_1_RNI8Q1Q[0] ׀ alu_opcode_1_f0_0_RNO[2] ׀ alu_opcode_4_m_0[4] ׀ alu_opcode_2_4_0_.m65 ׀ alu_opcode_2_4_0_.m10 ׀ alu_opcode_2_4_0_.m9 ׀ alu_opcode_2_4_0_.m41_i_m2 ׀ alu_opcode_2_4_0_.m40 ׀ dec_alu_right_path_mod_i[1] ׀ -datamux_o_alu_in_right_path_data_cnst_i_o2[1] alu_opcode_1_f0_0_RNO_1[1] ׀ alu_opcode_1_f0_0_a2_4_2[1] ׀ alu_opcode_1_f0_0_a2_2_1[3] ׀ alu_opcode_1_f0_0_RNO[3] ׀ state_32_iv_RNO_5[0] state_32_iv_RNO_2[0] un1_state_64 un1_state_50_1_RNI7CBD1 state_cnst_0_o15[1] state_cnst_i_a2_3[0]
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textctrl/SLICE_7 SLICE R22C27A )
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ofs16_0_o2 un1_dec_o_ea_ofs8_1 S mode_4_0_1_RNO[1]
mode_4_0_1[1] optype_3_2_0_.m7 optype_3_2_0_.m10 mode78 path_left_addr13 state_cnst_i_a2[5] state_cnst_i_5_RNO_0[5] state_cnst_i_a2_5[0] state_cnst_i_3_RNO[4] R dest_reg_cnst_i_a2_2[1] dest_reg_0_sqmuxa_2_i_0_2 un1_state_16_1_RNINUTA1 un1_state_23_1_RNIQNBF2 path_left_addr_cnst_i_1_RNO[2] state_7_sqmuxa_1_8 state82_RNIK9482 state82_RNI5IM34 state59_RNIUQAG1 state_RNIHO3N2[1] P
un1_state_126 un1_state_50_1_RNIMU2E1 un1_regs_o_su_iv_0[0] un1_k_cpu_addr_1_axb_0 P dest_reg_cnst_i_0[3] dest_reg_cnst_i_0_RNO[3] state57_RNI81VK1[0] un1_state_85_RNI07AH3 R k_cpu_data_o_1_sqmuxa un1_k_cpu_addr_4_sqmuxa S path_left_addr_cnst_0_a5_1[0] path_left_addr_cnst_i_o2[3] un1_state_108_1_1 un1_state_108_1_a7_0 À un1_state_108_1_2 un1_state_108_1_a7_1 À path_left_addr_cnst_0_0[0] path_left_addr_cnst_0_a5[0] path_right_addr_cnst_i_o2_0[1] path_right_addr_cnst_i_m3[1] state_cnst_i_a2_4_RNIBO4I2[0] state_RNI7LMJ1[1] P un1_k_cpu_addr_0_sqmuxa un1_k_cpu_addr_0_sqmuxa_1 state_cnst_0_6[1] S state_cnst_0_4[1] S SS_0_sqmuxa_RNO R right_reg_1[3] R
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! " # $ % & ' ( KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x3006::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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IX_pipe_75 R
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textctrl/SLICE_8 SLICE R22C26D )
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IX_pipe_77 R
DP_1_sqmuxa_0 R un1_k_pp_active_reg P k_opcode[2] P k_opcode[3] P
IX_1_sqmuxa_2 R datamux_o_dest_reg_addr[2] P DP_pipe_6 R DP_pipe_7 R path_left_data_sn_m4 R "datamux_o_alu_in_left_path_addr[2] P SU_1_sqmuxa_3_RNO R datamux_o_dest_reg_addr[0] P
ACCA_RNO_0[1] R
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! " # $ % & ' ( MMODE:CCU2 F1:F F0:F CCU2::S0=0x500C,S1=0x500C::A0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2
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un1_ACCB47 R
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WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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k_memhi[4] P
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textctrl/SLICE_9 SLICE R22C26C PMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x300A::C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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k_memhi[5] P
ACCA_RNO_0[0] R
ACCA_RNO_2[0] R
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textctrl/SLICE_10 SLICE R22C26B )
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k_memhi[2] P
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! " # $ % & ' ( FMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5096,S1=0x3006::D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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k_memhi[3] P path_right_data[2] R N_610_i_i_m2 R state_cnst_i_5[4] R state_cnst_i_4[4] R k_pp_active_reg_cnst_i_0[0] k_pp_active_reg_cnst_i_o5[0] un1_state_88_i_a7 À state_RNIC1ID2[4] P "un1_k_cpu_data_o_3_sqmuxa_RNIMUVE1 À un1_k_cpu_data_o_3_sqmuxa À state_3_sqmuxa_5_RNIE8SO9 À k_pp_regs_0_sqmuxa_2_RNI92L38 À
un1_q1620_1_0 À q1623 À overflow_out (
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textctrl/SLICE_11 SLICE R22C26A KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x5006::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2
WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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q_out_2[7] ( v8_2 ' v8_2_RNO ' q_out_sn_m13 ' v8_sn_m8 ' daa8h_r ' un3_daa8h_r_ac0_5 ' c8_0 ' cneg8_r_4 ' state_cnst_0_2_RNO[2] P state_cnst_0_a15_0_0[2] P un1_k_pp_regs_1_sqmuxa P k_pp_regs_7_sqmuxa_1 P video_en_RNIFLVI video_en bios_en_RNIM1KK bios_en visible_2_i_o3_2_RNI1OT71 un6_visiblelto10_0_o2 hsync_cnt_RNI0OA21[9] hsync_cnt_RNIUTER[5] hsync_cnt_RNIHEU22[0] x_cnt5_x_8_0_RNI3PBE1 tshift_1_sqmuxa_0_a2 visible_2_i_o3 "vsync_cnt_2_sqmuxa_i_0_a2_RNISLI62 line_cnt_RNIMPG01[3] "vsync_cnt_2_sqmuxa_i_0_a2_RNI6S161 vsync_cnt_RNI2J9K_0[0] un7_hsyncrlto10_i_a3_0_RNIP5HM un7_hsyncrlto10_i_a3_0 vsync_cnt_2_sqmuxa_i_0 vsync_cnt_2_sqmuxa_i_0_o3 vsync_cnt_0_sqmuxa_0_a3 vsync_cnt_2_sqmuxa_i_0_a2 visible_2_i_a2_2 visible_2_i_a2_4 vsync_cnt_0_sqmuxa_0_a3_RNO vsync_cnt_RNI2J9K[0] redr9_15 redr9_12 visible_2_i_o3_2 hsync_cnt_RNI0OA21_0[9] visible_2_i_a3 visible_2_i_a2_0 redr9_14 redr9_3 vsync_cnt_0_sqmuxa_0_o2 vsync_cnt_0_sqmuxa_0_o2_RNIE8G71 k_pp_regs_2_sqmuxa un1_state_88_i_o4_0_RNIDRP12 À state_32_0_iv_RNO_6[3] state133 state192lto7_4_RNIK14L1 un1_state_88_i_o4_0 À state_32_0_iv_RNO_2[3] state_cnst_i_a2_2[0] P k_pp_regs_5_sqmuxa_1_RNIUBQ6A k_pp_regs_6_sqmuxa_1_RNI0OJM3 state_32_0_iv_RNO_0[3] state_cnst_i_o2_1[3] S next_state_0_sqmuxa_4_RNIMOT3B state81_RNILMFK state_32_0_iv_RNO[3] state_cnst_i_o2_RNIME5R[4] P next_state_0_sqmuxa_4 un1_k_write_exg9 un1_state59_14_RNI6NFEA un1_state_37 À k_pp_regs_25_bm_RNO[7] state81 state_32_0_iv_RNO_1[3] un1_state_13_1_RNIPDP11 k_pp_regs_5_sqmuxa_1_RNI29I34 k_pp_regs_3_sqmuxa un1_state59_14 un1_state59_10 k_pp_regs_5_sqmuxa_1
un1_state59_6 state_32_0_iv_1[3] un1_state_1_sqmuxa_2 k_pp_regs_2_sqmuxa_2 un1_state59 un1_state_76_RNI6G423 k_cpu_oe_cnv P state_32_0_iv_RNO_3[3] optype_3_2_0_.m3 k_pp_regs_6_sqmuxa un1_k_pp_regs_8 state_32_0_iv_RNO_5[3] un1_state_13_1 cond_taken67 op[6]
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textctrl/SLICE_12 SLICE R24C28D )
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un1_op_3_3 op[2]
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0xF008,S1=0x3008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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un1_op_4_4 op[0] k_write_pc9 k_write_pc_0_sqmuxa k_pp_regs_25_bm_RNO_1[7] un1_k_opcode_3_3 state_32_0_iv_RNO_7[3] state_cnst_i_o2[4] P G_9 k_new_pc29_RNILU7S1 P state192lto7_4 k_pp_active_reg_cnst_0_1_RNO[3] un1_state_15_1 k_cpu_oe_3_0 P un1_state_76 un1_state_7_1_RNIPAL21 un1_state59_16 state_cnst_0_a2[2] À alu_opcode_1_f0_0_RNO_0[3] ׀ alu_opcode_1_f0_0_o2_0[3] ׀ alu_opcode102_1_RNI7TQL[0] ׀ optype_0_f0[0] alu_opcode102_1_RNITBBQ[0] ׀ alu_opcode_1_f0_0_a2_1[3] ׀ "alu_opcode_1_f0_0_o2_0_RNIPGPL1[3] ׀ 'datamux_o_alu_in_right_path_data_RNO[5] S alu_opcode_4_1_f0[0] ׀ mode79_5 alu_opcode_1_f0_0_RNO[1] ׀ dest_reg_0_sqmuxa_2_i_a2_4 alu_opcode_2_4_0_.m55 ׀ alu_opcode_2_4_0_.m51 ׀ alu_opcode_1_f0_0_a2_2_0[1] ׀ alu_opcode_2_4_0_.m33 ׀ alu_opcode_2_4_0_.m37 ׀ alu_opcode_2_4_0_.m35 ׀ alu_opcode103[0] ׀ mode76_5 un1_postbyte0_1[0] ׀ un1_postbyte0_20_5 un1_postbyte0_2_2[0] ׀ un1_postbyte0_17 alu_opcode103_2[0] ׀ un1_postbyte0_6 k_write_post_incdec_7_0 un1_eamem_addr63_3_1 S state_cnst_0_a2_6[1] state_cnst_0_11[1] S state_cnst_0_a2_4[1] state_cnst_i_8[4] R noofs7_2_RNIQBE91[0] noofs7_2_RNIK1DB[0] state_32_iv_RNO_10[0] state_cnst_i_o15[0] state_cnst_0_a15_0_0[1] state_cnst_0_9[1] S k_ofshi_1_sqmuxa_RNIHOKL
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) NGID1
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k_new_pc29 P state_32_iv_RNO[0] un1_next_state_1_sqmuxa_1 state_32_iv_RNO_0[0]
un1_state_122 k_pp_regs60_RNI18KD3 k_clear_e_3_1_RNIUBNG1 un1_state_87_1_0_RNIGMH52 un1_state_13_1_RNIS9ST state_32_iv_RNO_3[0] state_32_iv_RNO_6[0] k_eahi_0_sqmuxa_2 mode_cnst_1_i_a2_RNIA56C5[1] k_pp_regs60 un1_next_state_3_sqmuxa P state_32_iv_RNO_1[0] dest_reg44_3_0_a2_RNIQG1Q state_cnst_0_o2_0[1] state_cnst_0_6[2] P state_32_iv_RNO_4[0] un1_state_104_i_o4_RNIMB951 ' state83_1 state_7_sqmuxa_1 state_32_iv_1[0] state_32_iv_0[0] state_32_iv_RNO_7[0] state_32_iv_RNO_9[0] state_32_iv_RNO_8[0] state_cnst_0_a15_4_1[2] P un1_k_forced_mem_size41 k_write_post_incdec_7_0_0 k_ofshi_1_sqmuxa
un1_state_8_2 P state_cnst_0_o2_2[1] state128 P un1_state_87_1_0 k_clear_e_3_3_RNIH2LI1 k_eahi_11_iv_0_5_796_i_0 DP_7[1] R k_eahi_11_iv_0_5_i_a4_1_0 k_eahi_11_iv_0_2_859_i_0 S noofs10_1[0] un1_eapostbyte_7[0] S state_cnst_i_o2_7[0] state_cnst_0_0[2] P k_eahi_11_iv_0_5_i_a4_0_0 state_RNIN8K02[0] P
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* NGID2
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mode52_RNO mode52 use_s_1_RNO use_s_1 mode76_RNIMEVJ mode76 optype_3_2_0_.m8 optype_3_2_0_.m3_1 optype_3_2_0_.m11 optype_3_2_0_.m12 mode88_1_RNITJC03[0] state_cnst_0_7[2] P mode_4_i_RNILO6N[0] mode_4_i[0] mode_4_0_RNI1HMO[2]
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textctrl/SLICE_13 SLICE R24C28C )
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un1_mode93 optype_3_2_0_.N_19_m %datamux_o_alu_in_left_path_data_sn_m1 optype_0_f0[1] datamux_o_dest_sn_m1 R mode79_RNIFNDU1 mode79_RNI914D1 mode_4_i_a5_1[0] state_3_sqmuxa_1_i mode_4_0_a5_0[1] mode_4_0_a5_0_1[1] mode_8_sqmuxa_1_93_0 un1_postbyte0_20_1 optype_3_2_0_.m15 optype_3_2_0_.m5 mode79 path_left_addr14
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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mode53_1_i state59 mode_4_i_o5_1[0] k_write_exg_1_sqmuxa_RNO mode79_3 path_left_addr_2_1_.m5 dest_reg_3_1_RNO[1] dest_reg_3_1[1] un1_state_14_1
k_set_e_3_RNO R dest_reg_cnst_i_a2_0_a2[2] dest_reg_cnst_i_1_1[2] un1_dest_reg44_1_i_2_RNO un1_dest_reg44_1_i_2 un1_state_7_1_RNIOA7F1
un1_state_7_1 un1_state_29_2_RNIS51B1 k_inc_pc_3_0 P state_cnst_i_o2_2_RNIAFHA1[5] state_cnst_i_o2_2[5] state_cnst_i_5_RNO[5] un1_state_24_1 un1_state_16_1_RNI4KA21 un1_k_cpu_addr_2_sqmuxa_tz_1 À state57_1_RNIHL8H1[0] state_cnst_i_7[4] R state_cnst_i_8_RNO_0[5] state_cnst_i_8[5] dest_reg_cnst_i_a2_3[0] dest_reg_0_sqmuxa_2_i_0_3 dest_reg_0_sqmuxa_2_i_o2 un1_dest_reg44_1_i un1_state_15_2_RNI30NR1_0 un1_state_15_2 un1_state_23_1_RNIH8ID2 next_mem_state_8_0_a2_743_i_1 R un1_state_12_1_RNISHJN
un1_state_7_3 À state_cnst_i_5_RNO_2[5] state_cnst_i_5[5] state_cnst_i_o2_2_RNISJNF3[5] state_cnst_0_a15_4[1] S path_left_addr13_RNIKVIP path_right_addr_3_sqmuxa un1_state_33_RNI4UEP2 k_mem_dest_RNO[0] P un1_state_7_1_RNIQL6M
un1_state_7_2 À state_cnst_i_a15_2[0] state_cnst_i_a2_7[0] k_memhi_0_sqmuxa_RNIN4F02 k_memhi_0_sqmuxa un1_cpu_reset_13 k_cpu_addr_1_sqmuxa À state_cnst_i_9[5] state_RNI6KMJ1_0[0] P state_cnst_i_a15_10[0] state_cnst_0_o2_0[2] P next_state_cnst_i_1[0] next_state21 state_cnst_i_a15_0[5] un1_state_16_2 next_state_10_RNO[0]
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' NGID1
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state57[0] state_cnst_i_6[5] state_cnst_0_a2_2[1] S
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( NGID2
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k_new_pc25 un1_k_memlo[15] R state_cnst_i_o2[3] state_cnst_0_6_RNO[2] P state_cnst_i_a2_12[0] state_cnst_0_a15_12[1] S !path_left_addr_1_sqmuxa_2_RNIKPUD path_left_addr_1_sqmuxa_2 state_32_iv_2[5] state_32_iv_0[5] path_left_addr_cnst_i_1[3] path_left_addr_cnst_i_0[3] path_right_addr_am_RNO[0] &path_right_addr_cnst_0_a2_1_RNI402J[0] dest_reg_0_sqmuxa_2_i_0_RNI6G53 dest_reg_0_sqmuxa_2_i_0 un1_cpu_reset_13_1 un1_state_108_1 un1_postbyte0_33_1 un1_postbyte0_33_1_x2 state_cnst_i_a2[4] state_cnst_i_a15_10[4] R dest_reg_cnst_i_3[2] dest_reg_cnst_i_1[2] path_right_addr_cnst_0_0[0] path_right_addr_cnst_0_a2_1[0] path_left_addr_cnst_i_1[2] dest_reg_0_sqmuxa_2_i_a2_7 un1_state_23_1_RNI2Q3P1 state_RNI6DRP[3] P dest_reg_cnst_i_2[1] state133_2_i_o2 À dest_reg_cnst_i_0[0] dest_reg_cnst_i_a5_0_a2[0] un1_state_33 un1_state_73_3 P dest_reg_0_sqmuxa_2_i_a2_2 dest_reg48_5_0_a2 un1_state_108_1_a7 un1_state_27_2 dest_reg_2_i_a2[0] un1_postbyte0_34_1_a4_1 k_write_exg10_0
k_write_exg10 un1_state_39_2 un1_state_88_i_o4_0_RNIPQU51 À un1_state_12_2 state_32_0_iv_0_568_i_0 R state_cnst_i_a2_4[0] state_cnst_0_1[1] S un1_state_16_1 un1_state_51 À
k_clear_e_3_3 un1_state_21 P un1_state_36_1 k_cpu_oe_3_3 P un1_state_23_1 un1_state_35 state_cnst_i_8_RNO_1[5] state_cnst_i_8_RNO[5] state_cnst_0_a2_9[1] S state_cnst_0_8[1] S eamem_addr_o_cry_5_0_RNIUIQF1 S !datamux_o_alu_in_left_path_data16 P eamem_addr_o_axb_0_RNIINF81 S eamem_addr_o_axb_0 S state_cnst_i_o2_4_RNI9AOJ1[3] S state_cnst_i_o2_4[3] S k_cpu_addr_28_iv_0[0] S un1_k_cpu_addr_2_sqmuxa À k_cpu_addr_28_iv_0[7] S PC_9[7] R k_cpu_addr_28_iv_0[8] S reg_su[8] R k_cpu_addr_28_iv_0[12] S
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textctrl/SLICE_14 SLICE R24C28B )
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reg_su[12] R k_cpu_addr_28_iv_0[14] S
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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reg_su[14] R datamux_o_dest[8] S q_out[8] À datamux_o_dest[11] S q_out[11] À datamux_o_dest[13] S q_out[13] À k_new_pc28_RNILK8D5 S
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% NGID1
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k_new_pc28 S state_32_iv_2[1] S un1_state_101_0 P k_new_pc26_1_i_RNI1GUPD S k_mul_cnt_RNI37038 P k_new_pc_0[11] S DP_7[3] R k_new_pc_0[13] S DP_7[5] R
k_new_pc_0[8] S DP_7[0] R un1_k_p2_valid6_1 S k_p2_valid7 P un1_k_p2_valid6_1_0 S k_p2_valid6 P un1_pc_0[6] S PC_9[6] R un1_pc_0[5] S PC_9[5] R un1_pc_0[4] S PC_9[4] R un1_pc_0[3] S PC_9[3] R un1_pc_0[2] S PC_9[2] R un1_pc_0[1] S PC_9[1] R un1_pc_0[0] S PC_9[0] R k_eahi_11_iv_0_0_901_i_0 S DP_7[6] R un1_eapostbyte_16_i_m2_1[9] S ACCB_9[7] R state_cnst_0_0[1] S un1_state_38_1 À k_cpu_addr_28_iv_1_0[12] S un1_k_cpu_addr_2_sqmuxa_1 À datamux_o_dest_0[8] S datamux_o_dest13 R k_set_e_3_2_RNO R k_set_e_3_2 R ACCB_0_sqmuxa_1_RNO R ACCB_0_sqmuxa_1 R
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& NGID2
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k_ofslo[4] P
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textctrl/SLICE_15 SLICE R24C28A )
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k_ofslo[5] P un1_state_85_2_RNO R un1_state_85_2 R SS_0_sqmuxa_RNO_0 R SS_0_sqmuxa R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON Q1:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x300A,S1=0xF008::A0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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IX_pipe_78 R IX_pipe_8 R IX_1_sqmuxa_1_2 R IX_0_sqmuxa_1_1_RNI2C2L3 R DP_pipe_3 R DP_pipe_4 R right_reg_1_RNI2TRT[0] R right_reg_1[0] R state_cnst_i_a15_6[4] R state_cnst_i_7_RNIPETR1[4] R
ACCA_RNO_1[0] R datamux_o_dest_reg_addr[1] P
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$ NGID1
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k_ofshi[2] P
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textctrl/SLICE_16 SLICE R22C28D )
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k_ofshi[3] P SU_207_m3 R SU_0_sqmuxa_2_RNI4AD61 R SU_208_m3 R SU_16[1] R SU_209_m3 R SU_16[2] R SU_210_m3 R SU_16[3] R SU_211_m3 R SU_16[4] R SU_212_m3 R SU_16[5] R SU_213_m3 R SU_16[6] R SU_214_m3 R SU_16[7] R SS_223_m3 R SS_0_sqmuxa_RNIGPUT R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0xF008,S1=0x3008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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IY_pipe_70 R
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" NGID1
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IY_pipe_75 R SS_224_m3 R SS_16[1] R
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# NGID2
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PC_pipe_23 R
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textctrl/SLICE_17 SLICE R22C28C )
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PC_pipe_28 R SS_225_m3 R SS_16[2] R PC_pipe_3 R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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PC_pipe_33 R SS_226_m3 R SS_16[3] R
|
NGID1
|
PC_pipe_37 R
|
! NGID2
|
PC_pipe_38 R SS_227_m3 R SS_16[4] R
|
textctrl/SLICE_18 SLICE R22C28B )
|
PC_pipe_42 R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ! WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
PC_pipe_43 R SS_228_m3 R SS_16[5] R
|
NGID1
|
PC_pipe_47 R
|
NGID2
|
PC_pipe_48 R SS_229_m3 R SS_16[6] R
|
textctrl/SLICE_19 SLICE R22C28A )
|
PC_pipe_52 R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON Q1:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x300A,S1=0xF008::A0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 " REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 # WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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PC_pipe_53 R SS_230_m3 R SS_16[7] R
|
NGID1
|
PC_pipe_57 R
|
textctrl/SLICE_20 SLICE R24C32B )
|
PC_pipe_58 R SU_215_m3 R SU_16[8] R SU_216_m3 R SU_16[9] R SU_217_m3 R SU_16[10] R SU_218_m3 R SU_16[11] R SU_219_m3 R SU_16[12] R SU_220_m3 R SU_16[13] R SU_221_m3 R SU_16[14] R SU_222_m3 R SU_16[15] R SS_231_m3 R SS_16[8] R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0xF008,S1=0x3008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 % REG0 $ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 & WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
PC_pipe_62 R
|
4 NGID1
|
PC_pipe_63 R SS_232_m3 R SS_16[9] R
|
5 NGID2
|
PC_pipe_67 R
|
textctrl/SLICE_21 SLICE R24C32A )
|
PC_pipe_68 R SS_233_m3 R SS_16[10] R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 ( REG0 ' Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ) WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
PC_pipe_72 R
|
2 NGID1
|
PC_pipe_73 R SS_234_m3 R SS_16[11] R
|
3 NGID2
|
PC_pipe_77 R
|
textctrl/SLICE_22 SLICE R24C31D )
|
PC_pipe_78 R SS_235_m3 R SS_16[12] R PC_pipe_8 R SS_236_m3 R SS_16[13] R SS_237_m3 R SS_16[14] R SS_238_m3 R SS_16[15] R
ACCA_RNO_0[2] R un1_write_reg_addr_2 R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 + REG0 * Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 , WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
k_memhi[6] P
|
0 NGID1
|
k_memhi[7] P
ACCA_RNO_0[3] R
ACCA_RNO_1[3] R
|
1 NGID2
|
k_memlo[0] P
|
textctrl/SLICE_23 SLICE R24C31C )
|
k_memlo[1] P
ACCA_RNO_0[4] R
ACCA_RNO_1[4] R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 . REG0 - Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 / WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
k_memlo[2] P
|
. NGID1
|
k_memlo[3] P
ACCA_RNO_0[5] R
ACCA_RNO_1[5] R
|
/ NGID2
|
k_memlo[4] P
|
textctrl/SLICE_24 SLICE R24C31B )
|
k_memlo[5] P
ACCA_RNO_0[6] R
ACCA_RNO_1[6] R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 1 REG0 0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
k_memlo[6] P
|
, NGID1
|
k_memlo[7] P
ACCA_RNO_0[7] R
ACCA_RNO_1[7] R
|
- NGID2
|
k_ofshi[0] P
|
textctrl/SLICE_25 SLICE R24C31A )
|
k_ofshi[1] P
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON Q1:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x300A,S1=0xF008::A0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 3 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 4 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
SU_16_0[1] R SU_2_sqmuxa R
|
+ NGID1
|
SS_16_0[1] R SS_3_sqmuxa R
|
textctrl/SLICE_26 SLICE R23C32D MODE:CCU2 REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0x5002,S1=0x300A::B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 5 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 6 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
IY_pipe_25 R
|
k NGID1
|
IY_pipe_30 R eflag_0_sqmuxa_0_RNIOVLR R eflag_0_sqmuxa_0 R k_cpu_addr_28_iv_0[3] R reg_su[3] R intff_pipe_3 R k_cpu_addr_28_iv_0[9] R reg_su_i_m2[9] R datamux_o_dest[9] R q_out[9] À right_cry_3_0_RNO_0 R path_right_data[4] R right_cry_9_0_RNO_0 R path_right_data[10] R ACCB22_RNIDCT43 R ACCB22 R
|
textctrl/SLICE_27 SLICE R23C32C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF002,S1=0xF002::B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 8 REG0 7 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 9 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
k_ofshi[6] P
|
i NGID1
|
k_ofshi[7] P ACCB_0_sqmuxa_1_RNILJP21 R ACCB46 R
|
j NGID2
|
k_ofslo[2] P
|
textctrl/SLICE_28 SLICE R23C32B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF002,S1=0xF002::B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 ; REG0 : Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 < WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
k_ofslo[3] P path_left_data[2] R path_left_data_sn_m7 R path_left_data[15] R path_left_data_sn_m6 R path_right_data[15] R path_right_data_sn_m6 R PC_1_sqmuxa_2_RNIK4633 R
PC_1_sqmuxa_2 R
|
g NGID1
|
IX_pipe_60 R
|
h NGID2
|
IX_pipe_62 R k_pp_active_reg_cnst_0_a5[1] R k_pp_active_reg_cnst_i_o3[0]
SU_0_sqmuxa_2 R
SU_1_sqmuxa_2 R
SS_1_sqmuxa_1 R datamux_o_dest_reg_addr[3] P
|
textctrl/SLICE_29 SLICE R23C32A MODE:CCU2 REG1:#ON Q1:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x300A,S1=0xF002::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 = REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 > WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
IY_pipe_60 R
|
f NGID1
|
IY_pipe_65 R k_pp_active_reg_cnst_0_0[1] R k_pp_active_reg_cnst_0_2[1] R reg_su[2] R k_cpu_addr_28_iv_0[2] ' reg_su_i_m2[1] R k_cpu_addr_28_iv_0[1] P
|
textctrl/SLICE_30 SLICE R25C30B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0xF008,S1=0x5008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 @ REG0 ? Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 A WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
reg_su[11] R k_cpu_addr_28_iv_0[11] '
|
T NGID1
|
reg_su[13] R k_cpu_addr_28_iv_0[13] ' reg_su[4] R k_cpu_addr_28_iv_0[4] '
|
U NGID2
|
reg_su[15] R un1_regs_o_su_iv[15] ' reg_su[6] R k_cpu_addr_28_iv_0[6] '
|
textctrl/SLICE_31 SLICE R25C30A )
|
reg_su[10] R k_cpu_addr_28_iv_0[10] ' reg_su[5] R k_cpu_addr_28_iv_0[5] ' path_left_data_0[2] R "datamux_o_alu_in_left_path_addr[0] P cff_1_sqmuxa_2 R ACCB22_RNII5141 R SU_1_sqmuxa_4_1 R right_reg_1[2] R DP_1_sqmuxa_1_1_0 R right_reg_1[1] R k_opcode[4] P k_opcode[5] P state_cnst_i_0[4] R state_cnst_i_m2[4] P path_right_data_0[4] R ACCB_9[4] R path_right_data_0[2] R ACCB_9[2] R IX_10[0] R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 C REG0 B Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 D WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
IX_10_0[0] R
k_postbyte[4] P
k_postbyte[5] P IY_10[12] R IY_10_0[12] R
|
R NGID1
|
IX_pipe_18 R IX_pipe_2 R IY_10[7] R
|
S NGID2
|
IY_10_0[7] R
|
textctrl/SLICE_32 SLICE R25C29D )
|
IX_pipe_48 R IX_pipe_5 R IY_10[6] R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 F REG0 E Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 G WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
IY_10_0[6] R
|
P NGID1
|
IX_pipe_45 R
|
Q NGID2
|
IX_pipe_47 R IY_10[5] R
|
textctrl/SLICE_33 SLICE R25C29C )
|
IY_10_0[5] R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 I REG0 H Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 J WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
IX_pipe_42 R
|
N NGID1
|
IX_pipe_43 R IY_10[4] R
|
O NGID2
|
IY_10_0[4] R
|
textctrl/SLICE_34 SLICE R25C29B )
|
IX_pipe_38 R
|
! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 L REG0 K Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 M WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
IX_pipe_40 R IY_10[3] R
|
L NGID1
|
IY_10_0[3] R
|
M NGID2
|
IX_pipe_35 R
|
textctrl/SLICE_35 SLICE R25C29A )
|
IX_pipe_37 R IY_10[2] R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0::::SD=0 Q1:Q Q0:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF FCO:FCO CCU2::S0=0x300A,S1=0xF008::A0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 O REG0 N Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 P WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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IY_10_0[2] R
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^ NGID1
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IX_pipe_32 R
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K NGID2
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IX_pipe_33 R IY_10[1] R
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cpu0/SLICE_36 SLICE R10C24A )
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IY_10_0[1] R IX_pipe_3 R
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! " # $ % & ' ( AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x22D7::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 R WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/ea/SLICE_37 SLICE R19C20A CMODE:CCU2 F0:F CCU2::S0=0x5056,S1=0x300A::D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 U WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 >cpu0/regs/ea/SLICE_38 SLICE R19C19D )
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IX_pipe_30 R IY_10[0] R
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3036,S1=0x3036::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 V WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ?cpu0/regs/ea/SLICE_39 SLICE R19C19C )
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IY_10_0[0] R DP_pipe_9 R IX_10[1] R
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3036,S1=0x3036::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 W WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @cpu0/regs/ea/SLICE_40 SLICE R19C19B )
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IX_10_0[1] R ACCB_pipe_21 R ACCB_pipe_22 R IX_10[2] R
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3036,S1=0x5056::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 X WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Acpu0/regs/ea/SLICE_41 SLICE R19C19A 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x222D,S1=0x7778 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 Y WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Bcpu0/regs/ea/SLICE_42 SLICE R19C18D )
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IX_10_0[2] R ACCB_pipe_3 R ACCB_pipe_4 R IX_10[3] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7787,S1=0x222D 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 Z WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ccpu0/regs/ea/SLICE_43 SLICE R19C18C 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x222D,S1=0x7778 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 [ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Dcpu0/regs/ea/SLICE_44 SLICE R19C18B )
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IX_10_0[3] R ACCB_pipe_6 R ACCB_pipe_7 R IX_10[4] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7778,S1=0x7787 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 \ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ecpu0/regs/ea/SLICE_45 SLICE R19C18A AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x222D::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ] WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Fcpu0/regs/ea/SLICE_46 SLICE R18C20A HMODE:CCU2 F0:F CCU2::S0=0x5006,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ^ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Gcpu0/regs/ea/SLICE_47 SLICE R18C19D KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 _ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Hcpu0/regs/ea/SLICE_48 SLICE R18C19C )
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IX_10_0[4] R ACCB_pipe_9 R IX_10[5] R
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ` WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Icpu0/regs/ea/SLICE_49 SLICE R18C19B KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 a WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Jcpu0/regs/ea/SLICE_50 SLICE R18C19A )
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IX_10_0[5] R DP_pipe_1 R
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 b WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Kcpu0/regs/ea/SLICE_51 SLICE R18C18D )
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DP_pipe_10 R IX_10[6] R
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 c WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Lcpu0/regs/ea/SLICE_52 SLICE R18C18C )
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IX_10_0[6] R
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 d WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Mcpu0/regs/ea/SLICE_53 SLICE R18C18B )
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DP_pipe_12 R
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! " # $ % & ' ( FMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5056,S1=0x3006::D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 e WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ncpu0/regs/ea/SLICE_54 SLICE R18C18A KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x5009::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 f WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ocpu0/regs/ea/SLICE_55 SLICE R22C24A )
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DP_pipe_13 R IX_10[7] R
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! " # $ % & ' ( CMODE:CCU2 F0:F CCU2::S0=0x306C,S1=0x300A::D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 g WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Pcpu0/regs/ea/SLICE_56 SLICE R22C23D )
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IX_10_0[7] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7B48,S1=0x7B48 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 h WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Qcpu0/regs/ea/SLICE_57 SLICE R22C23C )
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DP_pipe_15 R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7B48,S1=0x7B48 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 i WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Rcpu0/regs/ea/SLICE_58 SLICE R22C23B )
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DP_pipe_16 R IX_10[12] R IX_10_0[12] R ACCB_pipe_1 R ACCB_pipe_10 R IY_10[8] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7B48,S1=0x7B48 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 j WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Scpu0/regs/ea/SLICE_59 SLICE R22C23A 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x7D28 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 k WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Tcpu0/regs/ea/SLICE_60 SLICE R22C22D 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 l WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ucpu0/regs/ea/SLICE_61 SLICE R22C22C 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 m WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Vcpu0/regs/ea/SLICE_62 SLICE R22C22B 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 n WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Wcpu0/regs/ea/SLICE_63 SLICE R22C22A AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x72D8::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 o WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Xcpu0/regs/SLICE_64 SLICE R10C20A )
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IY_10_0[8] R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0x7087,S1=0x3093::D0=0,D1=0 4 MODE K1 K0 REG1 q REG0 p Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 r WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @ NGID1 A NGID2 cpu0/regs/SLICE_65 SLICE R10C19D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 t REG0 s Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 u WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 ? NGID2 cpu0/regs/SLICE_66 SLICE R10C19C )
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IX_pipe_50 R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 w REG0 v Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 x WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 < NGID1 = NGID2 cpu0/regs/SLICE_67 SLICE R10C19B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 z REG0 y Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 { WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 : NGID1 ; NGID2 cpu0/regs/SLICE_68 SLICE R10C19A )
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IX_pipe_52 R intff_9_u R intff_9_0 R hflag_pipe_3 R IX_10[14] R IX_10_0[14] R ACCB_pipe_15 R ACCB_pipe_16 R IY_10[14] R IY_10_0[14] R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 } REG0 | Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ~ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 8 NGID1 9 NGID2 cpu0/regs/SLICE_69 SLICE R10C18D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 6 NGID1 7 NGID2 cpu0/regs/SLICE_70 SLICE R10C18C )
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IX_pipe_23 R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 5 NGID2 cpu0/regs/SLICE_71 SLICE R10C18B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 2 NGID1 3 NGID2 cpu0/regs/SLICE_72 SLICE R10C18A )
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IX_pipe_25 R IX_10[11] R IX_10_0[11] R next_push_state[0] P IY_10[11] R IY_10_0[11] R
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! " # $ % & ' ( AMODE:CCU2 FCO:FCO CCU2::S0=0x500C,S1=0x50FE::B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_73 SLICE R11C20A )
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IX_pipe_15 R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0xD02D,S1=0x5059::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 P NGID1 Q NGID2 cpu0/regs/SLICE_74 SLICE R11C19D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 N NGID1 O NGID2 cpu0/regs/SLICE_75 SLICE R11C19C )
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IX_pipe_17 R IX_10[13] R IX_10_0[13] R ACCB_pipe_12 R ACCB_pipe_13 R IY_10[13] R IY_10_0[13] R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xD02D,S1=0xD02D::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 L NGID1 M NGID2 cpu0/regs/SLICE_76 SLICE R11C19B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 J NGID1 K NGID2 cpu0/regs/SLICE_77 SLICE R11C19A )
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IX_pipe_20 R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xD02D,S1=0xD02D::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 H NGID1 I NGID2 cpu0/regs/SLICE_78 SLICE R11C18D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 F NGID1 G NGID2 cpu0/regs/SLICE_79 SLICE R11C18C )
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IX_pipe_22 R IX_10[15] R IX_10_0[15] R ACCB_pipe_18 R ACCB_pipe_19 R eflag_11 R CCRo14_RNIN1HU ' IY_10[15] R IY_10_0[15] R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xD02D,S1=0xD02D::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 D NGID1 E NGID2 cpu0/regs/SLICE_80 SLICE R11C18B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 B NGID1 C NGID2 cpu0/regs/SLICE_81 SLICE R11C18A )
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IX_pipe_27 R
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! " # $ % & ' ( AMODE:CCU2 FCO:FCO CCU2::S0=0x500C,S1=0x30FE::B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_82 SLICE R19C15A )
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IX_pipe_28 R IX_10[10] R IX_10_0[10] R
k_postbyte[6] P
k_postbyte[7] P IY_10[10] R IY_10_0[10] R
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! " # $ % & ' ( CMODE:CCU2 F0:F CCU2::S0=0x30AC,S1=0x300A::D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_83 SLICE R19C14D )
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IX_pipe_12 R
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! " # $ % & ' ( UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x300A,S1=0x500C::B0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_84 SLICE R19C14C )
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IX_pipe_13 R IX_10[9] R
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! " # $ % & ' ( UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_85 SLICE R19C14B )
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IX_10_0[9] R
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! " # $ % & ' ( UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_86 SLICE R19C14A UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x300A,S1=0x300A::B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_87 SLICE R19C13D )
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DP_pipe_21 R
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! " # $ % & ' ( UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_88 SLICE R19C13C )
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DP_pipe_22 R IY_10[9] R
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! " # $ % & ' ( UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x500C,S1=0x500C::A0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_89 SLICE R19C13B )
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IY_10_0[9] R
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! " # $ % & ' ( UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x300A,S1=0x500C::B0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_90 SLICE R19C13A PMODE:CCU2 F1:F FCO:FCO CCU2::S0=0x300A,S1=0x300A::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/a16/SLICE_91 SLICE R10C16A )
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IX_pipe_53 R
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! " # $ % & ' ( CMODE:CCU2 F1:F F0:F CCU2::S0=0x30A5,S1=0x300F::D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Bcpu0/alu/alu16/a16/SLICE_92 SLICE R10C15D )
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IX_pipe_55 R IX_10[8] R
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x30A5,S1=0x30A5::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ccpu0/alu/alu16/a16/SLICE_93 SLICE R10C15C )
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IX_10_0[8] R
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x30A5,S1=0x30A5::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Dcpu0/alu/alu16/a16/SLICE_94 SLICE R10C15B )
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DP_pipe_18 R
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x30A5,S1=0x50C3::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ecpu0/alu/alu16/a16/SLICE_95 SLICE R10C15A FMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xA009,S1=0x50C3::C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Fcpu0/alu/alu16/a16/SLICE_96 SLICE R10C14D )
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DP_pipe_19 R cff_9_u R c8_2 ' SS_1_sqmuxa R SS_4_sqmuxa R
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xC009,S1=0xC009::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Gcpu0/alu/alu16/a16/SLICE_97 SLICE R10C14C )
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IY_pipe_50 R
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xC009,S1=0xC009::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Hcpu0/alu/alu16/a16/SLICE_98 SLICE R10C14B KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xA009,S1=0xA009::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Icpu0/alu/alu16/a16/SLICE_99 SLICE R10C14A )
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IY_pipe_55 R hflag_9_0 R q_out_5_bm_RNO[2] ' fflag_pipe_3 R DP_7[4] R k_new_pc_0[12] (
k_postbyte[0] P
k_postbyte[1] P DP_7[7] R k_new_pc_0[15] '
k_postbyte[2] P
k_postbyte[3] P DP_7[2] R k_new_pc_0[10] k_opcode[6] P k_opcode[7] P cff_9_0 R
q_out_1_0_239 Ā
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! " # $ % & ' ( FMODE:CCU2 FCO:FCO CCU2::S0=0x000A,S1=0xC009::A0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Jcpu0/alu/alu16/a16/SLICE_100 SLICE R6C16A )
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q_out_3[8] Ā
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! " # $ % & ' ( MMODE:CCU2 F1:F F0:F CCU2::S0=0x3006,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Kcpu0/alu/alu16/a16/SLICE_101 SLICE R6C15D )
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q_out_1[8] À
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Lcpu0/alu/alu16/a16/SLICE_102 SLICE R6C15C )
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q_out_3[9] Ā
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Mcpu0/alu/alu16/a16/SLICE_103 SLICE R6C15B KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ncpu0/alu/alu16/a16/SLICE_104 SLICE R6C15A )
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q_out_1[9] À q_out_3[10] Ā q_out_1[10] À q_out_3[11] Ā q_out_1[11] À q_out_3[12] Ā q_out_1[12] À q_out_3[13] Ā q_out_1[13] À q_out_3[14] Ā q_out_1[14] À q_out_3[15] Ā q_out_1[15] À carry_out_3 Ā c16_0 À k_pp_active_reg_cnst_0_2_RNO[2] k_pp_active_reg_cnst_0_2[2] datamux_o_dest[10] q_out[10] À k_pp_active_reg_cnst_0_a5_1[2] state192lto7_5 P pipe1_1_6_23_0 un20_pipe1[11] pipe1_1_6_13_0
un20_pipe1[9] pipe1_1_6_18_0 un20_pipe1[10]
pipe1_1_6_3_0
un20_pipe1[7]
pipe1_1_6_8_0
un20_pipe1[8] un1_k_cpu_data_o_3_sqmuxa_RNO À un1_state_19_0 À un1_state_18_2_RNINGR01 À un1_state_18_2 À z16_2 À q_out[14] À un1_state_75_RNISTJ21 À state_1_sqmuxa_9 À z16_2_13 À z16_2_10 À z16_2_7 À q_out[12] À z16_2_9 À q_out[15] À state_1_sqmuxa_9_RNIEM2I6 À un1_state_108_1_a7_0_1_RNIADGF3 À q_out_sn_m11 À q_out_sn_m9 À q_out_sn_m6 À q_out_sn_m5 À un1_k_cpu_addr_2_sqmuxa_tz_0 À un1_k_cpu_addr_2_sqmuxa_tz_0_RNO À q1620 À q1620_1 À q1621 À q1621_0 À q_out[7] *
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ocpu0/alu/alu16/a16/SLICE_105 SLICE R6C14D KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Pcpu0/alu/alu16/a16/SLICE_106 SLICE R6C14C )
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q_out_2[7] * half_c_out_2 (
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Qcpu0/alu/alu16/a16/SLICE_107 SLICE R6C14B KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Rcpu0/alu/alu16/a16/SLICE_108 SLICE R6C14A KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x5006::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Scpu0/alu/alu16/a16/SLICE_109 SLICE R11C23A >MODE:CCU2 F1:F F0:F CCU2::S0=0x7078,S1=0x500E::D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Tcpu0/alu/alu16/a16/SLICE_110 SLICE R11C22D AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ucpu0/alu/alu16/a16/SLICE_111 SLICE R11C22C AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Vcpu0/alu/alu16/a16/SLICE_112 SLICE R11C22B AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Wcpu0/alu/alu16/a16/SLICE_113 SLICE R11C22A )
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q_out_2[3] ( q_out_5_bm_RNO[3] ' daa_lnm9_ac0_5 ' CCRo_4_5_RNO[2] '
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Xcpu0/alu/alu16/a16/SLICE_114 SLICE R11C21D )
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q_out_5[0] ' CCRo13_RNIPKBG ' CCRo13 ' CCRo_0[2] ' CCRo14 ' q_out_sn_m8 ' v8_sn_m10_0 ' un1_state_104_i_o4 ' state_cnst_i_a15_13_0[0] datamux_o_dest[12] datamux_o_dest_0[12] datamux_o_dest[14] datamux_o_dest_0[14] )datamux_o_alu_in_right_path_data_0_sqmuxa .datamux_o_alu_in_right_path_data_0_sqmuxa_1062 next_state10_1 next_state10 un1_state_84_1_a6_RNO P un1_state_84_1_a6 P state_32_0_iv_RNO[2] P state_cnst_0_8[2] P un1_state_101_RNI9RM81 P un1_cpu_reset_10_3 P un1_state_84_1_RNIJFIO P un1_state_84_1 P next_state_cnst_0_a2_0[4] P state_3_sqmuxa_1 P
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ycpu0/alu/alu16/a16/SLICE_115 SLICE R11C21C )
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k_memhi[0] P
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Zcpu0/alu/alu16/a16/SLICE_116 SLICE R11C21B AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [cpu0/alu/alu16/a16/SLICE_117 SLICE R11C21A )
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k_memhi[1] P un1_k_pp_regs_7_sqmuxa P k_pp_regs_7_sqmuxa P state_cnst_0_4[2] P state_cnst_0_4_RNO[2] P k_forced_mem_size_2_iv_i_RNO P k_forced_mem_size_2_iv_i_RNO_0 P state192lto7 P state192lto7_6 P
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! " # $ % & ' ( FMODE:CCU2 F1:F FCO:FCO CCU2::S0=0x500C,S1=0x7096::B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \cpu0/alu/alu16/a16/SLICE_118 SLICE R6C19A )
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vff_pipe_3 R
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! " # $ % & ' ( 9MODE:CCU2 F1:F F0:F CCU2::S0=0x72D8,S1=0x3004::C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ]cpu0/alu/alu16/a16/SLICE_119 SLICE R6C18D )
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zff_pipe_3 R alu_opcode_1_f0_0_RNO_0[1] ׀ path_left_addr_cnst_i_a2[3] alu_opcode_2_4_0_.m63 ׀ alu_opcode_2_4_0_.m5 ׀ un1_postbyte0_2_1[0] ׀ un1_postbyte0_17_RNO alu_opcode_1_f0_0_a2_4_2_0[1] ׀ k_write_exg9_0_0 un1_mode93_RNO mode76_0 q_out_2_cry_0_0_RNO Ā carry_i Ā
un1_state59_4 state_cnst_0_a2_1[2] À state_cnst_i_a15_11_1[3] path_right_addr_cnst_0_a2_0_1[0] k_pp_regs_25_bm_RNO_2[7] optype_3_2_0_.m13 alu_opcode_2_4_0_.m42_i_a2 ׀ path_left_addr_cnst_0_a2[0] mode_4_0_a5_1_1[1] state59_1 mode_4_0_a5[1] un1_dest_reg44_1_i_a2_0 optype32[0] path_right_addr_3_1[0] path_left_addr13_RNO un1_postbyte0_14_5 un1_postbyte0_21_6 path_right_addr_3_13 un1_eapostbyte_16_i_m2_am_RNO[1] S un1_eapostbyte_16_sn_m13_0_0 S k_eahi_11_iv_0_6_i_0_o2 S un1_state_108_1_RNO regs_o_su_m_0[7] S reg_su[7] R state_cnst_i_7_RNO[4] R un1_state_126_RNO k_pp_active_reg_cnst_0_2_1[1] R k_pp_active_reg_cnst_0_o3[3] pipe1_1_6_cry_5_RNO_1 pipe1_1_6_cry_5_RNO_0 pipe1_1_6_cry_5_0_RNO pipe1_1_6_cry_3_RNO_0 pipe1_1_6_cry_3_0_RNO pipe1_1_6_cry_1_0_RNO un1_state_7_3_RNIREBA3 À un1_state_21_RNI6VAF P q_out_sn_m12 À q1620_1_RNIULRV À q_out[5] * q_out[3] * q_out_sn_m4 ' h8_0 ' %datamux_o_alu_in_right_path_data_1[0] 'datamux_o_alu_in_right_path_data_RNO[1] ( un1_state_73_1 P state_cnst_0_2[2] P un1_state_24_1_RNISJT21 state_RNI6KMJ1[0] P SU_3_sqmuxa R
SS_lcry_0_RNO R 'datamux_o_alu_in_right_path_data_RNO[4] 'datamux_o_alu_in_right_path_data_RNO[6] ' 'datamux_o_alu_in_right_path_data_RNO[3] 'datamux_o_alu_in_right_path_data_RNO[7] visible_2_i_o2_1 vsync_cnt_2_sqmuxa_i_0_a2_0 state_32_0_iv_0[3] un1_state_122_0 k_pp_regs_25_bm_RNO_0[7] un1_state_73_3_RNO P un1_state_26_1 k_cpu_data_o_7_m0s2 P alu_opcode_2_4_0_.m1 ׀ mode_4_0_x2[1] alu_opcode102_1[0] ׀ un1_postbyte0_2_4 alu_opcode_1_f0_0_o2_0[1] ׀ alu_opcode_4_m_1_tz[4] ׀ dec_alu_right_path_mod_i_0[1] ׀ mode_4_i_a2_2[0] k_ealo_9_5_614_a4_1 un1_state_29_2 noofs7_1[0] un1_eapostbyte_8_1[0] S mode_cnst_1_i_a2[1] path_right_addr_bm_RNO[3] mode_4_i_a5[0] path_left_addr_cnst_i_a2[2] un1_path_left_addr15_2_0 un1_postbyte0_3_3 dest_reg_cnst_i_3[0] state133_3_0_a2 À path_left_addr_2_1_.m8_0 un1_postbyte0_33_1_a6 dest_reg44_3_0_a2 dest_reg44_3_0_a2_RNIMRER1 un1_state_12_1 state_32_0_iv_0_i_a5_2_1 R un1_state_50_1 k_cpu_oe_3_3_RNO P un1_state_32_3 un1_state_40_0 un1_state_35_3 state_32_iv_RNO[1] S state_cnst_0_a2_11[1] S state_cnst_0_4_RNO[1] S *datamux_o_alu_in_left_path_data_am_RNO[13] S datamux_o_dest_6[2] *datamux_o_alu_in_left_path_data_am_RNO[11] S *datamux_o_alu_in_left_path_data_am_RNO[12] eamem_addr_o_cry_9_0_RNIUPFN S *datamux_o_alu_in_left_path_data_am_RNO[14] k_new_pc_am_RNO[5] S k_new_pc_am_RNO[4] ' k_new_pc_am_RNO[1] S k_new_pc_am_RNO[6] ' eamem_addr_o_cry_3_0_RNIQCOF1 S $datamux_o_alu_in_left_path_data_0[4] ' eamem_addr_o_cry_1_0_RNIM6MF1 S $datamux_o_alu_in_left_path_data_0[6] ' regs_o_su_m_0[5] S regs_o_su_m_0[6] ' regs_o_su_m_0[8] S regs_o_su_m_0[4] ( regs_o_su_m_0[3] S regs_o_su_m_0[11] À regs_o_su_m_0[14] S regs_o_su_m_0[10] regs_o_su_m_0[13] S un1_regs_o_su_iv_0_a2[9] S regs_o_su_m_0[1] S regs_o_su_m_0[12] S state_32_iv_0[1] S state_32_0_iv_0[2] P
k_p2_valid8_4 S
k_p2_valid6_6 P k_eahi_11_iv_0_3_838_i_0 S k_eahi_11_iv_0_1_880_i_0 S un1_eapostbyte_16_2[12] S un1_eapostbyte_16_3[4] S un1_eapostbyte_16_2[15] S un1_eapostbyte_16_3_i_m2[10] S un1_eapostbyte_16_2[14] S un1_eapostbyte_16_3[6] S un1_eapostbyte_16_2[13] S un1_eapostbyte_16_3[5] S un1_eapostbyte_16_2[11] S un1_eapostbyte_16_3[3] S un1_eapostbyte_16_2[10] S un1_eapostbyte_16_2[8] S un1_eapostbyte_16_sn_m6_0 S un1_eapostbyte_16_3[0] S un1_eapostbyte_16_0[9] S un1_eapostbyte_16_0[15] S un1_eapostbyte_16_0[8] S un1_eapostbyte_16_0[14] S un1_eapostbyte_16_0[10] S un1_eapostbyte_16_0[13] S un1_eapostbyte_16_0[11] S un1_eapostbyte_16_0[12] S k_cpu_addr_28_iv_1_0[14] S k_cpu_addr_28_iv_1_0[1] P k_cpu_addr_28_iv_1_0[0] S k_cpu_addr_28_iv_1_0[13] ' k_cpu_addr_28_iv_1_0[7] S k_cpu_addr_28_iv_1_0[15] ' k_cpu_addr_28_iv_1_0[8] S k_cpu_addr_28_iv_1_0[4] ' datamux_o_dest_0[11] S datamux_o_dest_0[9] R k_new_pc_am_RNO[7] R *datamux_o_alu_in_left_path_data_am_RNO[15] ' k_new_pc_am_RNO[3] R *datamux_o_alu_in_left_path_data_am_RNO[10]
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ^cpu0/alu/alu16/a16/SLICE_120 SLICE R6C18C )
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SS_16_0[2] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _cpu0/alu/alu16/a16/SLICE_121 SLICE R6C18B 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x74B8,S1=0x74B8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 `cpu0/alu/alu16/a16/SLICE_122 SLICE R6C18A )
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SU_16_0[2] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 acpu0/alu/alu16/a16/SLICE_123 SLICE R6C17D 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x74B8,S1=0x74B8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 bcpu0/alu/alu16/a16/SLICE_124 SLICE R6C17C 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x74B8,S1=0x74B8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ccpu0/alu/alu16/a16/SLICE_125 SLICE R6C17B )
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IY_pipe_35 R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x74B8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 dcpu0/alu/alu16/a16/SLICE_126 SLICE R6C17A )
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IY_pipe_40 R
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! " # $ % & ' ( FMODE:CCU2 F1:F FCO:FCO CCU2::S0=0x500C,S1=0x703C::B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ecpu0/alu/alu16/mulu/SLICE_127 SLICE R9C12B RMODE:CCU2 F0:F CCU2::S0=0x300A,S1=0x0000::A0=0,B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_128 SLICE R9C12A )
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SS_16_0[3] R
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! " # $ % & ' (
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SU_16_0[3] R
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x101E,S1=0x3036::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_130 SLICE R9C11C )
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IY_pipe_45 R IY_pipe_5 R
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x101E,S1=0x101E::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_131 SLICE R9C11B FMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xF006,S1=0x101E::C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_132 SLICE R9C11A FMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x7078::A0=0,B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_133 SLICE R8C12A MODE:CCU2 REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF CCU2::S0=0x300A,S1=0x300A::B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 z NGID2 cpu0/alu/alu16/mulu/SLICE_134 SLICE R8C11D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x300A::C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_135 SLICE R8C11C )
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SU_16_0[4] R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_136 SLICE R8C11B )
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SS_16_0[4] R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_137 SLICE R8C11A )
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SU_16_0[5] R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_138 SLICE R8C10D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x9096,S1=0x5096::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_139 SLICE R8C10C )
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SS_16_0[5] R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0x7078::A0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 } NGID1 ~ NGID2 cpu0/alu/alu16/mulu/SLICE_140 SLICE R8C10B )
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SU_16_0[6] R
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0x500C::A0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 { NGID1 | NGID2 cpu0/alu/alu16/mulu/SLICE_141 SLICE R8C10A PMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x300A::A0=0,B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_142 SLICE R7C12A )
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SS_16_0[6] R
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! " # $ % & ' ( MMODE:CCU2 F1:F F0:F CCU2::S0=0x7008,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_143 SLICE R7C11D )
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SU_16_0[7] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_144 SLICE R7C11C )
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SS_16_0[7] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_145 SLICE R7C11B )
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SU_16_0[8] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_146 SLICE R7C11A )
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SS_16_0[8] R
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! " # $ % & ' ( AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x7888::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_147 SLICE R12C12A )
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SU_16_0[9] R
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! " # $ % & ' ( MMODE:CCU2 F1:F F0:F CCU2::S0=0x7008,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_148 SLICE R12C11D 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_149 SLICE R12C11C )
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SS_16_0[9] R SU_16_0[10] R SS_16_0[10] R SU_16_0[11] R SS_16_0[11] R SU_16_0[12] R SS_16_0[12] R SU_16_0[13] R SS_16_0[13] R SU_16_0[14] R SS_16_0[14] R SU_16_0[15] R SS_16_0[15] R un1_k_memlo[8] R un1_k_memlo[14] R un1_k_memlo[9] R un1_k_memlo[13] R un1_k_memlo[10] R un1_k_memlo[12] R right_cry_7_0_RNO_0 R right_cry_13_0_RNO_0 R right_cry_9_0_RNO R right_cry_13_0_RNO R right_cry_11_0_RNO R right_cry_11_0_RNO_0 R path_left_data[11] R path_left_data[12] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_150 SLICE R12C11B 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_151 SLICE R12C11A AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x7888::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_152 SLICE R14C14A )
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nff_pipe_3 R path_left_data[9] R path_left_data[14] R path_left_data[13] R path_left_data[10] R
ACCA_RNO_1[1] R
ACCA_RNO_1[2] R
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! " # $ % & ' ( MMODE:CCU2 F1:F F0:F CCU2::S0=0x7008,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_153 SLICE R14C13D )
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k_ofshi[4] P
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_154 SLICE R14C13C )
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k_ofshi[5] P
SU_1_sqmuxa_1 R
SU_lcry_0_RNO R SU_1_sqmuxa R SU_0_sqmuxa R k_set_e_3_1 R state_RNIV5RP[0] P state_32_0_iv_0_i_a5_1_1 R un1_state_108_1_a7_0_1 À N_550_i_0 R 'datamux_o_alu_in_right_path_data30_0_a2
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_155 SLICE R14C13B )
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IX_pipe_57 R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_156 SLICE R14C13A AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x7888::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_157 SLICE R14C12B MODE:CCU2 REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0x300A,S1=0x300A::B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_158 SLICE R14C12A )
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IX_pipe_58 R k_cpu_addr_28_iv_1_0[9] R k_cpu_addr_28_iv_1_0[5] ' k_cpu_addr_28_iv_1_0[3] R k_cpu_addr_28_iv_1_0[2] ' q_out_2_cry_1_0_RNO Ā l8 '
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x3006,S1=0x300A::C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_159 SLICE R14C11D )
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%
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_160 SLICE R14C11C )
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'
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1
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)
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REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_161 SLICE R14C11B )
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+
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5096,S1=0x3006::D0=0,C1=0,D1=0 4 MODE K1 K0 REG1
REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_162 SLICE R14C11A FMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x506A::A0=0,B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/a8/SLICE_163 SLICE R11C15A )
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-
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! " # $ % & ' ( CMODE:CCU2 F1:F F0:F CCU2::S0=0x30A5,S1=0x300F::D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Acpu0/alu/alu8/a8/SLICE_164 SLICE R11C14D )
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/
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x30A5,S1=0x50C3::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Bcpu0/alu/alu8/a8/SLICE_165 SLICE R11C14C )
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9 q_out_3_0[1]
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x30A5,S1=0x50C3::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ccpu0/alu/alu8/a8/SLICE_166 SLICE R11C14B AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x50C3,S1=0x50C3::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Dcpu0/alu/alu8/a8/SLICE_167 SLICE R11C14A )
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$ q_out_2_cry_1_0_RNO_0 Ā q_out_3_0[2]
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! " # $ % & ' ( AMODE:CCU2 FCO:FCO CCU2::S0=0x000A,S1=0x30A5::A0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ecpu0/alu/alu8/a8/SLICE_168 SLICE R6C25A )
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$ q_out_2_cry_3_0_RNO Ā q_out_3_0[3]
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! " # $ % & ' ( MMODE:CCU2 F1:F F0:F CCU2::S0=0x3006,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Fcpu0/alu/alu8/a8/SLICE_169 SLICE R6C24D )
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$ q_out_2_cry_5_0_RNO Ā q_out_3_0[5]
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Gcpu0/alu/alu8/a8/SLICE_170 SLICE R6C24C )
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$ q_out_2_cry_5_0_RNO_0 Ā q_out_3_0[6]
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Hcpu0/alu/alu8/a8/SLICE_171 SLICE R6C24B )
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$ q_out_2_cry_7_0_RNO Ā q_out_3_0[7]
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Icpu0/alu/alu8/a8/SLICE_172 SLICE R6C24A KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x5006::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Jcpu0/alu/alu8/a8/SLICE_173 SLICE R11C17A >MODE:CCU2 F1:F F0:F CCU2::S0=0x7078,S1=0x500E::D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Kcpu0/alu/alu8/a8/SLICE_174 SLICE R11C16D AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Lcpu0/alu/alu8/a8/SLICE_175 SLICE R11C16C )
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$ k_pp_active_reg_cnst_0_1[3] k_pp_active_reg_cnst_0_a5_0[2] un15_pipe1[12] pipe1_1_6_cry_7_0_RNO q1624_0 À CCRo14_1 ' q_out[2] * q_out_sn_m2 ' q_out[1] * q_out_3_0[0]
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Mcpu0/alu/alu8/a8/SLICE_176 SLICE R11C16B )
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$ q_out[6] * carry_out * k_cpu_addr_28_iv_1_0[6] ' k_cpu_addr_28_iv_1_0[11] ' k_mem_dest_RNO_0[0] P
un1_state_101 P cpu0_data_in_0[6] cen_o cpu0_data_in_0[7]
un1_cpu0_we_1 cpu0_data_in_0[5] cpu0_data_in_0[0]
chars_data[4]
chars_data[5] cpu0_data_in_0[4] cpu0_data_in_0[1]
chars_data[2]
chars_data[3] cpu0_data_in_0[3] cpu0_data_in_0[2]
chars_data[0]
chars_data[1] un1_cpu0_we cpu0_we_i P un1_bios_en cpu0_oe_i P redr9_11
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ncpu0/alu/alu8/a8/SLICE_177 SLICE R11C16A )
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yptr_axb_5 !vsync_cnt_2_sqmuxa_i_0_a2_RNITRFC un1_k_cpu_addr_2_sqmuxa_1_RNO À k_pp_regs_6_sqmuxa_1 un1_state_75 À op[4] IY_1_sqmuxa_2_1_0 R op[5] state57_1_0[0] op[3] un1_postbyte0_33_1_2 op[1] un1_postbyte0_6_3 alu_opcode_2_4_0_.m20 ׀ k_pp_regs_0_sqmuxa_2 À alu_opcode_1_f0_0_m2[2] ׀ un1_dest_reg44_1_i_o2 alu_opcode_2_4_0_.m7 ׀ state57_1[0] optype_3_2_0_.m18 dest_reg_0_sqmuxa_2_i_a2_3 optype_3_2_0_.m9 mode_4_i_a2_0[0] un1_state_1_sqmuxa_2_1 "datamux_o_alu_in_left_path_addr[3] P regs_o_su_m_0[2] S
SU_0_sqmuxa_1 R k_new_pc_2_i_m2_0[9] S state_cnst_i_8_RNO[4] R state_cnst_i_o2_1[0] S k_new_pc26_1_i S un1_pc_0[15] S k_cpu_addr_28_iv_0[15] ' un1_pc_0[14] S un1_pc_0[7] S un1_pc_0[13] S un1_pc_0[8] S un1_pc_0[12] S un1_pc_0[9] S un1_pc_0[11] S un1_pc_0[10] S eamem_addr_o_15_a S un1_eamem_addr63_3 S
k_p2_valid8_0 S
k_p2_valid6_2 P state_cnst_0_a2_2_RNIT3GO1[1] S cff_1_sqmuxa_2_RNI1FDN R un1_eapostbyte_16_sn_m8_0_o2 S k_new_pc_am_RNO[0] R right_cry_0_0_RNO R right_cry_7_0_RNO R right_cry_1_0_RNO R right_cry_5_0_RNO_0 R right_cry_1_0_RNO_0 R 'datamux_o_alu_in_right_path_data_RNO[2] right_cry_3_0_RNO R right_cry_5_0_RNO R PC_9_0[0] R PC_9_0[7] R
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! " # $ % & ' ( FMODE:CCU2 F1:F FCO:FCO CCU2::S0=0x500C,S1=0x7096::B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ocpu0/alu/alu8/a8/SLICE_178 SLICE R6C23A )
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IX_pipe_63 R
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! " # $ % & ' ( 9MODE:CCU2 F1:F F0:F CCU2::S0=0x72D8,S1=0x3004::C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ! WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Pcpu0/alu/alu8/a8/SLICE_179 SLICE R6C22D )
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IX_pipe_65 R fflag_9_0 R vff_9_0 R ACCB_9[6] R ACCB_9[0] R k_opcode[0] P k_opcode[1] P ACCB_9[5] R ACCB_9[1] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 " WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Qcpu0/alu/alu8/a8/SLICE_180 SLICE R6C22C )
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k_ofslo[6] P
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x74B8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 # WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Rcpu0/alu/alu8/a8/SLICE_181 SLICE R6C22B )
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k_ofslo[7] P PC_9_0[1] R PC_9_0[6] R
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x74B8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 $ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Scpu0/alu/alu8/a8/SLICE_182 SLICE R6C22A )
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IX_pipe_67 R
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! " # $ % & ' ( FMODE:CCU2 F1:F FCO:FCO CCU2::S0=0x300A,S1=0x703C::A0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 % WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Tcpu0/alu/alu8/SLICE_183 SLICE R8C14A )
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IX_pipe_68 R PC_9_0[2] R PC_9_0[5] R IX_pipe_7 R
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! " # $ % & ' ( MMODE:CCU2 F0:F CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 & WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 pcpu0/alu/alu8/SLICE_184 SLICE R8C13D )
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IX_pipe_70 R PC_9_0[3] R PC_9_0[4] R
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! " # $ % & ' ( UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xF001,S1=0xF001::A0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ' WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 qcpu0/alu/alu8/SLICE_185 SLICE R8C13C UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xF001,S1=0xF001::B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ( WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 rcpu0/alu/alu8/SLICE_186 SLICE R8C13B )
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IX_pipe_72 R
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! " # $ % & ' ( UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xF001,S1=0xF001::B0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ) WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 scpu0/alu/alu8/SLICE_187 SLICE R8C13A KMODE:CCU2 FCO:FCO CCU2::S0=0x000A,S1=0xF001::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 * WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 tcpu0/SLICE_188 SLICE R10C26A )
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IX_pipe_73 R
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! " # $ % & ' ( CMODE:CCU2 F0:F CCU2::S0=0x3063,S1=0x300A::D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 + WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_189 SLICE R10C25D )
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q_out_3[0] Ā
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x2D21,S1=0x2D21 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 , WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_190 SLICE R10C25C 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x4B41,S1=0x4B41 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 - WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_191 SLICE R10C25B 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x4B41,S1=0x4B41 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 . WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_192 SLICE R10C25A 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x4B41,S1=0x4B41 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 / WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_193 SLICE R10C24D )
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q_out_2[6] (
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x2D21,S1=0x2D21 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 0 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_194 SLICE R10C24C 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x4B41,S1=0x4B41 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 1 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_195 SLICE R10C24B )
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q_out_3[1] Ā
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x2D21,S1=0x2D21 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_196 SLICE R16C27B )
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q_out_2[5] (
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C+D)+B*((C+A)+D)) K0::H0=(~B*(A+D)+B*((A+C)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 4 K0 3 REG1 6 REG0 5 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 g NGID3 hcpu0/SLICE_197 SLICE R12C25A )
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q_out_3[2] Ā
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C+D)+B*((A+C)+D)) K0::H0=(~B*(C+D)+B*((C+A)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 8 K0 7 REG1 : REG0 9 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 i NGID3 jcpu0/SLICE_198 SLICE R12C28D )
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q_out_2[2] (
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C+D)+A*((B+C)+D)) K0::H0=(~C*(A+D)+C*((A+B)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 < K0 ; REG1 > REG0 = Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 k NGID3 lcpu0/SLICE_199 SLICE R11C25D )
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q_out_3[3] Ā
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C+D)+A*((C+B)+D)) K0::H0=(~A*(C+D)+A*((C+B)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 @ K0 ? REG1 B REG0 A Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 m NGID3 ncpu0/SLICE_200 SLICE R11C26D )
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q_out_2[1] (
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D+C)+A*((D+B)+C)) K0::H0=(~B*(A+D)+B*((C+A)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 D K0 C REG1 F REG0 E Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 o NGID3 pcpu0/SLICE_201 SLICE R11C26A )
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q_out_3[4] Ā q_out[0] *
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D+C)+A*((D+B)+C)) K0::H0=(~A*(C+D)+A*((B+C)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 H K0 G REG1 J REG0 I Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 q NGID3 rcpu0/SLICE_202 SLICE R11C26C )
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q_out_3[5] Ā q1623_1 À
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A+B)+D*((A+C)+B)) K0::H0=(~A*(C+D)+A*((B+C)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 L K0 K REG1 N REG0 M Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 s NGID3 tcpu0/SLICE_203 SLICE R12C27A )
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q_out_3[6] Ā
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(B+C)+D*((B+A)+C)) K0::H0=(~D*(A+C)+D*((A+B)+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 P K0 O REG1 R REG0 Q Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 u NGID3 vSLICE_204 SLICE R19C29C )
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q_out_3[7] Ā q_out_2_cry_3_0_RNO_0 Ā pipe1_1_6_14 q_out_2_cry_7_0_RNO_0 Ā un8_q_out_cry_7_0_RNO_0 Ā q_out_2_cry_9_0_RNO Ā un8_q_out_cry_9_0_RNO Ā q_out_2_cry_9_0_RNO_0 Ā un8_q_out_cry_9_0_RNO_0 Ā q_out_2_cry_11_0_RNO Ā un8_q_out_cry_11_0_RNO Ā q_out_2_cry_11_0_RNO_0 Ā un8_q_out_cry_11_0_RNO_0 Ā q_out_2_cry_13_0_RNO Ā un8_q_out_cry_13_0_RNO Ā q_out_2_cry_13_0_RNO_0 Ā un8_q_out_cry_13_0_RNO_0 Ā q_out_2_cry_15_0_RNO Ā un8_q_out_cry_15_0_RNO Ā un8_q_out_cry_1_0_RNO Ā
pipe0_1_5_1_b un8_q_out_cry_1_0_RNO_0 Ā pipe1_1_6_4 un8_q_out_cry_3_0_RNO Ā CCRo_0[3] ' un8_q_out_cry_5_0_RNO Ā un20_pipe1[12] un8_q_out_cry_5_0_RNO_0 Ā un20_pipe1[13] un8_q_out_cry_7_0_RNO Ā un15_pipe1[13] pipe1_1_6_9
pipe1_1_6_0_a pipe1_1_6_19 pipe1_1_6_0
pipe1_1_4_1_a
pipe0_1_5_1_a un1_k_cpu_addr_2_sqmuxa_RNO À un1_state_52 P q_out_5_bm_RNO[7] ' c8_3 ' cneg8_r_5 ' vneg8_r_4 ' CCRo_4_5[2] ' q_out[0] ' state_cnst_0_13[1] S state_cnst_0_7[1] S un1_state_85 R un1_cpu_reset_10_2 P vsync_cnt_2_sqmuxa_i_0_a2_1 x_cnt5_x_8_0 k_write_pc_6_0 state_cnst_i_3[4] R path_left_data[8] R "datamux_o_alu_in_left_path_addr[1] P y_cnt4_i un6_visiblelto10_0_o2_1 path_left_addr13_RNIDV4J mode88_1[0] k_cpu_addr_28_iv_1_0[10] ' k_ealo_9_3_661_m3 R state_3_sqmuxa_5 À k_pp_active_reg_cnst_i_a5[0] state_cnst_0_1[2] P k_ealo_9_5_614_a4_0_0 neg8_w_s_7_0_RNO ' vneg8_r_3 ' data_io_pad[0]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*C)+D*(B*C)) K0::H0=(~D*(B*C)+D*(A*C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 U K0 S REG1 W REG0 V Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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data_io[0] cpuclk_o_pad cpuclk_o clk40_i_pad clk40_i ldata_io_pad[7] ldata_io[7] ldata_io_pad[6] ldata_io[6] ldata_io_pad[5] ldata_io[5] ldata_io_pad[4] ldata_io[4] ldata_io_pad[3] ldata_io[3] ldata_io_pad[2] ldata_io[2] ldata_io_pad[1] ldata_io[1] ldata_io_pad[0] ldata_io[0]
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NGID1 ~ NGID2 NGID3 SLICE_205 SLICE R21C27B )
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lcen_o_pad lcen_o
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(D*A)+B*(C*A)) K0::H0=(~D*(C*A)+D*(B*A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 Y K0 X REG1 [ REG0 Z Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 x NGID1 } NGID2 NGID3 cpu0/SLICE_206 SLICE R19C30B )
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lwen_o_pad lwen_o
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*(~D*(~B*C))) K0::H0=(~A*(~D*C+D*(~B+C))+A*C) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 ] K0 \ REG1 REG0 ^ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 \ NGID2 cpu0/SLICE_207 SLICE R22C32A )
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loen_o_pad loen_o laddr_o_pad[5]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*D+B*(~C*(~A+D)+C*D)) K0::H0=(~C*(A*(B*~D))+C*(~A*(~B*~D)+A*~D)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 a K0 _ REG1 REG0 b Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 w NGID1 R NGID2 cpu0/alu/alu16/mulu/SLICE_208 SLICE R22C31D )
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laddr_o[5] laddr_o_pad[4]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~B*~D)+A*(~B*(~D*~C))) K0::H0=(C*(B*D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 d K0 c REG1 f REG0 e Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 u NGID1 NGID2 NGID3 cpu0/alu/alu16/mulu/SLICE_209 SLICE R22C31B )
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laddr_o[4] laddr_o_pad[3]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*~C)+(B*C)+(B*A) K0::H0=(~A*D)+(C*D)+(C*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 h REG1 REG0 i Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/alu/alu16/mulu/SLICE_210 SLICE R8C12C )
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laddr_o[3] laddr_o_pad[2]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*D)+C*(~B*A+B*(D@A))) K0::H0=(B*A) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 k K0 j REG1 m REG0 l Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/alu/alu16/mulu/SLICE_211 SLICE R10C11C )
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laddr_o[2] laddr_o_pad[1]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*D) K0::H0=(~B*C+B*(D@C)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 o K0 n REG1 REG0 p Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_212 SLICE R21C28A )
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laddr_o[1] laddr_o_pad[0]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C+A) K0::H0=(~A*(~C*(D*~B)+C*(~D+~B))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 r K0 q REG1 REG0 s Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 w NGID2 cpu0/SLICE_213 SLICE R18C29B )
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laddr_o[0]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*(~D*~C))) K0::H0=(~A*(~B*(C*D))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 v K0 t REG1 REG0 w Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 p NGID1 NGID2 cpu0/SLICE_217 SLICE R12C15D )
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blue_o_pad blue_o green_o_pad green_o red_o_pad red_o vsync_o_pad vsync_o textctrl_vsyncrio hsync_o_pad hsync_o textctrl_hsyncrio
leds_o_pad[7] leds_o[7]
leds_r_0io[7]
leds_o_pad[6] leds_o[6]
leds_r_0io[6]
leds_o_pad[5] leds_o[5]
leds_r_0io[5]
leds_o_pad[4] leds_o[4]
leds_r_0io[4]
leds_o_pad[3] leds_o[3]
leds_r_0io[3]
leds_o_pad[2] leds_o[2]
leds_r_0io[2]
leds_o_pad[1] leds_o[1]
leds_r_0io[1]
leds_o_pad[0] leds_o[0]
leds_r_0io[0] state_o_pad[5]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~A*C+A*D)+B*D) K0::H0=(~D*(~A*C+A*B)+D*B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 y K0 x REG1 { REG0 z Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_218 SLICE R10C17A )
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state_o[5] state_o_pad[4]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D*B+D*A)+C*A) K0::H0=(~A*(~D*C+D*B)+A*B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 } K0 | REG1 REG0 ~ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_219 SLICE R8C23A )
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state_o[4] state_o_pad[3]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~D*C+D*A)+B*A) K0::H0=(~A*(~D*B+D*C)+A*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_220 SLICE R8C23B )
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state_o[3] state_o_pad[2]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~D*C+D*A)+B*A) K0::H0=(~B*(~D*C+D*A)+B*A) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ` NGID1 NGID2 NGID3 cpu0/SLICE_221 SLICE R9C23D )
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state_o[2] state_o_pad[1]
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! " # $ % & ' ( MODE:LOGIC K1::H1=B+~D K0::H0=(C*~B)+(D*B)+(D*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 a NGID1 NGID2 NGID3 cpu0/alu/SLICE_222 SLICE R8C23C )
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state_o[1] state_o_pad[0]
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! " # $ % & ' ( MODE:LOGIC K1::H1=C+~A K0::H0=(D*~A)+(B*A)+(B*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 7 NGID1 & NGID2 ' NGID3 cpu0/SLICE_223 SLICE R11C24C )
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state_o[0] data_io_pad[7]
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! " # $ % & ' ( MODE:LOGIC K1::H1=D+~C K0::H0=(B*~A)+(C*A)+(C*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ^ NGID1 NGID2 NGID3 cpu0/alu/SLICE_224 SLICE R14C23A )
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data_io[7] data_io_pad[6]
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! " # $ % & ' ( MODE:LOGIC K1::H1=C+~B K0::H0=(C*~D)+(B*D)+(B*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 l NGID1
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data_io[6] data_io_pad[5]
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NGID2
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data_io[5] data_io_pad[4]
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NGID3 cpu0/SLICE_225 SLICE R14C21D )
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data_io[4] data_io_pad[3]
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! " # $ % & ' ( MODE:LOGIC K1::H1=A+~D K0::H0=(A*~B)+(D*B)+(D*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_226 SLICE R15C21A )
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data_io[3] data_io_pad[2]
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! " # $ % & ' ( MODE:LOGIC K1::H1=B+~C K0::H0=(D*~A)+(B*A)+(B*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/alu/SLICE_227 SLICE R14C22A )
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data_io[2] data_io_pad[1]
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! " # $ % & ' ( MODE:LOGIC K1::H1=D+~C K0::H0=(A*~B)+(C*B)+(C*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/alu/SLICE_228 SLICE R17C25C )
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data_io[1] cen_o_pad cen_o wen_o_pad wen_o oen_o_pad oen_o addr_o_pad[18]
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! " # $ % & ' ( MODE:LOGIC K1::H1=C+~B K0::H0=(D*~C)+(A*C)+(A*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 i NGID1 NGID2 NGID3 cpu0/SLICE_229 SLICE R12C13B )
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addr_o[18] addr_o_pad[17]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*C)+D*(~A+C)) K0::H0=(~A*(C*D)+A*(~C+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 T NGID1 NGID2 NGID3 cpu0/SLICE_230 SLICE R12C13D )
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addr_o[17] addr_o_pad[16]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C*B)+A*(~C+B)) K0::H0=(~A*(C*D)+A*(~C+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_231 SLICE R10C13A )
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addr_o[16] addr_o_pad[15]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(D*A)+B*(~D+A)) K0::H0=(~B*(D*A)+B*(~D+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_232 SLICE R14C16C )
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addr_o[15] addr_o_pad[14]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*~D)+(C*A)+(~A*~D)+(~B*~D)+(~B*A) K0::H0=C*~B*A*D REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/alu/SLICE_233 SLICE R14C15B )
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addr_o[14] addr_o_pad[13]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*~D)+(A*C)+(~C*~D)+(~B*~D)+(~B*C) K0::H0=A*~B*D*C REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 = NGID1 , NGID2 - NGID3 cpu0/alu/SLICE_234 SLICE R14C15A )
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addr_o[13] addr_o_pad[12]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*~D)+(A*C)+(~C*~D)+(~B*~D)+(~B*C) K0::H0=A*~B*D*C REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 q NGID2 r NGID3 cpu0/SLICE_235 SLICE R14C15D )
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addr_o[12] addr_o_pad[11]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*~D)+(C*A)+(~A*~D)+(~B*~D)+(~B*A) K0::H0=A*~B*C*D REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_236 SLICE R14C15C )
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addr_o[11] addr_o_pad[10]
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*~A)+(D*C)+(~C*~A)+(~B*~A)+(~B*C) K0::H0=A*~B*D*C REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_237 SLICE R15C14D )
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addr_o[10]
addr_o_pad[9] addr_o[9]
addr_o_pad[8] addr_o[8]
addr_o_pad[7] addr_o[7]
addr_o_pad[6] addr_o[6]
addr_o_pad[5] addr_o[5]
addr_o_pad[4] addr_o[4]
addr_o_pad[3] addr_o[3]
addr_o_pad[2] addr_o[2]
addr_o_pad[1] addr_o[1]
addr_o_pad[0] addr_o[0] reset_o_pad reset_o e textctrl/SLICE_0 SLICE R21C7D MMODE:CCU2 F0:F CCU2::S0=0x300A,S1=0x300A::B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*~D)+(C*B)+(~B*~D)+(~A*~D)+(~A*B) K0::H0=A*D*B REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/alu/SLICE_238 SLICE R16C16D )
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textctrl/SLICE_1 SLICE R21C7C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*~A)+(D*B)+(~B*~A)+(~C*~A)+(~C*B) K0::H0=B*~A*C*D REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 n NGID2 o NGID3 cpu0/alu/SLICE_239 SLICE R16C15C )
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*~D)+(C*~D)+(C*A) K0::H0=(B*~C)+(B*~A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 u NGID1
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textctrl/SLICE_2 SLICE R21C7B )
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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NGID2
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textctrl/SLICE_3 SLICE R21C7A KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x5006::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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NGID3 cpu0/SLICE_240 SLICE R11C27B )
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textctrl/SLICE_4 SLICE R22C8D RMODE:CCU2 F1:F F0:F CCU2::S0=0x300A,S1=0x300A::B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*D)+A*(~B*(D*C)+B*D)) K0::H0=(~B*(C*A)+B*(~D*(C*A)+D*C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_241 SLICE R11C28C )
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textctrl/SLICE_5 SLICE R22C8C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*D)+B*(~A*(C*D)+A*C)) K0::H0=(~B*(A*D)+B*(~C*(A*D)+C*D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_242 SLICE R11C28B )
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D*~A)) K0::H0=(~A*(~D*B+D*(~C*B))+A*(~C*B)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_regs/SLICE_243 SLICE R9C29B )
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textctrl/SLICE_6 SLICE R22C8B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*~A*~B)+(~C*~D*~B) K0::H0=(~A*C)+(~D*C)+(~D*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ( NGID1 NGID2 NGID3 cpu0/dec_regs/SLICE_244 SLICE R7C29B )
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=~C*~D*~A K0::H0=(B*~D)+(A*~D)+(A*~B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 l NGID1 ; NGID2 < NGID3 cpu0/dec_regs/SLICE_245 SLICE R9C29C )
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textctrl/SLICE_7 SLICE R22C8A KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x5006::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=~C*~A*~B*~D K0::H0=(~D*C)+(B*~C)+(B*~D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 o NGID1 > NGID2 ? NGID3 cpu0/dec_regs/SLICE_246 SLICE R9C28B )
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textctrl/SLICE_8 SLICE R21C8D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*~B*~C)+(A*~D) K0::H0=(D*~A)+(C*~A)+(C*~D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 r NGID1 A NGID2 B NGID3 cpu0/dec_regs/SLICE_247 SLICE R12C30C )
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! " # $ % & ' ( MMODE:CCU2 F1:F F0:F CCU2::S0=0x300A,S1=0x500C::B0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A)+B+C K0::H0=(D*B*A)+(C*~A)+(C*B)+(C*~D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 c NGID1 2 NGID2 3 NGID3 cpu0/dec_regs/SLICE_248 SLICE R12C29B )
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WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A)+C+B K0::H0=(D*A*~C)+(B*~C)+(B*~A)+(B*~D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ` NGID1 / NGID2 0 NGID3 cpu0/dec_regs/SLICE_249 SLICE R11C29A )
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textctrl/SLICE_9 SLICE R21C8C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*A*~B)+(~C*A*~B) K0::H0=(~A*~D*C)+(B*~A*~D)+(B*~C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 5 NGID2 NGID3 cpu0/dec_regs/SLICE_250 SLICE R12C30B )
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! " # $ % & ' ( PMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x300A::C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*~C*~B)+(D*~C*~A) K0::H0=(D*C)+(A*~C)+(A*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 g NGID1 7 NGID2 NGID3 cpu0/dec_regs/SLICE_251 SLICE R10C28D )
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textctrl/SLICE_10 SLICE R21C8B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*B)+(D*B)+(D*~C)+A K0::H0=(C*~D)+(A*~D)+(B*D)+(B*A)+(B*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 K NGID2 L NGID3 cpu0/dec_regs/SLICE_252 SLICE R14C28A )
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! " # $ % & ' ( FMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3096,S1=0x5006::D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~A+C)+D*(C*A)) K0::H0=(~C*(~B*(~D*~A)+B*(~D+A))+C*(B*A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _ NGID1 } NGID2 NGID3 cpu0/dec_regs/SLICE_253 SLICE R10C28A )
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textctrl/SLICE_11 SLICE R21C8A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*A)+(D*A)+(D*~B)+C K0::H0=(C*D)+(C*B)+(B*~D)+(A*~D)+(A*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 P NGID2 Q NGID3 cpu0/SLICE_254 SLICE R17C28C )
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! " # $ % & ' ( KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x3006::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2
WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*~D) K0::H0=(D*(~A*(C*B))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ] NGID1 NGID2 wcpu0/SLICE_255 SLICE R14C27A )
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textctrl/SLICE_12 SLICE R22C10D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*(B*(~C*~D))) K0::H0=((A*(~D*C))+B) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 s NGID1 NGID2 \cpu0/SLICE_256 SLICE R18C27B )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0xF008,S1=0x3008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*B)+((~(D*A)*~C)*~B) K0::H0=(~D*(~B*~A)+D*(~C*(~B*~A)+C*~A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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; NGID1
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NGID3 T NGID4 Ucpu0/SLICE_257 SLICE R17C26B )
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< NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*B)+((~(C*A)*~D)*~B) K0::H0=(~C*B)+((~(D*A)*~C)*~B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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textctrl/SLICE_13 SLICE R22C10C )
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NGID2
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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NGID3
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9 NGID1
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NGID4 V NGID5 Wcpu0/SLICE_258 SLICE R17C27C )
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: NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*A)+((~(D*B)*~C)*~A) K0::H0=(~A*~D+A*(C*~D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 : NGID2
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textctrl/SLICE_14 SLICE R22C10B )
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NGID3 X NGID4 Ycpu0/SLICE_259 SLICE R18C27A )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B)+((~(D*C)*~A)*~B) K0::H0=(~A*C)+((~(D*B)*~A)*~C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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7 NGID1
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NGID2 9 NGID3
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8 NGID2
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NGID4 Z NGID5 [cpu0/SLICE_260 SLICE R18C27D )
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textctrl/SLICE_15 SLICE R22C10A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A+D)+C*(A+B)) K0::H0=(~B*(D*C)+B*A) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0
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! " # $ % & ' ( MODE:CCU2 REG1:#ON Q1:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x300A,S1=0xF008::A0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Z NGID2 L NGID3 Mcpu0/SLICE_261 SLICE R19C27C )
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6 NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*~A+D*(~A+C)) K0::H0=(~D*(~A*(~C*~B)+A*~C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1
K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 N NGID3 Ocpu0/SLICE_262 SLICE R18C28C )
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textctrl/SLICE_16 SLICE R22C7D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D+A) K0::H0=(~A+C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 P NGID3 Qcpu0/SLICE_263 SLICE R19C27B )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0xF008,S1=0x3008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D+B) K0::H0=(~D+C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 R NGID3 Scpu0/SLICE_264 SLICE R17C31B )
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4 NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*(C*(~A*B))) K0::H0=(~C*((B+D)+A)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ! NGID1 NGID2 Kcpu0/SLICE_265 SLICE R18C30A )
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5 NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*(~A*(~C*D))) K0::H0=(((D+A)+B)+C) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 Jcpu0/SLICE_266 SLICE R16C31D )
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textctrl/SLICE_17 SLICE R22C7C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*(~D*A))) K0::H0=(~D*(~C*(A*B)+C*B)+D*B) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 7 NGID1 NGID2 ISLICE_269 SLICE R15C26B )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*A)+B*(D*A)) K0::H0=(~B*(C*A)+B*(D*A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 " K0 ! REG1 $ REG0 # Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 { NGID2 E NGID3 FSLICE_270 SLICE R15C26D )
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2 NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*A)+B*(D*A)) K0::H0=(~B*(C*A)+B*(D*A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 & K0 % REG1 ( REG0 ' Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 y NGID2 G NGID3 Hcpu0/SLICE_279 SLICE R15C34B )
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3 NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*(C*(D*~A))) K0::H0=(~B*(~D*(C+A))+B*(C+A)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 * K0 ) REG1 REG0 + Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ( NGID2 0cpu0/SLICE_292 SLICE R19C30D )
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textctrl/SLICE_18 SLICE R22C7B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*(B*(A*~D))) K0::H0=(~B*(~D*A)+B*(~D*(A+C))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 - K0 , REG1 REG0 . Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 U NGID2 cpu0/SLICE_293 SLICE R19C30C )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ! WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*(B*(A*D))) K0::H0=(~D*(~B*A)+D*(~B*(C+A))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 0 K0 / REG1 REG0 1 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 V NGID2 cpu0/SLICE_298 SLICE R21C33A )
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0 NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C+B)+A*~D) K0::H0=(~A*(~C*~B)+A*~D) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 3 K0 2 REG1 5 REG0 4 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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1 NGID2
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NGID3 cpu0/SLICE_299 SLICE R21C33B )
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textctrl/SLICE_19 SLICE R22C7A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=((B*D)+A) K0::H0=(~B*(D+A)+B*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 7 K0 6 REG1 9 REG0 8 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 * NGID2 NGID3
cpu0/SLICE_300 SLICE R21C31D )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON Q1:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x300A,S1=0xF008::A0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 " REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 # WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*~C)+(D*C)+(D*A) K0::H0=(A*B)+(A*~C)+(D*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 ; REG1 REG0 < Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 V NGID1 NGID2 NGID3 cpu0/SLICE_301 SLICE R21C30B )
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/ NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(A*D)+(B*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 > REG1 REG0 ? Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \ NGID1 NGID2 NGID3 cpu0/SLICE_302 SLICE R21C30D )
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textctrl/SLICE_20 SLICE R23C6B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=~D*A REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 A REG1 REG0 B Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Y NGID1 NGID2 NGID3 cpu0/SLICE_303 SLICE R21C30C )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0xF008,S1=0x3008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 % REG0 $ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 & WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*D)+(~C*B)+(A*B)+(A*D)+(A*C) K0::H0=(C*~A)+(C*~B)+(D*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 D REG1 REG0 E Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 S NGID1 NGID2 NGID3 cpu0/alu/alu16/mulu/SLICE_304 SLICE R21C32D )
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F NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*(~B*D)+A*D)) K0::H0=(~D*(C*(A*B))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 G K0 F REG1 I REG0 H Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 x NGID2 NGID3 cpu0/SLICE_305 SLICE R22C32D )
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G NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*(~B*~D))) K0::H0=(~C*(~A*D)+C*(~A*(~B*D))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K K0 J REG1 REG0 L Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 y NGID1 NGID2 cpu0/SLICE_306 SLICE R16C30B )
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textctrl/SLICE_21 SLICE R23C6A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(A*(D*C))) K0::H0=(((D+A)+C)+B) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 N K0 M REG1 REG0 O Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 $ NGID2 cpu0/SLICE_307 SLICE R16C34A )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 ( REG0 ' Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ) WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*(~D*B))) K0::H0=(~B*(A*~C)+B*(~A*D+A*(~C+D))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 Q K0 P REG1 REG0 R Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_308 SLICE R10C30B )
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D NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~D*(~A*~C))) K0::H0=(B*(A*(C*D))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 T K0 S REG1 REG0 U Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 & NGID1 NGID2 cpu0/SLICE_309 SLICE R18C30C )
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E NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~D*(B*C)+D*(~B+C))+A*(~B+C)) K0::H0=(~C*(D*B)+C*(~D*(B*A)+D*B)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 X K0 V REG1 REG0 Y Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_310 SLICE R18C28B )
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textctrl/SLICE_22 SLICE R23C5D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*(D*A))+B*(~C*A)) K0::H0=(~C*(~D*A+D*(A*~B))+C*(~D*A)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 [ K0 Z REG1 REG0 \ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ` NGID1 x NGID2 cpu0/SLICE_311 SLICE R10C30C )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 + REG0 * Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 , WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~C*(D*~B))) K0::H0=(B*(A*(D*C))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 ^ K0 ] REG1 REG0 _ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ' NGID1 NGID2 cpu0/SLICE_312 SLICE R19C34B )
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B NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~B*~D+B*(~D*A))+C*~D) K0::H0=D+B+C+A REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 a K0 ` REG1 c REG0 b Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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C NGID2
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NGID3
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textctrl/SLICE_23 SLICE R23C5C )
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NGID4
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 . REG0 - Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 / WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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cpu0/SLICE_313 SLICE R18C34A )
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@ NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*(B*(C*A))) K0::H0=(((D+C)+B)+A) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 e K0 d REG1 g REG0 f Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 X NGID1 NGID2
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A NGID2
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NGID3
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textctrl/SLICE_24 SLICE R23C5B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 1 REG0 0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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cpu0/SLICE_315 SLICE R17C32B )
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> NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=C+~(~D*~A)+~B K0::H0=(~A*~D) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 i K0 h REG1 k REG0 j Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ) NGID1 NGID2 NGID3
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? NGID2
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NGID4
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textctrl/SLICE_25 SLICE R23C5A )
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cpu0/SLICE_316 SLICE R18C31A )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON Q1:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0xF008::B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 3 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 4 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D*~B+D*A)+C*(~D+A)) K0::H0=(~D*(~B*~C)+D*~A) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 m K0 l REG1 o REG0 n Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ) NGID1 NGID2
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= NGID1
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NGID3
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textctrl/SLICE_26 SLICE R25C10D MODE:CCU2 REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0x5002,S1=0x300A::B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 5 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 6 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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cpu0/SLICE_317 SLICE R18C32B )
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~ NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(((A*B)+D)+C) K0::H0=(~D*(A*B)+D*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 q K0 p REG1 s REG0 r Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ' NGID1 NGID2
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textctrl/SLICE_27 SLICE R25C10C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF002,S1=0xF002::B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 8 REG0 7 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 9 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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NGID3
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| NGID1
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cpu0/SLICE_318 SLICE R18C32C )
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} NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*~C+B*A) K0::H0=(~B*(~A*(~D+~C))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 u K0 t REG1 w REG0 v Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 - NGID1 ( NGID2
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textctrl/SLICE_28 SLICE R25C10B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF002,S1=0xF002::B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 ; REG0 : Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 < WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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NGID3
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z NGID1
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cpu0/SLICE_319 SLICE R12C13A )
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{ NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*C)+D*(~A+C)) K0::H0=(~B*(C*A)+B*(~C+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 y K0 x REG1 { REG0 z Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 t NGID2 NGID3 cpu0/regs/SLICE_320 SLICE R21C21A )
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textctrl/SLICE_29 SLICE R25C10A MODE:CCU2 REG1:#ON Q1:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x000A,S1=0xF002::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 = REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 > WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*B+C*(B+D)) K0::H0=(~A*D+A*(D+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 } K0 | REG1 REG0 ~ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 F NGID1 C NGID2 NGID3 cpu0/regs/SLICE_321 SLICE R19C21D )
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y NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*D+C*(D+B)) K0::H0=(~C*B+C*(B+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 G NGID1 H NGID2 NGID3 cpu0/regs/SLICE_322 SLICE R19C21B )
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textctrl/SLICE_30 SLICE R24C10B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B+A*(B+D)) K0::H0=(~A*D+A*(D+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 I NGID1 E NGID2 NGID3 cpu0/regs/SLICE_323 SLICE R21C21C )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0xF008,S1=0x3008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 @ REG0 ? Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 A WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*C+A*(C+D)) K0::H0=(~A*B+A*(B+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 D NGID1 B NGID2 NGID3 cpu0/regs/SLICE_324 SLICE R22C20B )
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f NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~A*B+A*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 L NGID1 M NGID2 NGID3 cpu0/regs/SLICE_325 SLICE R22C19B )
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g NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*D+B*C) K0::H0=(~D*B+D*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 T NGID1 X NGID2 NGID3 cpu0/regs/SLICE_326 SLICE R22C18A )
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textctrl/SLICE_31 SLICE R24C10A MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 C REG0 B Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 D WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A+D*B) K0::H0=(~D*C+D*B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [ NGID1 ` NGID2 NGID3 cpu0/regs/SLICE_327 SLICE R21C19C )
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d NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*C+B*D) K0::H0=(~B*C+B*D) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 c NGID1 i NGID2 NGID3 cpu0/regs/SLICE_328 SLICE R17C20A )
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e NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*~B)+C*(B+A)) K0::H0=(~B*(D*~A)+B*(A+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 r NGID3 scpu0/regs/SLICE_329 SLICE R15C19D )
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textctrl/SLICE_32 SLICE R24C9D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 F REG0 E Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 G WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*~D)+B*(D+C)) K0::H0=(~A*(B*~D)+A*(D+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 t NGID3 ucpu0/regs/SLICE_330 SLICE R16C19B )
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b NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(B*~A)+D*(A+B)) K0::H0=(~D*(C*~B)+D*(B+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 v NGID3 wcpu0/regs/SLICE_331 SLICE R16C19A )
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c NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(A*~C)+B*(C+A)) K0::H0=(~B*(A*~C)+B*(C+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 x NGID3 ycpu0/regs/SLICE_332 SLICE R16C21D )
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textctrl/SLICE_33 SLICE R24C9C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 I REG0 H Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 J WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*~B)+D*(B+A)) K0::H0=(~D*(C*~B)+D*(B+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 # NGID1 ) NGID2 z NGID3 {cpu0/regs/SLICE_333 SLICE R15C24B )
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` NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(C*~A)+D*(A+C)) K0::H0=(~D*(A*~C)+D*(C+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 - NGID1 1 NGID2 | NGID3 }cpu0/regs/SLICE_334 SLICE R15C23A )
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a NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(B*~C)+D*(C+B)) K0::H0=(~A*(B*~D)+A*(D+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 5 NGID1 9 NGID2 ~ NGID3 cpu0/regs/SLICE_335 SLICE R17C24D )
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textctrl/SLICE_34 SLICE R24C9B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xF008,S1=0xF008::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 L REG0 K Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 M WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(C*~B)+D*(B+C)) K0::H0=(~B*(A*~C)+B*(C+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 < NGID1 A NGID2 NGID3 cpu0/regs/SLICE_336 SLICE R17C20D )
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^ NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*~C)+D*(C+A)) K0::H0=(~B*(C*~D)+B*(D+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 b NGID3 ccpu0/regs/SLICE_337 SLICE R16C18C )
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_ NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*~D)+C*(D+B)) K0::H0=(~B*(C*~D)+B*(D+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 d NGID3 ecpu0/regs/SLICE_338 SLICE R15C18A )
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textctrl/SLICE_35 SLICE R24C9A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(A*~C)+B*(C+A)) K0::H0=(~B*(C*~A)+B*(A+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 f NGID3 gcpu0/regs/SLICE_339 SLICE R17C18D )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON Q1:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0xF008::B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 N REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 O WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(D*~A)+B*(A+D)) K0::H0=(~A*(D*~B)+A*(B+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 h NGID3 icpu0/regs/SLICE_340 SLICE R16C21A )
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] NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*~B)+C*(B+D)) K0::H0=(~C*(D*~B)+C*(B+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 ( NGID2 j NGID3 kcpu0/regs/SLICE_341 SLICE R15C24A )
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cpu0/SLICE_36 SLICE R16C17A AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x2D27::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 Q WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/ea/SLICE_37 SLICE R19C20A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(C*~A)+D*(A+C)) K0::H0=(~C*(D*~A)+C*(A+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 0 NGID2 l NGID3 mcpu0/regs/SLICE_342 SLICE R15C20D )
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! " # $ % & ' ( CMODE:CCU2 F0:F CCU2::S0=0x3036,S1=0x300A::D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 T WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Dcpu0/regs/ea/SLICE_38 SLICE R19C19D 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7B78,S1=0x7B78 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 U WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ecpu0/regs/ea/SLICE_39 SLICE R19C19C 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7B78,S1=0x7B78 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 V WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Fcpu0/regs/ea/SLICE_40 SLICE R19C19B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*~B)+A*(B+D)) K0::H0=(~B*(C*~A)+B*(A+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 8 NGID2 n NGID3 ocpu0/regs/SLICE_343 SLICE R17C24B )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x1EEE,S1=0x7B78 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 W WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Gcpu0/regs/ea/SLICE_41 SLICE R19C19A 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7B78,S1=0xD222 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 X WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Hcpu0/regs/ea/SLICE_42 SLICE R19C18D 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7B78,S1=0x7B78 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 Y WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Icpu0/regs/ea/SLICE_43 SLICE R19C18C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*~D)+B*(D+C)) K0::H0=(~A*(C*~D)+A*(D+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 = NGID1 @ NGID2 p NGID3 qcpu0/regs/SLICE_344 SLICE R14C20A )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7B78,S1=0xB444 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 Z WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Jcpu0/regs/ea/SLICE_44 SLICE R19C18B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*~D*A)+(C*~A)+(C*~D)+(C*B) K0::H0=(C*B)+(D*~B)+(D*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 /cpu0/regs/SLICE_345 SLICE R18C22B )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xB444,S1=0x7D78 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 [ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Kcpu0/regs/ea/SLICE_45 SLICE R19C18A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(D*A)+B*(~A+D)) K0::H0=(~C*(B*D)+C*(~D+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 K NGID1 S NGID2 NGID3 cpu0/regs/SLICE_346 SLICE R14C19B )
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! " # $ % & ' ( AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x7D78::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 \ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Lcpu0/regs/SLICE_46 SLICE R15C24A MODE:CCU2 REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF CCU2::S0=0x5006,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 ^ REG0 ] Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 _ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 Mcpu0/regs/SLICE_47 SLICE R15C23D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 a REG0 ` Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 b WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 w NGID2 Ncpu0/regs/SLICE_48 SLICE R15C23C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 d REG0 c Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 e WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 Ocpu0/regs/SLICE_49 SLICE R15C23B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 g REG0 f Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 h WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 Pcpu0/regs/SLICE_50 SLICE R15C23A MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 j REG0 i Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 k WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 Qcpu0/regs/SLICE_51 SLICE R15C22D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~A*D+A*C)+B*C) K0::H0=(~D*(C*A)+D*(~A+C)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \ NGID1 $ NGID2 cpu0/regs/SLICE_347 SLICE R22C21D )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 m REG0 l Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 n WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 Rcpu0/regs/SLICE_52 SLICE R15C22C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*B)+(C*A) K0::H0=(C*B)+(A*~B)+(A*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 Ucpu0/regs/SLICE_348 SLICE R22C21B )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 p REG0 o Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 q WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 Scpu0/regs/SLICE_53 SLICE R15C22B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*B)+(D*A) K0::H0=(A*B)+(D*~B)+(D*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 Wcpu0/regs/SLICE_349 SLICE R17C22D )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x3036,S1=0x3006::D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 s REG0 r Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 t WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 { NGID1 NGID2 Tcpu0/regs/ea/SLICE_54 SLICE R15C22A KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x5009::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 u WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ucpu0/regs/SLICE_55 SLICE R11C24A MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0x7087,S1=0x5095::D0=0,D1=0 4 MODE K1 K0 REG1 w REG0 v Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 x WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 8 NGID1 9 NGID2 cpu0/regs/SLICE_56 SLICE R11C23D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 z REG0 y Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 { WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 6 NGID1 7 NGID2 cpu0/regs/SLICE_57 SLICE R11C23C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 } REG0 | Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ~ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 5 NGID2 cpu0/regs/SLICE_58 SLICE R11C23B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 2 NGID1 3 NGID2 cpu0/regs/SLICE_59 SLICE R11C23A MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 0 NGID1 1 NGID2 cpu0/regs/SLICE_60 SLICE R11C22D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1 / NGID2 cpu0/regs/SLICE_61 SLICE R11C22C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 - NGID2 cpu0/regs/SLICE_62 SLICE R11C22B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x7087,S1=0x7087::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 + NGID2 cpu0/regs/SLICE_63 SLICE R11C22A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*B)+(~D*A) K0::H0=(D*C)+(B*~C)+(B*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1
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! " # $ % & ' ( AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x30FE::A0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_64 SLICE R10C27A MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0xB04B,S1=0x5059::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 H NGID1 I NGID2 cpu0/regs/SLICE_65 SLICE R10C26D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 F NGID1 G NGID2 cpu0/regs/SLICE_66 SLICE R10C26C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 D NGID1 E NGID2 cpu0/regs/SLICE_67 SLICE R10C26B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 B NGID1 C NGID2 cpu0/regs/SLICE_68 SLICE R10C26A MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @ NGID1 A NGID2 cpu0/regs/SLICE_69 SLICE R10C25D MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 ? NGID2 cpu0/regs/SLICE_70 SLICE R10C25C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 < NGID1 = NGID2 cpu0/regs/SLICE_71 SLICE R10C25B MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0xB04B,S1=0xB04B::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 : NGID1 ; NGID2 cpu0/regs/SLICE_72 SLICE R10C25A AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x50FE::A0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/regs/SLICE_73 SLICE R19C28A )
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NGID2 NGID3 Zcpu0/regs/SLICE_350 SLICE R19C24D )
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! " # $ % & ' ( MODE:CCU2 REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF CCU2::S0=0x30AC,S1=0x300A::D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 n NGID1 o NGID2 cpu0/regs/SLICE_74 SLICE R19C27D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*A)+(C*B) K0::H0=(B*A)+(D*~A)+(D*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 NGID2 NGID3 \cpu0/regs/SLICE_351 SLICE R19C23B )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 t NGID1 Q NGID2 cpu0/regs/SLICE_75 SLICE R19C27C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x300A,S1=0x300A::B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 m NGID1 p NGID2 cpu0/regs/SLICE_76 SLICE R19C27B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*D)+(A*B) K0::H0=(A*D)+(B*~D)+(B*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 : NGID1 NGID2 NGID3 ^cpu0/regs/SLICE_352 SLICE R10C22D )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0x500C::A0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 h NGID1 k NGID2 cpu0/regs/SLICE_77 SLICE R19C27A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*C)+(B*A) K0::H0=(C*B)+(A*~B)+(A*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 1cpu0/regs/SLICE_353 SLICE R9C17B )
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! " # $ % & ' ( MODE:CCU2 REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ! NGID1 " NGID2 cpu0/regs/SLICE_78 SLICE R19C26D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*D)+(B*C) K0::H0=(B*A)+(C*~A)+(C*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 +cpu0/regs/SLICE_354 SLICE R9C22C )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0x500C::A0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_79 SLICE R19C26C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x300A,S1=0x300A::B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_80 SLICE R19C26B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*A)+(C*D) K0::H0=(C*D)+(B*~D)+(B*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 *cpu0/regs/SLICE_355 SLICE R12C19C )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_81 SLICE R19C26A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*D)+(B*C) K0::H0=(C*D)+(A*~D)+(A*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 ,cpu0/regs/SLICE_356 SLICE R14C17D )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON Q1:Q F1:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0x300A::B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ' NGID1 cpu0/alu/alu16/a16/SLICE_82 SLICE R11C31A MMODE:CCU2 F1:F F0:F CCU2::S0=0x5006,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Jcpu0/alu/alu16/a16/SLICE_83 SLICE R11C30D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*B)+(A*B)+(A*D) K0::H0=(B*A)+(D*~A)+(D*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 -cpu0/regs/SLICE_357 SLICE R14C20C )
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Kcpu0/alu/alu16/a16/SLICE_84 SLICE R11C30C KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Lcpu0/alu/alu16/a16/SLICE_85 SLICE R11C30B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*~D*B)+(C*~B)+(C*~D)+(C*A) K0::H0=(B*D)+(C*~D)+(C*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 .cpu0/regs/SLICE_358 SLICE R15C28D )
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Mcpu0/alu/alu16/a16/SLICE_86 SLICE R11C30A KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ncpu0/alu/alu16/a16/SLICE_87 SLICE R11C29D KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ocpu0/alu/alu16/a16/SLICE_88 SLICE R11C29C )
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! " # $ % & ' ( yMODE:LOGIC K0::H0=(~D*C+D*(~A+C)) REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 0cpu0/regs/SLICE_359 SLICE R17C20C )
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Pcpu0/alu/alu16/a16/SLICE_89 SLICE R11C29B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*D)+C*(~D+B)) K0::H0=(~C*(A*D)+C*(~D+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Qcpu0/alu/alu16/a16/SLICE_90 SLICE R11C29A )
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K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 N NGID1 W NGID2 NGID3 cpu0/regs/SLICE_360 SLICE R19C20B )
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! " # $ % & ' ( KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x3006::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Rcpu0/alu/alu16/a16/SLICE_91 SLICE R15C32A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(B*A)+D*(~A+B)) K0::H0=(~A*(D*B)+A*(~B+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _ NGID1 d NGID2 NGID3 cpu0/regs/SLICE_361 SLICE R14C18B )
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! " # $ % & ' ( CMODE:CCU2 F1:F F0:F CCU2::S0=0x30A5,S1=0x300F::D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Scpu0/alu/alu16/a16/SLICE_92 SLICE R15C31D AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x50C3,S1=0x50C3::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Tcpu0/alu/alu16/a16/SLICE_93 SLICE R15C31C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~B*D+B*A)+C*A) K0::H0=(~B*(C*D)+B*(~D+C)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 h NGID1 ! NGID2 cpu0/regs/SLICE_362 SLICE R21C24B )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x30A5,S1=0x50C3::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ucpu0/alu/alu16/a16/SLICE_94 SLICE R15C31B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*A)+B*(~A+C)) K0::H0=(~C*(D*A)+C*(~D+A)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 J NGID2 Rcpu0/regs/SLICE_363 SLICE R22C21C )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x50C3,S1=0x30A5::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Vcpu0/alu/alu16/a16/SLICE_95 SLICE R15C31A AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x50C3,S1=0x50C3::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Wcpu0/alu/alu16/a16/SLICE_96 SLICE R15C30D AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x50C3,S1=0x50C3::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Xcpu0/alu/alu16/a16/SLICE_97 SLICE R15C30C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*A)+(C*B) K0::H0=(B*D)+(C*~D)+(C*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 Scpu0/regs/SLICE_364 SLICE R18C22A )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x30A5,S1=0x50C3::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Ycpu0/alu/alu16/a16/SLICE_98 SLICE R15C30B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*C)+(D*B) K0::H0=(D*C)+(B*~C)+(B*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 Tcpu0/regs/SLICE_365 SLICE R22C21A )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x30A5,S1=0x30A5::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Zcpu0/alu/alu16/a16/SLICE_99 SLICE R15C30A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A)+(D*B) K0::H0=(B*D)+(A*~D)+(A*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 Vcpu0/regs/SLICE_366 SLICE R21C22D )
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! " # $ % & ' ( AMODE:CCU2 FCO:FCO CCU2::S0=0x000A,S1=0x30A5::A0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [cpu0/alu/alu16/a16/SLICE_100 SLICE R10C31A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A)+(D*C) K0::H0=(D*B)+(C*~B)+(C*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 ! REG1 REG0 " Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 Xcpu0/regs/SLICE_367 SLICE R21C21B )
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! " # $ % & ' ( 9MODE:CCU2 F1:F F0:F CCU2::S0=0x72D8,S1=0x3004::C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \cpu0/alu/alu16/a16/SLICE_101 SLICE R10C30D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*A)+(C*B) K0::H0=(D*C)+(A*~C)+(A*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 $ REG1 REG0 % Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 Ycpu0/regs/SLICE_368 SLICE R21C22B )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ]cpu0/alu/alu16/a16/SLICE_102 SLICE R10C30C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*C)+(A*B) K0::H0=(D*B)+(A*~B)+(A*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 ' REG1 REG0 ( Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 1 NGID1
NGID2 NGID3 [cpu0/regs/SLICE_369 SLICE R19C23D )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ^cpu0/alu/alu16/a16/SLICE_103 SLICE R10C30B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*A)+(C*B) K0::H0=(A*D)+(C*~D)+(C*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 * REG1 REG0 + Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 7 NGID1 NGID2 NGID3 ]cpu0/regs/SLICE_370 SLICE R19C23C )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _cpu0/alu/alu16/a16/SLICE_104 SLICE R10C30A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*A)+(C*D) K0::H0=(A*B)+(D*~B)+(D*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 - REG1 REG0 . Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 = NGID1 NGID2 NGID3 _cpu0/regs/SLICE_371 SLICE R21C23C )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 `cpu0/alu/alu16/a16/SLICE_105 SLICE R10C29D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*C)+(A*D) K0::H0=(A*B)+(D*~B)+(D*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 0 REG1 REG0 1 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @ NGID1 NGID2 NGID3 `cpu0/regs/SLICE_372 SLICE R21C24A )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x74B8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 acpu0/alu/alu16/a16/SLICE_106 SLICE R10C29C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*C)+(B*A) K0::H0=(C*B)+(D*~B)+(D*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 3 REG1 REG0 4 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 C NGID1 NGID2 NGID3 acpu0/SLICE_373 SLICE R14C21C )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x74B8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 bcpu0/alu/alu16/a16/SLICE_107 SLICE R10C29B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*D)+(C*~A)+(~C*B) K0::H0=(B*D)+(~B*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 6 REG1 REG0 7 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 x NGID2 y NGID3 _cpu0/SLICE_374 SLICE R12C21C )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x72D8,S1=0x72D8 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ccpu0/alu/alu16/a16/SLICE_108 SLICE R10C29A FMODE:CCU2 F1:F FCO:FCO CCU2::S0=0x300A,S1=0x705A::A0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 dcpu0/alu/alu16/a16/SLICE_109 SLICE R15C35A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*B)+(A*~C)+(~A*D) K0::H0=(A*B)+(~A*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 9 REG1 REG0 : Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 { NGID2 | NGID3 `cpu0/SLICE_375 SLICE R9C25D )
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! " # $ % & ' ( >MODE:CCU2 F1:F F0:F CCU2::S0=0x7078,S1=0x300E::D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ecpu0/alu/alu16/a16/SLICE_110 SLICE R15C34D AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 fcpu0/alu/alu16/a16/SLICE_111 SLICE R15C34C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*A)+(D*~C)+(~D*B) K0::H0=(A*C)+(~A*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 < REG1 REG0 = Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ~ NGID2 NGID3 acpu0/SLICE_376 SLICE R14C22C )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 gcpu0/alu/alu16/a16/SLICE_112 SLICE R15C34B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*C)+(D*~A)+(~D*B) K0::H0=(B*C)+(~B*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 ? REG1 REG0 @ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 bcpu0/SLICE_377 SLICE R14C21B )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 hcpu0/alu/alu16/a16/SLICE_113 SLICE R15C34A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*A)+(C*~D)+(~C*B) K0::H0=(C*A)+(~C*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 B REG1 REG0 C Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 ccpu0/SLICE_378 SLICE R12C21D )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 icpu0/alu/alu16/a16/SLICE_114 SLICE R15C33D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*A)+(D*~B)+(~D*C) K0::H0=(C*D)+(~C*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 E REG1 REG0 F Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 dcpu0/SLICE_379 SLICE R8C22A )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 jcpu0/alu/alu16/a16/SLICE_115 SLICE R15C33C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*A)+(D*~B)+(~D*C) K0::H0=(D*B)+(~D*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 H REG1 REG0 I Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 ecpu0/SLICE_380 SLICE R9C25B )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 kcpu0/alu/alu16/a16/SLICE_116 SLICE R15C33B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*A)+(B*~D)+(~B*C) K0::H0=(A*B)+(~A*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 K REG1 REG0 L Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 fcpu0/SLICE_381 SLICE R21C31B )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7078,S1=0x7078::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 lcpu0/alu/alu16/a16/SLICE_117 SLICE R15C33A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C*(A*B))) K0::H0=(~D*(~C*(B+A)+C*B)+D*(~C*B+C*(B+A))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 N K0 M REG1 REG0 O Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 ^cpu0/SLICE_382 SLICE R16C27D )
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! " # $ % & ' ( FMODE:CCU2 F1:F FCO:FCO CCU2::S0=0x500C,S1=0x7096::B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 mcpu0/alu/alu16/mulu/SLICE_118 SLICE R17C35B RMODE:CCU2 F0:F CCU2::S0=0x300A,S1=0x0000::A0=0,B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_119 SLICE R17C35A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~D*(~C*A))) K0::H0=(((B*D)+C)+A) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 Q K0 P REG1 REG0 R Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1
NGID2 ]SLICE_383 SLICE R2C25B )
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! " # $ % & ' (
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*((B+A)+C)) K0::H0=~A REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 T K0 S REG1 REG0 U Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 SLICE_384 SLICE R25C31D )
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! " # $ % & ' ( AMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x101E,S1=0x101E::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_122 SLICE R17C34B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A@D) K0::H0=(~C*~D+C*(~B*~D+B*(~A*~D))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 W K0 V REG1 Y REG0 X Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( FMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xF006,S1=0x101E::C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_123 SLICE R17C34A FMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x7078::A0=0,B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_124 SLICE R12C35A )
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{ NGID1
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! " # $ % & ' ( MODE:CCU2 REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ~ NGID2 cpu0/alu/alu16/mulu/SLICE_125 SLICE R12C34D )
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NGID2 NGID3 SLICE_385 SLICE R25C31B )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x3006,S1=0x500C::C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_126 SLICE R12C34C MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_127 SLICE R12C34B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C@(B*(A*D))) K0::H0=(B@(A*D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 [ K0 Z REG1 ] REG0 \ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_128 SLICE R12C34A )
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NGID1
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_129 SLICE R12C33D )
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NGID2 NGID3 cpu0/SLICE_386 SLICE R17C33D )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x9096,S1=0x5096::D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_130 SLICE R12C33C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*((A+C)+D)+B*A) K0::H0=A+(~C*D)+B REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:ENABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 _ K0 ^ REG1 a REG0 ` Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x300A,S1=0x7078::B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_131 SLICE R12C33B )
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NGID4
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_132 SLICE R12C33A )
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cpu0/SLICE_387 SLICE R17C33A )
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! " # $ % & ' ( PMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x500C::A0=0,B0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_133 SLICE R11C35A MMODE:CCU2 F1:F F0:F CCU2::S0=0x7008,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_134 SLICE R11C34D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A+B)+D*((A+C)+B)) K0::H0=(~D*(B+C)+D*((B+A)+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:ENABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 c K0 b REG1 e REG0 d Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 NGID2
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2
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NGID3
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WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_135 SLICE R11C34C )
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cpu0/SLICE_388 SLICE R17C33C )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_136 SLICE R11C34B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*~D)+C*~A) K0::H0=(~C*(~B*(~A*~D))+C*~D) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:ENABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 g K0 f REG1 i REG0 h Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_137 SLICE R11C34A AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x7888::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2
WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_138 SLICE R10C33A MMODE:CCU2 F1:F F0:F CCU2::S0=0x7008,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_139 SLICE R10C32D )
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NGID1 NGID2
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_140 SLICE R10C32C )
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NGID3 textctrl/SLICE_389 SLICE R23C29B )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_141 SLICE R10C32B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D+~B)) K0::H0=(~B*(~C*(~A*~D))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 LSRMUX:LSR SRMODE:LSR_OVER_CE LSRONMUX:LSRMUX REGMODE:FF 4 MODE K1 k K0 j REG1 REG0 l Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_142 SLICE R10C32A )
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l NGID1
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! " # $ % & ' ( AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x7888::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_143 SLICE R9C33A MMODE:CCU2 F1:F F0:F CCU2::S0=0x7008,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_144 SLICE R9C32D )
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q NGID2 SLICE_391 SLICE R9C16C )
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_145 SLICE R9C32C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D*(~B*~A))) K0::H0=(((D+C)+A)+B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 n K0 m REG1 p REG0 o Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 a NGID1 k NGID2
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_146 SLICE R9C32B )
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` NGID3
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! " # $ % & ' ( 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x7888,S1=0x7888 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_147 SLICE R9C32A )
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aSLICE_392 SLICE R12C22B )
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! " # $ % & ' ( AMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x7888::A0=0,B0=0,C0=0,D0=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu16/mulu/SLICE_148 SLICE R11C33B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*~C) K0::H0=(~C*(D*B)+C*(~D+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 r K0 q REG1 t REG0 s Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( MODE:CCU2 REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF CCU2::S0=0x500C,S1=0x300A::A0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_149 SLICE R11C33A MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x300A::C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_150 SLICE R11C32D )
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b NGID3
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_151 SLICE R11C32C )
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cSLICE_393 SLICE R14C24C )
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 ! REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 " WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_152 SLICE R11C32B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*C) K0::H0=(~D*(~A*B)+D*(B+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 v K0 u REG1 x REG0 w Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( MODE:CCU2 REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF FCO:FCO CCU2::S0=0x5096,S1=0x3006::D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 $ REG0 # Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 % WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/mulu/SLICE_153 SLICE R11C32A )
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d NGID3
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! " # $ % & ' ( FMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x306C::A0=0,B0=0,C0=0,D0=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 & WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/a8/SLICE_154 SLICE R8C28A HMODE:CCU2 F1:F F0:F CCU2::S0=0x5009,S1=0x300F::C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ) WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
cpu0/alu/alu8/a8/SLICE_155 SLICE R8C27D KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5009,S1=0x5009::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 * WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/a8/SLICE_156 SLICE R8C27C )
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eSLICE_394 SLICE R12C15A )
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3009,S1=0x5009::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 + WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/a8/SLICE_157 SLICE R8C27B KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5009,S1=0x5009::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 , WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/a8/SLICE_158 SLICE R8C27A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=~C K0::H0=~D REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 z K0 y REG1 | REG0 { Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( FMODE:CCU2 FCO:FCO CCU2::S0=0x500C,S1=0x3009::B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 - WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/a8/SLICE_159 SLICE R9C27A MMODE:CCU2 F1:F F0:F CCU2::S0=0x5006,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 . WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/a8/SLICE_160 SLICE R9C26D )
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V NGID3
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 / WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/a8/SLICE_161 SLICE R9C26C KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 0 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/a8/SLICE_162 SLICE R9C26B )
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WSLICE_395 SLICE R12C15B MODE:LOGIC K1::H1=~A K0::H0=~A REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 ~ K0 } REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 1 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/a8/SLICE_163 SLICE R9C26A )
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X NGID3
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! " # $ % & ' ( KMODE:CCU2 F1:F FCO:FCO CCU2::S0=0x300A,S1=0x3006::A0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/SLICE_164 SLICE R7C30A MMODE:CCU2 F0:F CCU2::S0=0x300A,S1=0x300A::B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 3 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/SLICE_165 SLICE R7C29D UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xF001,S1=0xF001::B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 4 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/SLICE_166 SLICE R7C29C )
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YSLICE_396 SLICE R12C15C )
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! " # $ % & ' ( UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xF001,S1=0xF001::B0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 5 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/SLICE_167 SLICE R7C29B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=~C K0::H0=~D REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( UMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0xF001,S1=0xF001::B0=0,C0=0,D0=0,A1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 6 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/alu/alu8/SLICE_168 SLICE R7C29A KMODE:CCU2 FCO:FCO CCU2::S0=0x000A,S1=0xF001::A0=0,C0=0,D0=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 7 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_169 SLICE R24C26A HMODE:CCU2 F0:F CCU2::S0=0x5006,S1=0x300A::C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 8 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_170 SLICE R24C25D )
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Z NGID3
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 9 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_171 SLICE R24C25C )
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[SLICE_397 SLICE R19C17A )
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 : WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*~D)+C*(D+B)) K0::H0=(~C*(~B*(~D+A)+B*~D)+C*((~D+A)+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 m NGID2
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cpu0/SLICE_172 SLICE R24C25B )
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\ NGID3
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x5006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ; WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_173 SLICE R24C25A )
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]textctrl/SLICE_398 SLICE R23C28B )
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 < WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_174 SLICE R24C24D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(B*A)+D*(~B*A)) K0::H0=(~B*A) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 = WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
cpu0/SLICE_175 SLICE R24C24C )
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| NGID1
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x5006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 > WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_176 SLICE R24C24B )
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y NGID2
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! " # $ % & ' ( KMODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x3006,S1=0x3006::C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 ? WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_177 SLICE R24C24A KMODE:CCU2 FCO:FCO CCU2::S0=0x300A,S1=0x5006::A0=0,B0=0,C0=0,D0=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 @ WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_178 SLICE R16C19A CMODE:CCU2 F0:F CCU2::S0=0x5065,S1=0x300A::D0=0,A1=0,B1=0,C1=0,D1=0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 A WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_179 SLICE R16C18D 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x221D,S1=0x221D 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 B WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_180 SLICE R16C18C 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x221D,S1=0x221D 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 C WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_181 SLICE R16C18B 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x212D,S1=0x221D 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 D WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_182 SLICE R16C18A 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x221D,S1=0x221D 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 E WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_183 SLICE R16C17D 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x221D,S1=0x221D 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 F WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_184 SLICE R16C17C 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x221D,S1=0x221D 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 G WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_185 SLICE R16C17B 6MODE:CCU2 F1:F F0:F FCO:FCO CCU2::S0=0x221D,S1=0x221D 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 H WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 cpu0/SLICE_186 SLICE R21C17C )
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G NGID3
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C+B)+D*((~C+B)+A)) K0::H0=(~D*(~A+C)+D*((~A+C)+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 J K0 I REG1 L REG0 K Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 9 NGID1 NGID2 NGID3 cpu0/SLICE_187 SLICE R22C17D )
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Htextctrl/SLICE_399 SLICE R23C28C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~A+D)+B*((~A+D)+C)) K0::H0=(~B*(~A+D)+B*((~A+D)+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 N K0 M REG1 P REG0 O Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_188 SLICE R23C17C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D*A)+C*(D*A)) K0::H0=(~D*(C*(B*A))+D*(~C*A+C*(~B*A))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~B+C)+A*((~B+C)+D)) K0::H0=(~A*(~B+D)+A*((~B+D)+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 R K0 Q REG1 T REG0 S Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_189 SLICE R21C18D )
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x NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~B+D)+C*((~B+D)+A)) K0::H0=(~C*(~B+A)+C*((~B+A)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 V K0 U REG1 X REG0 W Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ; NGID2 NGID3 cpu0/SLICE_190 SLICE R23C18C )
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w NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~B+A)+C*((~B+A)+D)) K0::H0=(~C*(~B+D)+C*((~B+D)+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 Z K0 Y REG1 \ REG0 [ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 = NGID1 NGID2 NGID3 cpu0/SLICE_191 SLICE R23C18B )
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I NGID3
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A+B)+C*((~A+B)+D)) K0::H0=(~A*(~B+D)+A*((~B+D)+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 ^ K0 ] REG1 ` REG0 _ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_192 SLICE R22C17C )
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Jtextctrl/SLICE_400 SLICE R21C29B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~B+D)+C*((~B+D)+A)) K0::H0=(~C*(~B+A)+C*((~B+A)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 b K0 a REG1 d REG0 c Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 5 NGID1 NGID2 NGID3 cpu0/SLICE_193 SLICE R17C19A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*D)+A*(~D+B)) K0::H0=(B*(A*(C*D))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C+A)+B*((~C+A)+D)) K0::H0=(~B*(~C+A)+B*((~C+A)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 f K0 e REG1 h REG0 g Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 7 NGID1 NGID2 NGID3 cpu0/SLICE_194 SLICE R18C31D )
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NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*(~D*A)+C*(A+D))+B*A) K0::H0=(~B*(~C*(~D*A)+C*(A+D))+B*A) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 j K0 i REG1 REG0 k Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 B NGID2 cpu0/SLICE_195 SLICE R18C25A )
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NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~A*(~B*C)+A*(C+B))+D*C) K0::H0=((D+~(~A+~C))*B)+(((~A+~C)*D)*~B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 m K0 l REG1 o REG0 n Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 F NGID3 NGID4 cpu0/alu/alu16/mulu/SLICE_196 SLICE R16C30C )
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? NGID3
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~C*(~D*B)+C*(B+D))+A*B) K0::H0=(~A*(~C*(~D*B)+C*(B+D))+A*B) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 q K0 p REG1 REG0 r Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 } NGID1 NGID2 cpu0/alu/alu8/SLICE_197 SLICE R23C25C )
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@textctrl/SLICE_401 SLICE R22C29D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=((D+~(~B+~C))*A)+(((~B+~C)*D)*~A) K0::H0=((B+~(~A+~C))*D)+(((~A+~C)*B)*~D) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 t K0 s REG1 v REG0 u Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 NGID4 NGID5 cpu0/alu/alu16/mulu/SLICE_198 SLICE R12C32D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*B)+A*(~B+D)) K0::H0=(~D*(A*B)+D*(~B+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*B)+A*(~D*C+D*(B@C))) K0::H0=(D*B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 x K0 w REG1 z REG0 y Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/alu/alu16/SLICE_199 SLICE R16C30D )
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NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=~D K0::H0=(~D*C+D*(B@C)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 | K0 { REG1 REG0 } Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_201 SLICE R9C21C )
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NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~C+~B)+A*(B+C)) K0::H0=(~A*C+A*D) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 ~ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 NGID2 lcpu0/SLICE_202 SLICE R15C26B )
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A NGID3
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~A*C+A*B)+D*B) K0::H0=(~D*(~A*B+A*C)+D*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 C NGID1 A NGID2 NGID3 cpu0/alu/SLICE_203 SLICE R22C27D )
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Btextctrl/SLICE_402 SLICE R22C29C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*A)+(~B*~C)+(B*D) K0::H0=(C*~B)+(A*B)+(A*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_204 SLICE R15C28D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(A*C)+B*(~C+A)) K0::H0=(~D*(A*C)+D*(~C+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*B+A*D)+C*D) K0::H0=(~D*(~A*B+A*C)+D*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_205 SLICE R12C28A )
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NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~B*A+B*C)+D*C) K0::H0=(~A*(~B*D+B*C)+A*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 B NGID1 NGID2 NGID3 cpu0/SLICE_206 SLICE R14C25A )
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NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~B*(C*D)+B*(~C+D))+A*D) K0::H0=(~C*(~A*D+A*B)+C*B) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 - NGID2 cpu0/SLICE_207 SLICE R21C29B )
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C NGID3
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B)+(A*D)+~C K0::H0=(C*~A)+(D*A)+(D*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 q NGID2 r NGID3 cpu0/alu/SLICE_208 SLICE R17C27A )
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Dtextctrl/SLICE_403 SLICE R22C29A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*B)+(D*A)+~C K0::H0=(B*~C)+(A*C)+(A*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ) NGID1 NGID2 NGID3 cpu0/alu/SLICE_209 SLICE R22C28B MODE:LOGIC K1::H1=(~C*A)+(C*B)+~D K0::H0=(B*~A)+(C*A)+(C*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_210 SLICE R17C28B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~B*(D*A)+B*(~A+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A)+(D*B)+~C K0::H0=(D*~A)+(B*A)+(B*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 t NGID2 u NGID3 cpu0/alu/SLICE_211 SLICE R17C28D )
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NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A)+(D*B)+~C K0::H0=(C*~A)+(B*A)+(B*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_212 SLICE R22C29C )
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NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*D)+(A*B)+~C K0::H0=(A*~C)+(D*C)+(D*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 w NGID2 x NGID3 cpu0/alu/SLICE_213 SLICE R16C28C )
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E NGID3
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*C)+(B*A)+~D K0::H0=(A*~D)+(C*D)+(C*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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FSLICE_404 SLICE R14C29D )
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NGID3 cpu0/alu/SLICE_214 SLICE R21C29D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C+D) K0::H0=(C@A) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 r NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B)+(A*D)+~C K0::H0=(B*~A)+(D*A)+(D*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 NGID2 NGID3 cpu0/alu/SLICE_215 SLICE R18C30A )
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7 NGID3
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*B)+A*(~D+B)) K0::H0=(~B*(D*C)+B*(~D+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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8textctrl/SLICE_405 SLICE R22C30B )
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NGID1 NGID2 NGID3 cpu0/alu/SLICE_216 SLICE R17C29D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D+B) K0::H0=(B@C) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C*D)+A*(~C+D)) K0::H0=(~B*(C*A)+B*(~C+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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NGID1
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NGID1
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NGID2
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NGID2 NGID3 cpu0/SLICE_217 SLICE R16C30B )
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9 NGID3
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*D)+C*(~A+D)) K0::H0=(~B*(A*C)+B*(~A+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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:textctrl/SLICE_406 SLICE R22C29B )
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NGID1 NGID2 NGID3 cpu0/alu/SLICE_218 SLICE R17C30C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*C) K0::H0=(~D*(~C*(~B*A))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*D)+A*(~B+D)) K0::H0=(~C*(D*B)+C*(~D+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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NGID1
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NGID2 NGID3 cpu0/SLICE_219 SLICE R16C28A )
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NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*A*C)+(D*B*A)+(~B*~A) K0::H0=A*D REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_220 SLICE R16C29C )
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; NGID3
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*~D+A*(C+B)) K0::H0=(~C*(A*D)+C*((A*D)+B)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/SLICE_221 SLICE R17C29B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*~D)+(A*~D)+(A*B) K0::H0=B*D REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B+(~D+~A)) K0::H0=(D+A) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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NGID2
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NGID1
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NGID3 cpu0/alu/SLICE_222 SLICE R17C29C )
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NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*A*B)+(D*C*A)+(~C*~A) K0::H0=B*C REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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= NGID3
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NGID2
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>textctrl/SLICE_408 SLICE R23C29D )
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NGID3 cpu0/alu/SLICE_223 SLICE R17C29A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(((~A+B)+C)+D) K0::H0=(~B*(~C*(~A*~D))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 LSRMUX:LSR SRMODE:LSR_OVER_CE LSRONMUX:LSRMUX REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*A*D)+(C*B*A)+(~B*~A) K0::H0=A*C REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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m NGID1
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NGID2
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r NGID2
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NGID3 cpu0/alu/SLICE_224 SLICE R18C29D )
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6cpu0/test_cond/cond_taken_15_0/SLICE_409 SLICE R14C29A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*C*B)+(A*D*C)+(~D*~C) K0::H0=A*B REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( vMODE:LOGIC K1::H1=(~B*~D*~A)+(~D*~C*~A)+(B*C*A)+(D*A) K0::H0=(C*~A*~B)+(C*A*B)+(~C*D) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/test_cond/cond_taken_8/SLICE_410 SLICE R14C29B )
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NGID2
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! " # $ % & ' ( gMODE:LOGIC K1::H1=(~C*~B*~D)+(~A*B*~D)+(C*~B*D)+(A*B*D) K0::H0=(A*B*C)+(~B*~C)+(~A*~B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_alu/alu_opcode_2_4_0_.m20/SLICE_411 SLICE R10C31B )
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NGID3 cpu0/alu/SLICE_225 SLICE R16C29D )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(B*~C)+(D*C) K0::H0=(C*B)+(~C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_alu/alu_opcode_2_4_0_.m60/SLICE_412 SLICE R10C30D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*B*C)+(A*D*B)+(~D*~B) K0::H0=C*D REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*D)+(~B*D)+(~B*A) K0::H0=(D*A)+(~D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_alu/alu_opcode_2_4_0_.m30/SLICE_413 SLICE R8C30D )
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NGID2
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! " # $ % & ' ( VMODE:LOGIC K1::H1=(~B*~D)+(~B*~C)+(B*~A) K0::H0=(~D*~B)+(D*~A)+(D*~C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_alu/alu_opcode_2_4_0_.m41/SLICE_414 SLICE R9C31B )
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NGID3 cpu0/alu/SLICE_226 SLICE R17C30A )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~C*D)+(C*B) K0::H0=(~A*~D*B)+(A*D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_alu/alu_opcode_2_4_0_.m9/SLICE_415 SLICE R10C31A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*~D)+(A*~D)+(A*B) K0::H0=B*A REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( 5MODE:LOGIC K1::H1=A*D*~C K0::H0=~A*D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 NGID2 cpu0/dec_alu/alu_opcode_2_4_0_.m47/SLICE_416 SLICE R9C31A )
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NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*D*~A)+(~C*~B*~A)+(B*~D*A)+(~C*B*~D) K0::H0=(A*D*~C)+(A*~B*~C)+(~A*B*~C)+(~A*B*~D) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 NGID2 cpu0/dec_alu/alu_opcode_2_4_0_.m54/SLICE_417 SLICE R9C30D )
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NGID2
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~D*~A*~B)+(D*~A*B) K0::H0=(B*~A*C)+(B*A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 NGID2 cpu0/dec_alu/alu_opcode_2_4_0_.m33/SLICE_418 SLICE R8C30C )
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NGID3 cpu0/SLICE_227 SLICE R10C24C )
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(B*~C)+(A*C) K0::H0=(~C*~A)+(C*D) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 NGID2 cpu0/dec_op/un1_mode93_RNIC8563/SLICE_419 SLICE R12C30D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~A*C+A*D) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 N NGID2 mcpu0/SLICE_228 SLICE R11C20D )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(C*~B)+A+D K0::H0=(~B*C)+~A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
s NGID1 @ NGID2 Acpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420 SLICE R15C27B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*A+C*(A+D))+B*(~C*(~D*A)+C*(A+D))) K0::H0=(~B*(C*A)+B*(~C*(D*A)+C*A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ( NGID1 / NGID2 NGID3 cpu0/SLICE_229 SLICE R11C20B )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~A*C)+(D*~A)+B K0::H0=(~A*~D)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
v NGID1 C NGID2 Dcpu0/dec_op/optype_3_2_0_.m10/SLICE_421 SLICE R16C30D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(D+A)+B*((D+C)+A)) K0::H0=(~C*(~B*(D*~A)+B*D)+C*(~B*(D*~A)+B*(A+D))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 1 NGID2 NGID3 cpu0/SLICE_230 SLICE R11C20A )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~B*~A)+(~C*~B)+~D K0::H0=B+A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 b NGID2 ccpu0/dec_op/mode_cnst_1_0_a2_RNIOV3S[0]/SLICE_422 SLICE R14C25A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B+A*(~D+B)) K0::H0=(~B*(~A*(C*~D)+A*C)+B*(A*C)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 & NGID2 cpu0/SLICE_231 SLICE R11C26A )
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~B*D)+(~A*D)+(A*~B)+(~C*~B)+(~C*~A) K0::H0=(~A*~B)+(D*~B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 q NGID2 ?cpu0/dec_regs/path_left_addr_cnst_0_2[0]/SLICE_423 SLICE R11C30A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*A)+C*(~B+A)) K0::H0=(~B*C+B*A) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 )cpu0/SLICE_232 SLICE R11C27D )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~D*~B*C)+A K0::H0=(D*~B*C)+A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 NGID2 cpu0/regs/ea/k_new_pc_5[0]/SLICE_424 SLICE R21C24C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*~D*~C)+(D*A)+(A*C)+(B*A) K0::H0=(C*B)+(A*~B)+(A*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/dec_regs/SLICE_233 SLICE R11C16D )
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! " # $ % & ' ( sMODE:LOGIC K1::H1=(B*D*~C)+(D*~A*~C)+(B*~A*C)+(~B*A*C)+(B*D*~A)+(~B*D*A) K0::H0=(C*D)+(B*D)+(B*~C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 V NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[5]/SLICE_425 SLICE R22C19D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*~C*~A)+(D*~B*~C) K0::H0=(~A*~D)+(C*D)+(C*~A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _ NGID1 d NGID2 m NGID3 #cpu0/dec_regs/SLICE_234 SLICE R12C15A )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~A*C)+(D*C)+(D*A) K0::H0=(~C*D)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[2]/SLICE_426 SLICE R22C19A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~B*(~D*~C))+A*(~B*(~D+C)+B*C)) K0::H0=(~C*(~A*D+A*B)+C*(~A*D)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 e NGID2 $cpu0/dec_regs/SLICE_235 SLICE R14C16A )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~A*D)+(C*D)+(C*A) K0::H0=(~D*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[15]/SLICE_427 SLICE R16C22C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*~D*~C)+(~A*~D*~C)+(A*~B*~D) K0::H0=(~C*~B)+(D*B)+(D*~C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 \ NGID2 ] NGID3 %cpu0/dec_regs/SLICE_236 SLICE R12C15D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(A*C)+(A*B) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3_i_m2[14]/SLICE_428 SLICE R17C21D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*~A*~D)+(C*~B*~A) K0::H0=(~B*~D)+(C*D)+(C*~B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 _ NGID2 ` NGID3 &cpu0/dec_regs/SLICE_237 SLICE R10C18A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(C*B)+(C*D) K0::H0=(D*~B)+(C*B)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[13]/SLICE_429 SLICE R16C20B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=C+D+A+B K0::H0=(C*D)+(B*~D)+(B*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 D NGID2 E NGID3 cpu0/dec_regs/SLICE_238 SLICE R10C18D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~D)+(A*D)+(A*C) K0::H0=(A*~D)+(C*D)+(C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[12]/SLICE_430 SLICE R17C17C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*A)+B K0::H0=(~D*B)+(A*B)+(C*~B)+(C*A)+(C*~D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 G NGID2 H NGID3 cpu0/dec_regs/SLICE_239 SLICE R12C18B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(B*~A)+(D*A)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[11]/SLICE_431 SLICE R15C19C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*~A)+(~B*C)+(~D*~B) K0::H0=(~D*~C*B)+(A*~D*~C)+(A*~B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 N NGID2 O NGID3 !cpu0/dec_regs/SLICE_240 SLICE R11C18C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(C*~A)+(D*A)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[10]/SLICE_432 SLICE R15C21B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*~B)+(~A*C)+(~D*~A) K0::H0=(A*D)+(B*~D)+(B*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 J NGID2 K NGID3 "cpu0/dec_regs/SLICE_241 SLICE R14C18B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(C*A)+(C*B) K0::H0=(B*~A)+(D*A)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[9]/SLICE_433 SLICE R16C19C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=C+D+B+A K0::H0=(~C*B)+(~C*A)+(C*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Q NGID2 R NGID3 cpu0/dec_regs/SLICE_242 SLICE R17C18D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(B*~C)+(D*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[8]/SLICE_434 SLICE R17C21C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*~C+A*D) K0::H0=(~A*(~C*~D)+A*B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 j NGID2 NGID3 cpu0/dec_regs/SLICE_243 SLICE R14C18C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(D*C)+(D*A) K0::H0=(D*~C)+(B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[7]/SLICE_435 SLICE R17C18A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=D+A+B+C K0::H0=(~B*D)+(B*C)+(~B*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~A)+(C*A)+(C*D) K0::H0=(B*~A)+(D*A)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 W NGID2 X NGID3 cpu0/regs/SLICE_244 SLICE R17C17A )
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NGID2 cpu0/regs/ea/ea_reg_3[6]/SLICE_436 SLICE R18C17C )
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! " # $ % & ' ( tMODE:LOGIC K0::H0=((~C*B)+A) REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0
Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 $cpu0/regs/SLICE_245 SLICE R17C18C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(D*A)+(D*B) K0::H0=(C*~A)+(B*A)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
NGID2 cpu0/regs/ea/ea_reg_3[5]/SLICE_437 SLICE R16C18D )
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! " # $ % & ' ( sMODE:LOGIC K0::H0=((B+A)+D) REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 #cpu0/SLICE_246 SLICE R9C23A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(A*C)+(A*B) K0::H0=(B*~C)+(D*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[4]/SLICE_438 SLICE R15C18B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*D+C*A) K0::H0=(~D*(B*(~A*C))+D*((~A+~C)+B)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_247 SLICE R18C10A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(D*A)+(D*B) K0::H0=(B*~A)+(D*A)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[3]/SLICE_439 SLICE R16C18B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*~B) K0::H0=(~C*(~D*(~A*B))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_248 SLICE R19C16D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(A*~C)+(B*C)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[2]/SLICE_440 SLICE R15C17B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*(A*(~D*~C))) K0::H0=((A*(~C*D))+B) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_249 SLICE R22C18D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(A*C)+(A*B) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3_i_m2[1]/SLICE_441 SLICE R17C18C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*B)+((~(A*D)*~C)*~B) K0::H0=(~C*(~D*(~A*~B)+D*~A)+C*(~B+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 x NGID2 NGID3 | NGID4 }cpu0/SLICE_250 SLICE R22C18B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(B*C)+(B*D) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[0]/SLICE_442 SLICE R18C17D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A)+((~(C*B)*~D)*~A) K0::H0=(~C*(~D*(~A*~B)+D*~A)+C*(~B+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 ! REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 ~ NGID4 cpu0/SLICE_251 SLICE R22C17A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~D)+(A*D)+(A*B) K0::H0=(C*~D)+(B*D)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SS_16[0]/SLICE_443 SLICE R10C23D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*B)+((~(A*C)*~D)*~B) K0::H0=(~A*D)+((~(B*C)*~A)*~D) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 # K0 " REG1 % REG0 $ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 NGID4 NGID5 cpu0/SLICE_252 SLICE R22C18C )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~C*~A)+(C*A) K0::H0=(C*A)+(D*~A)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SU_16[0]/SLICE_444 SLICE R10C23C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C*(~B*~A)+C*~B)+D*(~A+C)) K0::H0=(~C*B)+((~(D*A)*~C)*~B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 ' K0 & REG1 ) REG0 ( Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 NGID4 cpu0/SLICE_253 SLICE R22C15D )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~D*~A)+(D*A) K0::H0=(C*B)+(A*~B)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[7]/SLICE_445 SLICE R17C17D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D+C)+A*(D+B)) K0::H0=(~A*(D*C)+A*B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 + K0 * REG1 - REG0 , Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 y NGID2 t NGID3 ucpu0/SLICE_254 SLICE R23C16A )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*A)+(C*D) K0::H0=(C*~B)+(A*B)+(A*C)+~D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[0]/SLICE_446 SLICE R18C20B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*~A+C*(~A+B)) K0::H0=(~B*(~D*~C)+B*(~D*(A*~C))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 / K0 . REG1 1 REG0 0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 v NGID3 wcpu0/SLICE_255 SLICE R23C14C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*D)+(A*B) K0::H0=(B*~D)+(A*D)+(A*B)+C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[1]/SLICE_447 SLICE R18C15B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D+A) K0::H0=(~C*(~B*(~D+A)+B*~D)+C*((~D+A)+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 3 K0 2 REG1 5 REG0 4 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 NGID2 x NGID3 ycpu0/SLICE_256 SLICE R23C17D )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*A)+(D*C) K0::H0=(D*~A)+(B*A)+(B*D)+~C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[2]/SLICE_448 SLICE R15C17A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C+D) K0::H0=(~D+B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 7 K0 6 REG1 9 REG0 8 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 z NGID3 {cpu0/SLICE_257 SLICE R22C15B )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*C)+(D*B) K0::H0=(D*~A)+(B*A)+(B*D)+~C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[3]/SLICE_449 SLICE R16C17B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*~D)) K0::H0=(~A*((C+D)+B)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 ; K0 : REG1 REG0 < Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 scpu0/SLICE_258 SLICE R21C17A )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*D)+(C*A) K0::H0=(A*~D)+(C*D)+(C*A)+~B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[4]/SLICE_450 SLICE R15C15D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*(B*(A*D))) K0::H0=(((A+C)+D)+B) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 > K0 = REG1 REG0 ? Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 rcpu0/SLICE_259 SLICE R18C16C )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~A*C)+(A*B) K0::H0=(A*~B)+(C*B)+(C*A)+~D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[5]/SLICE_451 SLICE R15C15A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*(B*(~D*A))) K0::H0=(~B*(~A*(D*C)+A*C)+B*C) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 A K0 @ REG1 REG0 B Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 \ NGID2 qSLICE_260 SLICE R18C14A )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*C)+(D*A) K0::H0=(D*~A)+(B*A)+(B*D)+~C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[6]/SLICE_452 SLICE R18C15D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~B*C+B*D)+A*D) K0::H0=(~B*(~D*C+D*A)+B*A) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 D K0 C REG1 F REG0 E Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*A)+(D*C) K0::H0=(C*~A)+(B*A)+(B*C)+~D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_6[15]/SLICE_453 SLICE R16C22B )
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+ NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(C*B)+(C*D) K0::H0=(A*~D)+(B*D)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 V NGID1 2 NGID2 3cpu0/regs/path_left_data_7[15]/SLICE_454 SLICE R16C22A )
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NGID2 i NGID3 jSLICE_261 SLICE R19C12A )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(D*~B)+(A*B)+(A*D) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Y NGID1 5 NGID2 6cpu0/regs/path_left_data_6[9]/SLICE_455 SLICE R17C19B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~B*C+B*A)+D*A) K0::H0=(~D*(~B*A+B*C)+D*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 H K0 G REG1 J REG0 I Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(D*~A)+(B*A)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \ NGID1 8 NGID2 9cpu0/regs/path_left_data_7[9]/SLICE_456 SLICE R17C19A )
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NGID1
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(A*~B)+(D*B)+(D*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _ NGID1 ; NGID2
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NGID2 k NGID3 lSLICE_262 SLICE R16C14C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~D)+(A*D)+(A*C) K0::H0=(A*~D)+(B*D)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 b NGID1 > NGID2 ?cpu0/regs/path_left_data_7[8]/SLICE_458 SLICE R18C21A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*A+C*D)+B*D) K0::H0=(~B*(~C*A+C*D)+B*D) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 L K0 K REG1 N REG0 M Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(B*~A)+(C*A)+(C*B) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 A NGID2 Bcpu0/regs/path_left_data_6[14]/SLICE_459 SLICE R17C22B )
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, NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(C*B)+(C*D) K0::H0=(C*~A)+(D*A)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 h NGID1 D NGID2 Ecpu0/regs/path_left_data_6[12]/SLICE_460 SLICE R15C17D )
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NGID2 m NGID3 nSLICE_263 SLICE R15C13A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(C*D)+(C*A) K0::H0=(C*~B)+(A*B)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 G NGID2 Hcpu0/regs/path_left_data_7[14]/SLICE_461 SLICE R17C22A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D*B+D*A)+C*A) K0::H0=(~A*(~D*B+D*C)+A*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 P K0 O REG1 R REG0 Q Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(C*~B)+(A*B)+(A*C) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 n NGID1 J NGID2 Kcpu0/regs/path_left_data_7[10]/SLICE_462 SLICE R15C22C )
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NGID1
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~A)+(D*A)+(D*B) K0::H0=(A*~B)+(D*B)+(D*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 q NGID1 M NGID2 Ncpu0/regs/path_left_data_6[10]/SLICE_463 SLICE R15C22D )
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NGID2 o NGID3 pcpu0/SLICE_264 SLICE R23C16D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(D*A)+(D*B) K0::H0=(D*~C)+(B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 ! REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 t NGID1 P NGID2 Qcpu0/regs/path_left_data_7[12]/SLICE_464 SLICE R15C17C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*~D)) K0::H0=C+~(~B*~A) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 T K0 S REG1 REG0 U Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~C)+(A*C)+(A*B) K0::H0=(D*~A)+(C*A)+(C*D) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 # REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 w NGID1 S NGID2 Tcpu0/regs/path_left_data_7[11]/SLICE_465 SLICE R15C22A )
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NGID3 hcpu0/SLICE_273 SLICE R18C15B )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~C)+(A*C)+(A*B) K0::H0=(C*~D)+(B*D)+(B*C) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 % REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 V NGID2 Wcpu0/regs/path_left_data_6[11]/SLICE_466 SLICE R15C22B )
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! " # $ % & ' ( MODE:LOGIC K0::H0=(~D*(C+B)+D*(~B*(C*A)+B*A)) REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 V REG1 REG0 W Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 / NGID1 Wcpu0/SLICE_286 SLICE R17C17B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(D*~A)+(C*A)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 ' REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 } NGID1 Y NGID2 Zcpu0/regs/path_left_data_7[13]/SLICE_467 SLICE R15C20A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*D)+C*(D+A)) K0::H0=(~B*(~C*A)+B*(~C*(A+D))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 Y K0 X REG1 REG0 Z Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 >cpu0/SLICE_287 SLICE R18C17D )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(D*~C)+(B*C)+(B*D) K0::H0=(A*~D)+(B*D)+(B*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 ) REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 \ NGID2 ]cpu0/regs/path_left_data_6[13]/SLICE_468 SLICE R15C20B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~B*(A*D))) K0::H0=(~D*(~C*A)+D*(~C*(B+A))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 \ K0 [ REG1 REG0 ] Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ] NGID2 =cpu0/SLICE_292 SLICE R14C10C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(B*C)+(B*A) K0::H0=(B*~D)+(C*D)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 + REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 _ NGID2 `cpu0/regs/path_left_data_6[7]/SLICE_469 SLICE R17C16D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B+D)+C*~A) K0::H0=(~C*(~D*~B)+C*~A) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 _ K0 ^ REG1 a REG0 ` Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 1 NGID3 2cpu0/SLICE_293 SLICE R14C10B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(C*B)+(C*D) K0::H0=(C*~B)+(D*B)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 - REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 b NGID2 ccpu0/regs/path_left_data_7[7]/SLICE_470 SLICE R17C16B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*D+A*(~B*(C+D)+B*D)) K0::H0=(~D*(C+B)+D*A) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 c K0 b REG1 e REG0 d Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 3 NGID3 4cpu0/SLICE_294 SLICE R15C12C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~A)+(B*A)+(B*D) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 / REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 e NGID2 fcpu0/regs/path_left_data_7[0]/SLICE_471 SLICE R18C20C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*B)+(A*B)+(A*C) K0::H0=~B*A REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 g REG1 REG0 h Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
X NGID1 NGID2 NGID3 )cpu0/SLICE_295 SLICE R14C11A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(B*C)+(B*A) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 1 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 h NGID2 icpu0/regs/path_left_data_6[0]/SLICE_472 SLICE R18C20D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*B)+(D*B)+(D*C) K0::H0=~B*~A*D REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 j REG1 REG0 k Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
j NGID1 NGID2 NGID3 *cpu0/SLICE_296 SLICE R14C12A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(C*D)+(C*A) K0::H0=(D*~B)+(C*B)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 3 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 k NGID2 lcpu0/regs/path_left_data_7[1]/SLICE_473 SLICE R17C15B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*B)+(D*B)+(D*C) K0::H0=(A*B)+(D*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 m REG1 REG0 n Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
g NGID1 NGID2 NGID3 +cpu0/SLICE_297 SLICE R14C11C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(B*~C)+(A*C)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 5 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 n NGID2 ocpu0/regs/path_left_data_6[1]/SLICE_474 SLICE R18C16D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B)+(D*B)+(D*A) K0::H0=~D*A REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 p REG1 REG0 q Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
d NGID1 NGID2 NGID3 ,cpu0/SLICE_298 SLICE R15C11B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~B)+(C*B)+(C*A) K0::H0=(B*~A)+(D*A)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 7 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 q NGID2 rcpu0/regs/path_left_data_7[2]/SLICE_475 SLICE R15C16B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*C)+(D*C)+(D*B) K0::H0=(D*C)+(D*~A)+(B*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 s REG1 REG0 t Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
^ NGID1 NGID2 NGID3 -cpu0/SLICE_299 SLICE R14C11B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(B*~C)+(A*C)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 9 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 t NGID2 ucpu0/regs/path_left_data_6[2]/SLICE_476 SLICE R15C16C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*B)+(A*B)+(A*D) K0::H0=(C*B)+(B*A)+(D*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 v REG1 REG0 w Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
a NGID1 NGID2 NGID3 .cpu0/SLICE_300 SLICE R15C10D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(B*C)+(B*A) K0::H0=(B*~A)+(D*A)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 ; REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 w NGID2 xcpu0/regs/path_left_data_7[3]/SLICE_477 SLICE R16C17A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A)+(C*A)+(C*D) K0::H0=~D*A REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 y REG1 REG0 z Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
[ NGID1 NGID2 NGID3 /cpu0/SLICE_301 SLICE R15C11A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~D)+(A*D)+(A*B) K0::H0=(D*~C)+(B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 = REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 z NGID2 {cpu0/regs/path_left_data_6[3]/SLICE_478 SLICE R16C18A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*D)+(~B*C)+(A*C)+(A*D)+(A*B) K0::H0=(A*~C)+(A*~B)+(D*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 | REG1 REG0 } Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
U NGID1 NGID2 NGID3 0cpu0/SLICE_302 SLICE R18C10D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(A*B)+(A*C) K0::H0=(C*~A)+(D*A)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 ? REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 } NGID2 ~cpu0/regs/path_left_data_7[4]/SLICE_479 SLICE R15C15B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C*(B*A))) K0::H0=(((A+C)+D)+B) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 ~ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 (cpu0/SLICE_303 SLICE R18C15D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(C*B)+(C*D) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 A REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_6[4]/SLICE_480 SLICE R15C15C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*(~C*~A)) K0::H0=(~D*C+D*((~A*~B)+C)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 'cpu0/SLICE_304 SLICE R16C16D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(A*B)+(A*D) K0::H0=(D*~A)+(B*A)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 C REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_7[5]/SLICE_481 SLICE R16C15A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C+B)+D*(~C*~A+C*(B*~A))) K0::H0=(D*(A*B)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 = NGID1 NGID2 &cpu0/SLICE_305 SLICE R15C19B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~D)+(A*D)+(A*B) K0::H0=(C*~D)+(B*D)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 E REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_6[5]/SLICE_482 SLICE R15C16A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*D+A*C) K0::H0=(~A*D+A*(~B*D+B*(C+D))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ; NGID1 NGID2 %cpu0/SLICE_306 SLICE R17C16A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(C*D)+(C*A) K0::H0=(B*~C)+(D*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 G REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_7[6]/SLICE_483 SLICE R18C15A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*(C*~D))+A*(B*(~C*~D))) K0::H0=(~C*(~A*D+A*(D*~B))+C*(~A*D)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 NGID2 $cpu0/SLICE_307 SLICE R15C17B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(B*C)+(B*A) K0::H0=(D*~B)+(A*B)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 I REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_6[6]/SLICE_484 SLICE R18C15C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~A*D)) K0::H0=(A*(C*B)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 B NGID2 #cpu0/SLICE_308 SLICE R18C11B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~D)+(A*D)+(A*B) K0::H0=(D*~A)+(B*A)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 K REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[5]/SLICE_485 SLICE R16C15B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*~D+C*(~D*A))+B*~D) K0::H0=B+A+~(~D*~C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*A)+(C*D) K0::H0=(C*~D)+(A*D)+(A*C)+~B OFX0:F M0MUX:M0 4 MODE K1 K0 M REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[2]/SLICE_486 SLICE R16C16C )
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NGID1 NGID2 NGID3 NGID4 cpu0/SLICE_309 SLICE R18C11D )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~A*C)+(A*D) K0::H0=(C*~D)+(A*D)+(A*C)+~B OFX0:F M0MUX:M0 4 MODE K1 K0 O REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[1]/SLICE_487 SLICE R18C14D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(C*(B*~A))) K0::H0=(((A+C)+B)+D) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 l NGID1 NGID2 ! NGID3 "cpu0/SLICE_311 SLICE R16C12B )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*A)+(C*B) K0::H0=(A*~C)+(B*C)+(B*A)+~D OFX0:F M0MUX:M0 4 MODE K1 K0 Q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[7]/SLICE_488 SLICE R17C15A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B+~C)+~(A*D) K0::H0=(~D*~A) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 j NGID1 NGID2 NGID3 NGID4 cpu0/SLICE_312 SLICE R16C14A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*A)+(B*C) K0::H0=(D*~B)+(A*B)+(A*D)+C OFX0:F M0MUX:M0 4 MODE K1 K0 S REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[6]/SLICE_489 SLICE R17C14A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*~D+C*A)+B*(~C+A)) K0::H0=(~D*(~C*~B)+D*~A) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 + NGID1 NGID2 NGID3 cpu0/SLICE_313 SLICE R17C13A )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~B*C)+(B*A) K0::H0=(D*~B)+(A*B)+(A*D)+~C OFX0:F M0MUX:M0 4 MODE K1 K0 U REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data_6[8]/SLICE_490 SLICE R18C21D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(((~B*A)+D)+C) K0::H0=(~A*(D*B)+A*C) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 NGID2 NGID3 cpu0/SLICE_314 SLICE R15C13B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(B*A)+(B*C) K0::H0=(C*~D)+(A*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 W REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data_7[8]/SLICE_491 SLICE R18C21C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*~C+B*A) K0::H0=(~D*A+D*(~B*A+B*(~C*A))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ) NGID2 NGID3 cpu0/regs/SLICE_315 SLICE R18C21D )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(D*~C)+(B*C)+(B*D) K0::H0=(D*~C)+(A*C)+(A*D) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 Y REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 NGID2 cpu0/regs/path_right_data_6[15]/SLICE_492 SLICE R16C22D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B+A*(B+D)) K0::H0=(~A*(B+D)+A*((B+D)+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 P NGID1 9 NGID2 NGID3 cpu0/regs/SLICE_316 SLICE R19C22D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~D)+(B*D)+(B*C) K0::H0=(C*~A)+(B*A)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 [ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 & NGID1 NGID2 cpu0/regs/path_right_data_7[15]/SLICE_493 SLICE R16C20C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*A+B*(A+D)) K0::H0=(~C*D+C*(D+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ; NGID1 < NGID2 NGID3 cpu0/regs/SLICE_317 SLICE R18C22B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(C*~B)+(A*B)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 ] REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ) NGID1 NGID2 cpu0/regs/path_right_data_7[14]/SLICE_494 SLICE R17C21A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A+D*(A+B)) K0::H0=(~A*B+A*(B+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 ? NGID2 NGID3 cpu0/regs/SLICE_318 SLICE R18C23B )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(C*~D)+(A*D)+(A*C) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 _ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 NGID2 cpu0/regs/path_right_data_6[14]/SLICE_495 SLICE R17C21B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A+D*(A+B)) K0::H0=(~D*A+D*(A+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 = NGID1 : NGID2 NGID3 cpu0/regs/SLICE_319 SLICE R17C20A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(B*C)+(B*A) K0::H0=(B*~C)+(D*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 a REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 / NGID1 NGID2 cpu0/regs/path_right_data_7[10]/SLICE_496 SLICE R15C21C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*B)+C*(~D*(A*B)+D*B)) K0::H0=(C*(D*(~B*A))) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \ NGID1 NGID2 NGID3 cpu0/regs/SLICE_320 SLICE R17C22B )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(C*~B)+(A*B)+(A*C) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 c REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 2 NGID1 NGID2 cpu0/regs/path_right_data_7[11]/SLICE_497 SLICE R15C18C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*(C*(~A*B))) K0::H0=(~A*~C+A*(~D*~C+D*(~C*~B))) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Z NGID2 NGID3 cpu0/regs/SLICE_321 SLICE R17C24A )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~D)+(C*D)+(C*B) K0::H0=(D*~B)+(C*B)+(C*D) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 e REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 5 NGID1 NGID2 cpu0/regs/path_right_data_6[11]/SLICE_498 SLICE R15C18D )
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! " # $ % & ' ( MODE:LOGIC K0::H0=(A*(~B*~D)) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 A NGID1 NGID2 cpu0/regs/SLICE_322 SLICE R14C20C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(A*B)+(A*D) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 g REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 8 NGID1 NGID2 cpu0/regs/path_right_data_7[9]/SLICE_499 SLICE R17C19C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C*B)+D*(~A*(~C*B)+A*B)) K0::H0=(~A*~C+A*(~C*(~B+~D))) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/regs/SLICE_323 SLICE R16C22A )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(D*~C)+(B*C)+(B*D) K0::H0=(C*~B)+(D*B)+(D*C) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 i REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ; NGID1 NGID2 cpu0/regs/path_right_data_6[9]/SLICE_500 SLICE R17C19D )
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! " # $ % & ' ( MODE:LOGIC K0::H0=(D*(~C*A)) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @ NGID1 NGID2 cpu0/regs/SLICE_324 SLICE R18C21B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(B*~A)+(D*A)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 k REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 NGID2 cpu0/regs/path_right_data_6[10]/SLICE_501 SLICE R15C21D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~A*(C*~D)+A*~D)+B*~D) K0::H0=(B*(~D*(C*A))) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 r NGID3 vcpu0/regs/SLICE_325 SLICE R21C25D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(C*~D)+(B*D)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 m REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 A NGID1 NGID2 cpu0/regs/path_right_data_7[13]/SLICE_502 SLICE R15C19A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*(~D*B)+A*(B+D))+C*B) K0::H0=((C+~(~B+~A))*D)+(((~B+~A)*C)*~D) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 l NGID1 NGID2
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(C*~A)+(B*A)+(B*C) K0::H0=(A*~D)+(B*D)+(B*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 o REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 D NGID1 NGID2 !cpu0/regs/path_right_data_6[13]/SLICE_503 SLICE R15C19B )
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NGID3 O NGID4 ^cpu0/regs/ea/SLICE_326 SLICE R23C25A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(B*C)+(B*D) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 G NGID1 # NGID2 $cpu0/regs/path_right_data_7[12]/SLICE_504 SLICE R17C17A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=((D+~(~B+~A))*C)+(((~B+~A)*D)*~C) K0::H0=((C+~(~B+~A))*D)+(((~B+~A)*C)*~D) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 NGID2 i NGID3 NGID4 L NGID5 Kcpu0/regs/SLICE_327 SLICE R18C18B )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(A*~D)+(C*D)+(C*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 s REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 J NGID1 & NGID2 'cpu0/regs/path_right_data_6[12]/SLICE_505 SLICE R17C17B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*(~D*B)+A*(B+D))+C*B) K0::H0=(~B*(C*D)+B*(~C+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 j NGID1 G NGID2 u NGID3 Pcpu0/regs/ea/SLICE_328 SLICE R21C29A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(D*C)+(D*A) K0::H0=(A*~B)+(D*B)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 u REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 M NGID1 ) NGID2 *cpu0/regs/path_right_data_7[5]/SLICE_506 SLICE R16C15D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B+A*(~D*B+D*C)) K0::H0=(~C*(~B*(~A*D)+B*(D+A))+C*D) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 H NGID1 ' NGID2 Ncpu0/regs/SLICE_329 SLICE R18C18C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 w REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 P NGID1 , NGID2 -cpu0/regs/path_right_data_6[0]/SLICE_507 SLICE R18C17B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*(D*~B)) K0::H0=(~C*(~A*(~B*D)+A*(D+B))+C*D) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 E NGID1 NGID2 Qcpu0/regs/ea/SLICE_330 SLICE R23C22D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(B*~C)+(D*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 y REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 S NGID1 / NGID2 0cpu0/regs/path_right_data_7[0]/SLICE_508 SLICE R18C17A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*~D)+C*(D+A)) K0::H0=((B+~(~D+~A))*C)+(((~D+~A)*B)*~C) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 m NGID1 NGID2 NGID3 Rcpu0/SLICE_331 SLICE R21C29C )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(C*~D)+(B*D)+(B*C) K0::H0=(A*~C)+(D*C)+(D*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 { REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 V NGID1 2 NGID2 3cpu0/regs/path_right_data_6[4]/SLICE_509 SLICE R15C14B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*D) K0::H0=(~B*(~C*(~A*D)+C*(D+A))+B*D) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 D NGID1 NGID2 Mcpu0/SLICE_332 SLICE R11C28B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(A*B)+(A*D) K0::H0=(D*~C)+(B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 } REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Y NGID1 5 NGID2 6cpu0/regs/path_right_data_7[4]/SLICE_510 SLICE R15C14A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C*(B*A))+D*(~C*(~B+A))) K0::H0=(~B*D+B*C) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_333 SLICE R11C26D )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~D)+(C*D)+(C*B) K0::H0=(A*~B)+(C*B)+(C*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \ NGID1 8 NGID2 9cpu0/regs/path_right_data_6[3]/SLICE_511 SLICE R16C17D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*B)+(C*~B)+(C*D) K0::H0=(C*A*~D)+(B*C*A)+(B*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 q NGID3 cpu0/SLICE_334 SLICE R14C15D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(C*~D)+(A*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _ NGID1 ; NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D+(~B+~A))) K0::H0=(~B*(~C*A)+B*(A+C)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 8 NGID2 cpu0/regs/SLICE_335 SLICE R18C19C )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(D*~A)+(C*A)+(C*D) K0::H0=(D*~C)+(B*C)+(B*D) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 b NGID1 > NGID2 ?cpu0/regs/path_right_data_6[2]/SLICE_513 SLICE R16C16A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~C*(D*~B)+C*~B)+A*~B) K0::H0=(~D+((~B+~C)+A)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 NGID2 cpu0/regs/SLICE_336 SLICE R17C19D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(D*C)+(D*A) K0::H0=(B*~D)+(C*D)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 A NGID2 Bcpu0/regs/path_right_data_7[2]/SLICE_514 SLICE R15C16D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*~C) K0::H0=(C*(D*(~B*A))) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [ NGID1 NGID2 % NGID3 &cpu0/SLICE_337 SLICE R18C24D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(D*A)+(D*B) K0::H0=(D*~A)+(C*A)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 h NGID1 D NGID2 Ecpu0/regs/path_right_data_6[1]/SLICE_515 SLICE R18C16A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*~C) K0::H0=(A@~C) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 x NGID3 cpu0/SLICE_346 SLICE R10C21C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(B*~C)+(D*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 G NGID2 Hcpu0/regs/path_right_data_7[1]/SLICE_516 SLICE R17C14D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*D+A*B) K0::H0=(~A*(C*(~D*B))+A*((~D+~B)+C)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(B*A)+(B*C) K0::H0=(C*~D)+(B*D)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 n NGID1 J NGID2 Kcpu0/regs/path_right_data_6[7]/SLICE_517 SLICE R17C16A )
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NGID1 NGID2 cpu0/SLICE_347 SLICE R17C18B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(B*~C)+(D*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 q NGID1 M NGID2 Ncpu0/regs/path_right_data_7[7]/SLICE_518 SLICE R17C16C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*C+B*(~D*(C*A)+D*(~A+C))) K0::H0=(D*(~B*(A*C)+B*(C+A))) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 7 NGID1 NGID2 q NGID3 scpu0/regs/SLICE_348 SLICE R24C18A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(B*D)+(B*A) K0::H0=(A*~B)+(C*B)+(C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 t NGID1 P NGID2 Qcpu0/regs/path_right_data_6[6]/SLICE_519 SLICE R17C14C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*A*B)+(A*B*~C)+(D*~B*~C)+(D*A*~C)+(~D*~B*C)+(~D*A*C) K0::H0=(B*C)+(D*~C)+(D*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 O NGID1 NGID2 NGID3 Mcpu0/regs/SLICE_349 SLICE R24C23D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(B*C)+(B*A) K0::H0=(D*~B)+(C*B)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 w NGID1 S NGID2 Tcpu0/regs/path_right_data_7[6]/SLICE_520 SLICE R17C14B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*D)+(B*~D)+(B*C) K0::H0=(C*D)+(B*~D)+(B*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ^ NGID2 _ NGID3 Pcpu0/SLICE_350 SLICE R23C22A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(B*~D)+(A*D)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 V NGID2 Wcpu0/regs/path_right_data_6[5]/SLICE_521 SLICE R16C16B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*D)+(C*~D)+(C*A) K0::H0=(C*B)+(D*~B)+(D*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~D)+(C*D)+(C*B) K0::H0=(B*~C)+(A*C)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 n NGID2 ocpu0/alu/alu16/a16/overflow_out/SLICE_522 SLICE R8C17A )
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Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 Tcpu0/regs/SLICE_351 SLICE R24C23A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D*C)+(~B*~A*D) K0::H0=(A*D*~B)+(~A*~D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[14]/SLICE_523 SLICE R7C19B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*C)+(A*~C)+(A*D) K0::H0=(D*C)+(A*~C)+(A*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0
Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 R NGID1 NGID2 NGID3 Wcpu0/SLICE_352 SLICE R24C22D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(B*C)+(~B*A) K0::H0=C*D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[13]/SLICE_524 SLICE R9C15B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*C)+(A*~C)+(A*D) K0::H0=(A*C)+(B*~C)+(B*A) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
NGID2 NGID3 Zcpu0/regs/SLICE_353 SLICE R24C22B )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(C*B)+(~C*A) K0::H0=A*D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[12]/SLICE_525 SLICE R6C19D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*C)+(D*~C)+(D*A) K0::H0=(C*A)+(D*~A)+(D*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 a NGID2 b NGID3 ]cpu0/SLICE_354 SLICE R24C23C )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(B*C)+(~B*A) K0::H0=C*D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[11]/SLICE_526 SLICE R6C19B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*A)+(C*~A)+(C*D) K0::H0=(C*D)+(A*~D)+(A*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 NGID2 NGID3 acpu0/regs/SLICE_355 SLICE R23C22C )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(B*A)+(~B*D) K0::H0=D*B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[10]/SLICE_527 SLICE R8C18D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*B)+(A*~B)+(A*D) K0::H0=(D*B)+(A*~B)+(A*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 U NGID1 NGID2 NGID3 dcpu0/regs/SLICE_357 SLICE R14C25B )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(C*A)+(~C*B) K0::H0=D*B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[9]/SLICE_528 SLICE R6C16D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*(~A*D))+B*((D+A)+C)) K0::H0=(~C*(~B*(~A*D))+C*((D+A)+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 x NGID1 y NGID2 y NGID3 |cpu0/regs/SLICE_358 SLICE R14C27C )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(B*D)+(~B*C) K0::H0=C*B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[8]/SLICE_529 SLICE R6C16B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*(~B*D))+C*((D+B)+A)) K0::H0=(~D*(~A*(~B*C))+D*((C+B)+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 ! REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 { NGID2 NGID3 cpu0/regs/SLICE_359 SLICE R12C23A )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(B*D)+(~B*C) K0::H0=A*D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[15]/SLICE_530 SLICE R6C19C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~B*(~A*C))+D*((C+A)+B)) K0::H0=(~C*(~B*(~A*D))+C*((D+A)+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 # K0 " REG1 % REG0 $ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 } NGID2 NGID3 cpu0/regs/SLICE_360 SLICE R12C26B )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(B*D)+(~B*C) K0::H0=D*A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[7]/SLICE_531 SLICE R8C17C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~B*(~C*D))+A*((D+C)+B)) K0::H0=(~C*(~B*(~A*D))+C*((D+A)+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 ' K0 & REG1 ) REG0 ( Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ~ NGID1 NGID2 NGID3 cpu0/regs/SLICE_361 SLICE R12C25C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~A*D)+(A*C) K0::H0=(C*~D*A)+(B*C*A)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[0]/SLICE_532 SLICE R9C17D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*(~B*D))+C*((D+B)+A)) K0::H0=(~A*(~B*(~C*D))+A*((D+C)+B)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 + K0 * REG1 - REG0 , Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/regs/SLICE_362 SLICE R12C24A )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*A)+(D*C) K0::H0=(C*~D*A)+(B*C*A)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[1]/SLICE_533 SLICE R8C19A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*(~B*D))+C*((D+B)+A)) K0::H0=(~D*(~C*(~B*A))+D*((A+B)+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 / K0 . REG1 1 REG0 0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/regs/SLICE_363 SLICE R12C22D )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~C*A)+(C*D) K0::H0=(A*~D*C)+(B*A*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[2]/SLICE_534 SLICE R7C18B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~A*(~B*C))+D*((C+B)+A)) K0::H0=(~A*(~C*(~B*D))+A*((D+B)+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 3 K0 2 REG1 5 REG0 4 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/regs/SLICE_364 SLICE R11C25B )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*C)+(D*B) K0::H0=(B*~A*D)+(C*B*D)+(C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[3]/SLICE_535 SLICE R8C16C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*(~B*D))+C*((D+B)+A)) K0::H0=(~B*(~A*(~D*C))+B*((C+D)+A)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 7 K0 6 REG1 9 REG0 8 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 ~ NGID3 cpu0/regs/SLICE_430 SLICE R19C22C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~C*D)+(C*B) K0::H0=(A*~B*D)+(C*A*D)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[4]/SLICE_536 SLICE R7C18A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~A*(~B*~D))) K0::H0=((B*(~A*~D))+C) REG1::::SD=0 REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 REGMODE:FF 4 MODE K1 ; K0 : REG1 = REG0 < Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_431 SLICE R12C20C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~C*D)+(C*B) K0::H0=(B*~C*D)+(A*B*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[5]/SLICE_537 SLICE R9C15A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~B*~D)) K0::H0=(B*((~C+D)+A)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 ? K0 > REG1 REG0 @ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 m NGID1 + NGID2 (cpu0/SLICE_432 SLICE R15C27A )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~C*D)+(C*A) K0::H0=(D*~C*A)+(B*D*A)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[6]/SLICE_538 SLICE R8C16A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*C)+(D*A) K0::H0=(C*A)+(~C*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 B REG1 REG0 C Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_433 SLICE R14C26D )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~C*D)+(C*B) K0::H0=(C*~B*A)+(D*C*A)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/datamux_o_dest[4]/SLICE_539 SLICE R14C18D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*C)+(A*B) K0::H0=(B*D)+(~B*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 E REG1 REG0 F Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_434 SLICE R14C27A )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*C)+(D*A) K0::H0=(~B*D*C)+(D*A)+(~C*A)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/datamux_o_dest[5]/SLICE_540 SLICE R9C22B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B)+(A*D) K0::H0=(D*B)+(~D*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 H REG1 REG0 I Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_435 SLICE R15C27D )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~B*D)+(B*C) K0::H0=(~A*C*D)+(C*B)+(~D*B)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 9 NGID2 cpu0/alu/alu16/datamux_o_dest[6]/SLICE_541 SLICE R12C22C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*C)+(D*A) K0::H0=(C*A)+(~C*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 K REG1 REG0 L Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_436 SLICE R14C26C )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*A)+(D*C) K0::H0=(~B*A*D)+(A*C)+(~D*C)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/l8/datamux_o_dest[7]/SLICE_542 SLICE R14C18A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*C)+(B*A) K0::H0=(A*B)+(~A*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 N REG1 REG0 O Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_437 SLICE R14C26B )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*C)+(D*A) K0::H0=(~A*B*D)+(B*C)+(~D*C)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 j NGID1 : NGID2 cpu0/alu/alu8/l8/datamux_o_dest[0]/SLICE_543 SLICE R11C23C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*A)+(C*D) K0::H0=(B*C)+(~B*D) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 Q REG1 REG0 R Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_438 SLICE R15C27B )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*B)+(D*C) K0::H0=(~B*C*D)+(C*A)+(~D*A)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 b NGID2 cpu0/alu/alu8/l8/datamux_o_dest[1]/SLICE_544 SLICE R8C20A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*C)+(D*A) K0::H0=(A*C)+(~A*B) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 T REG1 REG0 U Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_439 SLICE R14C27D )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*C)+(D*B) K0::H0=(~B*C*D)+(C*A)+(~D*A)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 l NGID1 a NGID2 cpu0/alu/alu8/v8_0/SLICE_545 SLICE R8C14D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*C)+(B*A) K0::H0=(D*A)+(~D*C) REG0:#ON Q0:Q GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC OFX0:F LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 W REG1 REG0 X Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
E NGID1 NGID2 NGID3 cpu0/SLICE_440 SLICE R21C12A )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=~B*~A*C*D K0::H0=(C*B*~D)+(C*~B*D)+(~C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 NGID2 cpu0/alu/alu8/CCRo[2]/SLICE_546 SLICE R9C17A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*(B*(A*D))) K0::H0=(~A*(C+B)+A*((D+C)+B)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 Z K0 Y REG1 REG0 [ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_441 SLICE R19C16C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=~B*~A*C*D K0::H0=(B*~A)+(C*~A)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 lcpu0/alu/alu8/CCRo[3]/SLICE_547 SLICE R14C17B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*(C*(B*A))) K0::H0=(~B*(A+D)+B*((A+D)+C)) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 ] K0 \ REG1 REG0 ^ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 NGID2 SLICE_442 SLICE R24C17B )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(B*A)+(~B*C) K0::H0=(D*~A)+(B*~A)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/CCRo[1]/SLICE_548 SLICE R7C17C )
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! " # $ % & ' ( oMODE:LOGIC K0::H0=(A@~B) REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 _ REG1 REG0 ` Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 SLICE_443 SLICE R24C17D kMODE:LOGIC K0::H0=~A REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 a REG1 REG0 b Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 'SLICE_444 SLICE R19C8D )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(D*A)+(~D*C) K0::H0=(B*~A)+(C*~A)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/q_out_5[7]/SLICE_549 SLICE R12C14A )
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! " # $ % & ' ( MODE:LOGIC K0::H0=(~A+(~D+~B)) REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 LSRMUX:LSR SRMODE:LSR_OVER_CE LSRONMUX:LSRMUX REGMODE:FF 4 MODE K1 K0 c REG1 REG0 d Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 SLICE_445 SLICE R19C8C )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(D*C*~A)+(B*C*~A)+(~B*~D*A)+(~C*A) K0::H0=~D*C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/q_out_5[5]/SLICE_550 SLICE R9C21B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A@(B*D)) K0::H0=(A@D) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 f K0 e REG1 h REG0 g Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(B*D*~A)+(~D*A)+(~B*A) K0::H0=~D*~A*B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/CCRo[0]/SLICE_551 SLICE R7C20B )
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NGID1
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*~C*D)+(C*A)+(B*A) K0::H0=(B*~D)+(A*~D)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/q_out_5[6]/SLICE_552 SLICE R12C14D )
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NGID2 $ NGID3 %SLICE_446 SLICE R19C8A )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~A*D*~C)+(~D*C)+(A*C) K0::H0=~D*~C*A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/q_out_5[1]/SLICE_553 SLICE R8C15B )
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! " # $ % & ' ( MODE:LOGIC K0::H0=(~B*A+B*(~C*A+C*(D@A))) REG0:#ON Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 i REG1 REG0 j Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(B*C*~A)+(~C*A)+(~B*A) K0::H0=~D*~A*B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/q_out_5[2]/SLICE_554 SLICE R7C17B )
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' NGID1 &cpu0/SLICE_447 SLICE R17C13C )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~A*D*~C)+(~D*C)+(A*C) K0::H0=~D*~C*B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/q_out_5[3]/SLICE_555 SLICE R12C16B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*((D+C)+A)+B*C) K0::H0=(~B*D+B*((~A*~C)+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:ENABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 l K0 k REG1 n REG0 m Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 j NGID1 S NGID2 NGID3 cpu0/SLICE_448 SLICE R17C13D )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(C*A*~D)+(B*A*~D)+(~B*~C*D)+(~A*D) K0::H0=~B*C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ! NGID2 "cpu0/alu/alu8/q_out_4[1]/SLICE_556 SLICE R8C15A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D*A+D*(~B+A))+C*A) K0::H0=(~B*(D+C)+B*((A+D)+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:ENABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 p K0 o REG1 r REG0 q Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_449 SLICE R18C12A )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(B*A)+(C*A)+(C*~B) K0::H0=(~D*C)+(D*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ) NGID2 *cpu0/alu/alu8/q_out_4[2]/SLICE_557 SLICE R7C17A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C*(~A*~B))+D*~B) K0::H0=(~A*(~B*~D)+A*(~B*(C*~D))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:ENABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 t K0 s REG1 v REG0 u Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 X NGID1 ' NGID2 NGID3 textctrl/SLICE_450 SLICE R23C9B )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(A*B)+(C*B)+(C*~A) K0::H0=(~B*C)+(B*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 , NGID2 -cpu0/alu/alu8/q_out_4[3]/SLICE_558 SLICE R12C16A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~C+~D)) K0::H0=(~B*(~C*(~A*~D))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 LSRMUX:LSR SRMODE:LSR_OVER_CE LSRONMUX:LSRMUX REGMODE:FF 4 MODE K1 x K0 w REG1 REG0 y Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(C*B)+(A*B)+(A*~C) K0::H0=(~A*D)+(A*C) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 / NGID2 0cpu0/alu/alu8/q_out_4[5]/SLICE_559 SLICE R9C21A )
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NGID1
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(B*C)+(A*C)+(A*~B) K0::H0=(~B*D)+(B*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 3 NGID2 4cpu0/alu/alu8/q_out_4[6]/SLICE_560 SLICE R12C14C )
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NGID2
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(A*B)+(D*B)+(D*~A) K0::H0=(~A*D)+(A*C) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 6 NGID2 7cpu0/alu/alu8/q_out_4[7]/SLICE_561 SLICE R14C16A )
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xSLICE_454 SLICE R14C17C MODE:LOGIC K0::H0=0 REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 z REG1 | REG0 { Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(D*C)+(A*C)+(A*~D) K0::H0=(~A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ; NGID2
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v NGID2
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~B*A*C)+(D*C)+(D*~A)+(D*B) K0::H0=(A*~C)+(B*~C)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 > NGID2 ?cpu0/alu/alu8/q_out_1[0]/SLICE_563 SLICE R7C22B )
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wSLICE_455 SLICE R14C18A )
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! " # $ % & ' ( aMODE:LOGIC K1::H1=(B*~D*A)+(~B*D*A)+(B*D*~A)+(B*A*~C)+(D*~C) K0::H0=(~C*B)+(C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 C NGID2 Dcpu0/alu/alu8/q_out_1[4]/SLICE_564 SLICE R7C16B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C*~A)) K0::H0=(D*~B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 ~ K0 } REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( aMODE:LOGIC K1::H1=(B*~A*D)+(~B*A*D)+(B*A*~D)+(B*D*~C)+(A*~C) K0::H0=(C*D)+(~C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 F NGID2 Gcpu0/alu/alu8/c8_1/SLICE_565 SLICE R6C21C )
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h NGID3
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(D*A)+(D*C) K0::H0=(~A*D)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 O NGID2 Pcpu0/alu/alu8/q_out[0]/SLICE_566 SLICE R7C23B )
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iSLICE_456 SLICE R14C28D )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~B*D)+(B*C) K0::H0=(~D*~A*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 L NGID2 (cpu0/alu/alu8/q_out[4]/SLICE_567 SLICE R8C16D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~A*~D)) K0::H0=(B*D) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 y NGID2
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~D*C)+(D*B) K0::H0=(~D*~C*B)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 M NGID2 2cpu0/alu/alu8/datamux_o_dest[2]/SLICE_568 SLICE R7C19C )
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j NGID3
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*C)+(D*B) K0::H0=(~B*C*D)+(C*A)+(~D*A)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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kSLICE_457 SLICE R16C28B )
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NGID1 n NGID2 cpu0/alu/alu8/datamux_o_dest[3]/SLICE_569 SLICE R11C20B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=~D K0::H0=(~D*B+D*C) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ] NGID1 NGID2
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~C*A)+(C*D) K0::H0=(~C*A*D)+(A*B)+(~D*B)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 8 NGID2 cpu0/dec_regs/SLICE_570 SLICE R17C36A )
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l NGID3
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~C*(D+A)+C*D)+B*D) K0::H0=(~D*(C*(A*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_571 SLICE R12C25C )
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mSLICE_458 SLICE R18C19B )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~A*(~B*(D*C))) K0::H0=(~B*((A*D)+C)+B*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_572 SLICE R12C24D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~D*(C*~B)+D*(B+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 I NGID1 O NGID2
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~C*(~B*(A*D))) K0::H0=(~B*((A*D)+C)+B*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_573 SLICE R8C31D )
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n NGID3
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! " # $ % & ' ( IMODE:LOGIC K1::H1=C+((~B*A)*D) K0::H0=(~D*(~A*B+A*(~C+B))+D*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_regs/SLICE_574 SLICE R7C26C )
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otextctrl/SLICE_459 SLICE R21C9C )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(~A*(~D+(C*~B))+A*(C*~B)) K0::H0=(~A*(~B*C)+A*(B@D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_575 SLICE R18C25C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*B)+A*(~D*B)) K0::H0=(~A*B) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=((D+A+C)*B)+((D+C)*~B) K0::H0=(~C*(~B*(~A*D)+B*D)+C*D) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 h NGID3 * NGID4 +cpu0/regs/SLICE_576 SLICE R19C24B )
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NGID1
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! " # $ % & ' ( EMODE:LOGIC K1::H1=((A*(~B*~C))+D) K0::H0=(~B*(~A*(~D*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 1cpu0/alu/alu8/SLICE_577 SLICE R8C14C )
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NGID2
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! " # $ % & ' ( SMODE:LOGIC K1::H1=((B+~(C*D))*A)+((B*C*D)*~A) K0::H0=(~C*D+C*(~B*A+B*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 T NGID2 ctextctrl/SLICE_578 SLICE R23C30D )
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Y NGID3
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~A*(~C*(D*~B))) K0::H0=(~A*B+A*(~C*B+C*(B+D))) F1:F F0:F 4 MODE K1 K0
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Ztextctrl/SLICE_460 SLICE R21C9B )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*(~D*C))+A*(~B*C+B*(D*C))) K0::H0=(~B*(C*A)+B*(~D*(C*A)+D*(C*~A))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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NGID1
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* NGID1
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textctrl/SLICE_579 SLICE R23C31A )
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NGID2
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*(B*(~A*~C))) K0::H0=(~D*~A+D*(~B*~A+B*(~C*~A))) F1:F F0:F 4 MODE K1
K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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[ NGID3
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o NGID1
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\textctrl/SLICE_461 SLICE R23C11A )
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textctrl/SLICE_580 SLICE R24C30B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(D*~C)+B*(C+D)) K0::H0=(A*(C*(B*D))) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(B*(D*(A+C))) K0::H0=(~A*(B*C)+A*(B*(C+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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& NGID1
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t NGID1
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NGID2
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textctrl/SLICE_581 SLICE R23C31C )
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Q NGID3
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(B*(C*(D*A))) K0::H0=(~B*~D+B*(~C*(~A*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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Rtextctrl/SLICE_462 SLICE R23C12B )
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~ NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*~D)+C*(D+B)) K0::H0=(~D*(C*~A)+D*(A+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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cpu0/test_cond/SLICE_582 SLICE R15C30B )
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NGID1
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! " # $ % & ' ( \MODE:LOGIC K1::H1=(~C*(~A*B)+C*(B+A)) K0::H0=(~D*(~C*~B+C*(~A*~B))+D*(C*(~A*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_583 SLICE R11C27C )
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NGID2
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*(~B+~A)+D*(~C*~A+C*(~B+~A))) K0::H0=(A*(B*(C*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_584 SLICE R11C27D )
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S NGID3
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! " # $ % & ' ( [MODE:LOGIC K1::H1=(~D*~A+D*(~C*(~A*~B)+C*~A)) K0::H0=(~B*(D*C)+B*(~A*(D*C)+A*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_585 SLICE R11C27A )
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Ttextctrl/SLICE_463 SLICE R23C11B )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~B+(~A*(~D*~C))) K0::H0=(~A*(B*~C)+A*(B*(~C+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_586 SLICE R11C29C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*~B)+C*(B+A)) K0::H0=(~B*(D*~C)+B*(C+D)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(~D+(~B*(~A*~C))) K0::H0=(~D*(A*B)+D*(~C*(A*B)+C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_587 SLICE R9C27A )
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NGID1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(~A*B+A*D)) K0::H0=(~A*(~D*B+D*C)+A*(D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_588 SLICE R14C24B )
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NGID2
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! " # $ % & ' ( =MODE:LOGIC K1::H1=((C+D)+B) K0::H0=(~A+((~B+D)+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 lcpu0/SLICE_589 SLICE R16C36A )
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U NGID3
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*(~C*(A+D)+C*A)+B*A) K0::H0=(C*(~D*~B)) F1:F F0:F 4 MODE K1 ! K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_590 SLICE R16C35A )
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Vtextctrl/SLICE_464 SLICE R23C11C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=((~A*~C)*~B)*~D K0::H0=(~A*(D+B)+A*(~C+(D+B))) F1:F F0:F 4 MODE K1 # K0 " REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 ~cpu0/SLICE_591 SLICE R18C31D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(A*~C)+B*(C+A)) K0::H0=(~A*(C*~D)+A*(D+C)) REG1:#ON REG0:#ON Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(A*(~C*(D*~B))) K0::H0=(~C*B+C*(~D*B+D*(B+A))) F1:F F0:F 4 MODE K1 % K0 $ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ^cpu0/SLICE_592 SLICE R14C23C )
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NGID1
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! " # $ % & ' ( iMODE:LOGIC K1::H1=(~A*((~D+C)+B)+A*(~B*C+B*(C+D))) K0::H0=(~A*(~B*~C+B*(~D*~C))+A*(~B*(D*~C))) F1:F F0:F 4 MODE K1 ' K0 & REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 # NGID1 cpu0/SLICE_593 SLICE R12C24B )
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NGID2
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(~C*~B+C*(~D*~A+D*(B@A))) K0::H0=(~C*(D+A)+C*((B+D)+A)) F1:F F0:F 4 MODE K1 ) K0 ( REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 cpu0/SLICE_594 SLICE R15C31B )
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W NGID3
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(~A*D+A*(~B*D+B*(D*~C))) K0::H0=(~B*(D*~A)+B*(D*(~A*C))) F1:F F0:F 4 MODE K1 + K0 * REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 cpu0/SLICE_595 SLICE R15C29A )
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XSLICE_465 SLICE R17C17C )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~D*(A*(B*C))+D*(~A*(~B*C)+A*C)) K0::H0=(~D*~C+D*A) F1:F F0:F 4 MODE K1 - K0 , REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ; NGID1 cpu0/dec_op/SLICE_596 SLICE R22C32C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*~A)+B*(A+C)) K0::H0=(~A+(~D+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(D*(B*(~C*A))) K0::H0=(~A*D+A*((B*C)+D)) F1:F F0:F 4 MODE K1 / K0 . REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 = NGID1 Hcpu0/dec_op/SLICE_597 SLICE R21C32B )
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I NGID3
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(A*(~B*(C*~D))) K0::H0=(~A*B+A*(~C*(D+B)+C*B)) F1:F F0:F 4 MODE K1 1 K0 0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 M NGID1 Qcpu0/dec_op/SLICE_598 SLICE R14C27D )
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JSLICE_466 SLICE R17C14A )
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(~A*(~D*(B+C)+D*~C)) K0::H0=(~D*(~A*(B+C)+A*C)+D*(~A+C)) F1:F F0:F 4 MODE K1 3 K0 2 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ^ NGID1 lcpu0/dec_op/SLICE_599 SLICE R16C31C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*A+C*B) K0::H0=(B*(D*(C*A))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~B*(~A*(C*D)+A*(~D+C))+B*(~D+C)) K0::H0=(~B*(D+A)+B*(~A*D)) F1:F F0:F 4 MODE K1 5 K0 4 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 h NGID1 cpu0/SLICE_600 SLICE R18C36C )
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K NGID3
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~C*(~B*~A)) K0::H0=(~B*((D*A)+C)+B*C) F1:F F0:F 4 MODE K1 7 K0 6 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 i NGID1 cpu0/dec_op/SLICE_601 SLICE R12C30A )
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Ltextctrl/SLICE_467 SLICE R21C10B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(C*(~B*D))) K0::H0=(~B*(A+D)+B*(~C+(A+D))) F1:F F0:F 4 MODE K1 9 K0 8 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 o NGID1 cpu0/dec_op/SLICE_602 SLICE R14C32D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D@C) K0::H0=(~A+~D) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(C*(~B*(A*~D))) K0::H0=(~B*C+B*(~A*(C+D)+A*C)) F1:F F0:F 4 MODE K1 ; K0 : REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 x NGID1 cpu0/dec_op/SLICE_603 SLICE R14C33D )
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NGID1
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~C*(~A*(B*D)+A*D)) K0::H0=(~C*(~D*A+D*(~B+A))+C*A) F1:F F0:F 4 MODE K1 = K0 < REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 y NGID1 cpu0/dec_op/SLICE_604 SLICE R15C27A )
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NGID2
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(A*(~D*(~C+B))) K0::H0=(~C*B+C*(~A*(D+B)+A*B)) F1:F F0:F 4 MODE K1 ? K0 > REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ~ NGID1 cpu0/SLICE_605 SLICE R12C28B )
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M NGID3
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! " # $ % & ' ( EMODE:LOGIC K1::H1=((~C*D+C*(D+A))+B) K0::H0=(D*(~B*(C*A))) F1:F F0:F 4 MODE K1 A K0 @ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 scpu0/dec_op/SLICE_606 SLICE R15C27C )
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Ntextctrl/SLICE_468 SLICE R22C11A )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*C+D*(~C*(A*~B)+C*A)) K0::H0=(~D*(A*~C)+D*(~C*~B)) F1:F F0:F 4 MODE K1 C K0 B REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_607 SLICE R18C34D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*C) K0::H0=(~D*(~B*(~C*A))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(~D*(B*C)+D*(B*(A+C))) K0::H0=(~A*(~C*~D)+A*(~C*(~D*B))) F1:F F0:F 4 MODE K1 E K0 D REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_608 SLICE R7C29D )
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NGID1
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~D*C+D*(~B*(C+A)+B*C)) K0::H0=(~C*(~B*A+B*(D*A))+C*(~B*(~D*A))) F1:F F0:F 4 MODE K1 G K0 F REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_609 SLICE R8C28C )
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NGID2
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~B*C+B*(~A*C+A*(D+C))) K0::H0=(B*(D*(~C*A))) F1:F F0:F 4 MODE K1 I K0 H REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_610 SLICE R19C33B )
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O NGID3
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~D*(~A*B+A*(B+C))+D*B) K0::H0=(C*(D*(~B*A))) F1:F F0:F 4 MODE K1 K K0 J REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_611 SLICE R14C16D )
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Ptextctrl/SLICE_469 SLICE R23C9A )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~A*(C*(D*B))+A*(D*B)) K0::H0=(~C*(~D*~A)+C*(~D+A)) F1:F F0:F 4 MODE K1 M K0 L REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [ NGID1 acpu0/dec_regs/SLICE_612 SLICE R9C29A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(((~B+A)+D)+C) K0::H0=(~C*(~B*(~A*~D))) REG0:#ON Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 LSRMUX:LSR SRMODE:LSR_OVER_CE LSRONMUX:LSRMUX REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(D*(~A*(~C*~B))) K0::H0=(~C*(~A*~B+A*(~B*~D))) F1:F F0:F 4 MODE K1 O K0 N REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 t NGID1 cpu0/dec_regs/SLICE_613 SLICE R12C29D )
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NGID1
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! " # $ % & ' ( ZMODE:LOGIC K1::H1=(~D*(~C*~B)+D*(~C+(~B+A))) K0::H0=(~C*((D+B)+A)+C*(~A+(D+B))) F1:F F0:F 4 MODE K1 Q K0 P REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 u NGID1 cpu0/dec_regs/SLICE_614 SLICE R14C34B )
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NGID2
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*A+B*(~D*A+D*(A+C))) K0::H0=(~B*C+B*(~D*(A+C)+D*C)) F1:F F0:F 4 MODE K1 S K0 R REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 { NGID1 cpu0/dec_regs/SLICE_615 SLICE R18C35A )
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Hcpu0/test_cond/cond_taken4/SLICE_470 SLICE R9C20D )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(D*~A)*B*~C K0::H0=(~A*(C+B)+A*((C+B)+D)) F1:F F0:F 4 MODE K1 U K0 T REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_616 SLICE R15C35B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=~A*C*D K0::H0=~A*B*D*C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
P NGID1 NGID2 cpu0/test_cond/cond_taken_15_0/SLICE_471 SLICE R9C21A )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~A*(~D*B)) K0::H0=(~A*(B*D)+A*(~C*(B*D)+C*(~B+D))) F1:F F0:F 4 MODE K1 W K0 V REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_617 SLICE R10C28B )
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! " # $ % & ' ( vMODE:LOGIC K1::H1=(~B*~D*~A)+(~D*~C*~A)+(B*C*A)+(D*A) K0::H0=(B*~D*~C)+(B*D*C)+(~B*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 NGID2 cpu0/test_cond/cond_taken_8/SLICE_472 SLICE R9C21B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~B*(D+C)+B*(~C+D)) K0::H0=(~C*D+C*(~A*D+A*(B+D))) F1:F F0:F 4 MODE K1 Y K0 X REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_618 SLICE R7C28D )
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! " # $ % & ' ( gMODE:LOGIC K1::H1=(~B*~C*~D)+(~A*C*~D)+(B*~C*D)+(A*C*D) K0::H0=(B*D*C)+(~D*~C)+(~B*~D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 NGID2 cpu0/dec_alu/alu_opcode_2_4_0_.m54/SLICE_473 SLICE R9C19C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~C*A+C*(A*~D)) K0::H0=(~D*(~A+C)+D*(C+B)) F1:F F0:F 4 MODE K1 [ K0 Z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_619 SLICE R8C28B )
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! " # $ % & ' ( aMODE:LOGIC K1::H1=(~D*~A*~B)+(D*A*~B) K0::H0=(D*A*~B*~C)+(D*~A*B*~C)+(D*~A*~B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 : NGID2 [cpu0/dec_alu/alu_opcode_1_f0_0_m2_0[2]/SLICE_474 SLICE R12C14C )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(D*(~C*(B*A))) K0::H0=(~D*((~B+A)+C)+D*A) F1:F F0:F 4 MODE K1 ] K0 \ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_620 SLICE R15C35D )
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! " # $ % & ' ( ^MODE:LOGIC K1::H1=(~C*~B)+(D*B) K0::H0=(D*A*~B)+(D*~C*~B)+(~D*C*~B)+(~D*C*~A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 = NGID2 Lcpu0/dec_alu/alu_opcode_2_4_0_.m19/SLICE_475 SLICE R14C15C )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(~(D+A)*B)*C K0::H0=(~A*(~D*~C+D*(~C*~B))+A*(~D+~B)) F1:F F0:F 4 MODE K1 _ K0 ^ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_regs/SLICE_621 SLICE R10C31C )
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! " # $ % & ' ( ZMODE:LOGIC K1::H1=(~A*~C*~B)+(~A*~B*~D)+(~C*~D) K0::H0=(~D*C)+(B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 K NGID2 Bcpu0/dec_op/mode_4_0[2]/SLICE_476 SLICE R15C17D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(D*(~C*(~B+~A)+C*~A)) F1:F F0:F 4 MODE K1 a K0 ` REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_622 SLICE R10C27B )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~C*~D)+B+A K0::H0=(~A*C*~D)+B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 / NGID1 NGID2 cpu0/dec_op/un1_mode93_RNIC8563/SLICE_477 SLICE R15C20D )
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! " # $ % & ' ( VMODE:LOGIC K1::H1=(~A+(~B*(~C+~D)+B*~D)) K0::H0=(~B*((D+A)+C)+B*(~C+(D+A))) F1:F F0:F 4 MODE K1 c K0 b REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_623 SLICE R21C18B )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~B*D)+A+C K0::H0=(C*~A)+~D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 2 NGID1 NGID2 cpu0/dec_op/optype_3_2_0_.m17/SLICE_478 SLICE R14C21B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~A*(C+D)+A*C) K0::H0=(~C*(A*(~B*D))) F1:F F0:F 4 MODE K1 e K0 d REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 d NGID1 cpu0/regs/SLICE_624 SLICE R18C29C )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(B*~C)+(~D*C)+(~D*B) K0::H0=~D+A+C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 C NGID1 NGID2 cpu0/regs/ea/datamux_o_dest[5]/SLICE_479 SLICE R14C26A )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=((B*(C*A))+D) K0::H0=(~A*(~C*(B*D))) F1:F F0:F 4 MODE K1 g K0 f REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 # NGID1 cpu0/regs/SLICE_625 SLICE R16C30A )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~C*D)+(C*A) K0::H0=(~A*D*B)+(D*C)+(~B*C)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ? NGID2 Ycpu0/regs/ea/un1_eapostbyte_16_6[2]/SLICE_480 SLICE R21C21D )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~B*((D*C)+A)+B*(D+A)) K0::H0=(B*(~C*(~A*D))) F1:F F0:F 4 MODE K1 i K0 h REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_626 SLICE R19C26A )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~A*C)+(D*C)+(D*A) K0::H0=(A*~C)+(A*D)+(~A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[15]/SLICE_481 SLICE R24C20D )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(A*(B*(C*D))) K0::H0=(~C*(A*(~B*D))+C*(~A*(B*D)+A*D)) F1:F F0:F 4 MODE K1 k K0 j REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ecpu0/regs/SLICE_627 SLICE R18C26B )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*C)+(A*C)+(A*B) K0::H0=(B*A)+(~B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_i_m2[9]/SLICE_482 SLICE R24C21B )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*C+B*A) K0::H0=(~A*(~D*~C+D*(B*~C))+A*(~D*(~B*~C))) F1:F F0:F 4 MODE K1 m K0 l REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_628 SLICE R19C26D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*D)+(A*D)+(A*C) K0::H0=(D*A)+(~D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[12]/SLICE_483 SLICE R23C19D )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~C*A+C*D) K0::H0=(~D*(~B*A+B*(C*A))+D*(~B*(~C*A))) F1:F F0:F 4 MODE K1 o K0 n REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 cpu0/regs/SLICE_629 SLICE R18C23A )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*C)+(A*C)+(A*B) K0::H0=(A*D)+(~A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[15]/SLICE_484 SLICE R18C25B )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~C*A+C*D) K0::H0=(~D*(A*(~C*~B))+D*(~A*(C*~B)+A*~B)) F1:F F0:F 4 MODE K1 q K0 p REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_630 SLICE R21C33C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~A)+(C*A)+(C*D) K0::H0=(C*~A)+(D*A)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[14]/SLICE_485 SLICE R17C25B )
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! " # $ % & ' ( eMODE:LOGIC K1::H1=(~C*(~A*B+A*(B+D))+C*((~D+B)+A)) K0::H0=(~A*(~B*C+B*(C+D))+A*((~D+C)+B)) F1:F F0:F 4 MODE K1 s K0 r REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_631 SLICE R22C33D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[13]/SLICE_486 SLICE R19C23C )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~B*C+B*((~A*D)+C)) K0::H0=(C*(A*(D*B))) F1:F F0:F 4 MODE K1 u K0 t REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_632 SLICE R15C20C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~B)+(C*B)+(C*A) K0::H0=(D*~B)+(A*B)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[12]/SLICE_487 SLICE R18C23A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*D+C*B) K0::H0=(~D*(~B*(C*~A)+B*(A+C))+D*C) F1:F F0:F 4 MODE K1 w K0 v REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 g NGID1 cpu0/SLICE_633 SLICE R19C21A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(C*D)+(C*A) K0::H0=(C*~D)+(A*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[11]/SLICE_488 SLICE R17C21C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~D+~C)+B*~C) K0::H0=(~C*(D*B)+C*((D*B)+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 y K0 x REG1 { REG0 z Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 NGID2 1 NGID3 2cpu0/regs/SLICE_634 SLICE R25C35C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(A*B)+(A*D) K0::H0=(D*~B)+(A*B)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[10]/SLICE_489 SLICE R19C21A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~D*(A*~C)+D*A)) K0::H0=(~B*C+B*(A*(D*C))) F1:F F0:F 4 MODE K1 } K0 | REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_635 SLICE R15C26A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(D*~B)+(C*B)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3_i_m2[9]/SLICE_490 SLICE R17C23D )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~B*(~D+~C)+B*(~D+(~C*A))) K0::H0=(D*(C*(~B*~A))) F1:F F0:F 4 MODE K1 K0 ~ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_636 SLICE R19C33C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~D)+(A*D)+(A*C) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3[8]/SLICE_491 SLICE R19C23A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*A+B*(~D*A+D*(A+C))) K0::H0=(~D*(C*(~A*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 r NGID1 tcpu0/alu/alu16/SLICE_637 SLICE R14C19D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(C*D)+(C*A) K0::H0=(C*~D)+(B*D)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ! NGID1 NGID2 cpu0/regs/ea/ea_reg_3[7]/SLICE_492 SLICE R16C26A )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~C*A+C*D) K0::H0=(~B*(~D*~C+D*(A*~C))+B*(~D*(~A*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _ NGID1 {cpu0/alu/alu8/SLICE_638 SLICE R7C23D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(B*C)+(B*D) K0::H0=(D*~C)+(B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 $ NGID1 NGID2 cpu0/regs/ea/ea_reg_3[6]/SLICE_493 SLICE R17C25D )
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! " # $ % & ' ( cMODE:LOGIC K1::H1=((A+(B*C))*D)+((~(B*C)*A)*~D) K0::H0=(~A*(C*~B)+A*(~D*(C*~B)+D*(B+C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 S NGID2 ccpu0/alu/alu8/a8/SLICE_639 SLICE R14C17C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(B*A)+(B*C) K0::H0=(D*~A)+(B*A)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ' NGID1 NGID2 cpu0/regs/ea/ea_reg_3[5]/SLICE_494 SLICE R17C22A )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(~C*A+C*D) K0::H0=(~D*(~A*(~B*C)+A*(B*~C))+D*(~A*(B*~C)+A*(~B*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 / NGID1 6cpu0/alu/alu8/SLICE_640 SLICE R7C17D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(C*~D)+(B*D)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 NGID2 cpu0/regs/ea/ea_reg_3[4]/SLICE_495 SLICE R16C22C )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(~C*(B@D)+C*(~B*(D*~A))) K0::H0=(~C*(~D*(A*B))+C*(~D*(~B+A)+D*~B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 Ucpu0/alu/alu8/SLICE_641 SLICE R7C23A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(C*B)+(C*D) K0::H0=(D*~B)+(A*B)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 - NGID1 NGID2 cpu0/regs/ea/ea_reg_3[3]/SLICE_496 SLICE R15C26D )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~A*(~D+C)+A*~D) K0::H0=(~C*(D@A)+C*(~D*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 I NGID1 ^cpu0/alu/alu8/SLICE_642 SLICE R10C17C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 0 NGID1 NGID2 cpu0/regs/ea/ea_reg_3_i_m2[1]/SLICE_497 SLICE R15C21C )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(B*(D+A)) K0::H0=((~B*A+B*(C+A))+D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 K NGID1 Vcpu0/alu/alu8/SLICE_643 SLICE R8C15C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(D*~B)+(C*B)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 3 NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[14]/SLICE_498 SLICE R23C19A )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(((D+B)+C)+A) K0::H0=(~D*(C+B)+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 N NGID1 `cpu0/SLICE_644 SLICE R21C28D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*D)+(A*D)+(A*B) K0::H0=(A*C)+(~A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 6 NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[13]/SLICE_499 SLICE R24C19B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~A*D+A*(D*C))+B*(A*(D*C))) K0::H0=(~A*~B+A*(C*(D*~B))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*D)+(A*D)+(A*C) K0::H0=(A*C)+(~A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 9 NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[11]/SLICE_500 SLICE R23C20A )
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NGID1 NGID2 C NGID3 Dtextctrl/SLICE_645 SLICE R21C27C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*B)+(C*B)+(C*D) K0::H0=(A*C)+(~A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 < NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[10]/SLICE_501 SLICE R24C19C )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(B*(A*(C*D))) K0::H0=(~B*(~C*~D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*D)+(C*D)+(C*B) K0::H0=(A*C)+(~A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ? NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[8]/SLICE_502 SLICE R24C20A )
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NGID1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*D)+(A*D)+(A*C) K0::H0=(A*B)+(~A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 B NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_i_m2[1]/SLICE_503 SLICE R21C19A )
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textctrl/SLICE_646 SLICE R23C29C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*B)+(A*B)+(A*C) K0::H0=(B*C)+(~B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 H NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[3]/SLICE_504 SLICE R21C20A )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(((~D+C)+B)+A) K0::H0=(~A*(~D*(~C*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*D)+(A*D)+(A*C) K0::H0=(~A*D)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 K NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[6]/SLICE_505 SLICE R22C21D )
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NGID1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*D)+(A*D)+(A*C) K0::H0=(~A*C)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 N NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[5]/SLICE_506 SLICE R22C20D )
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ptextctrl/SLICE_647 SLICE R24C30D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*B)+(C*B)+(C*D) K0::H0=(~D*B)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Q NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[4]/SLICE_507 SLICE R22C20B )
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! " # $ % & ' ( 7MODE:LOGIC K1::H1=(D+A) K0::H0=(((B+D)+A)+C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*B)+(A*B)+(A*C) K0::H0=(~D*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 T NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[0]/SLICE_508 SLICE R21C20D )
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NGID1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*A)+(C*A)+(C*D) K0::H0=(~B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 W NGID1 NGID2 cpu0/regs/ea/un1_eapostbyte_16_6[7]/SLICE_509 SLICE R24C21A )
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textctrl/SLICE_648 SLICE R25C31C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*D)+(A*D)+(A*C) K0::H0=(A*C)+(~A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Z NGID1 NGID2 cpu0/regs/ea/ea_reg_3[2]/SLICE_510 SLICE R21C23C )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~B+(~C+(~A+D))) K0::H0=(~C*(~B+~A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(D*~B)+(C*B)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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NGID1
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cpu0/regs/ea/ea_reg_3[0]/SLICE_511 SLICE R21C25B )
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textctrl/SLICE_649 SLICE R23C30C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~D)+(B*D)+(B*C) K0::H0=(D*~C)+(B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
NGID2 cpu0/regs/ea/datamux_o_dest[0]/SLICE_512 SLICE R16C28D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(((D+B)+C)+A) K0::H0=(C*(~A*(~D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~C*A)+(C*D) K0::H0=(~B*C*D)+(C*A)+(~D*A)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 C NGID2 cpu0/regs/SU_16[0]/SLICE_513 SLICE R14C25D )
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NGID1
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~D*~A)+(D*A) K0::H0=(C*D)+(A*~D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 % NGID2 &cpu0/regs/SS_16[0]/SLICE_514 SLICE R16C25C )
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textctrl/SLICE_650 SLICE R23C28A )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~C*~D)+(C*D) K0::H0=(D*B)+(C*~B)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ( NGID2 )cpu0/regs/path_left_data[6]/SLICE_515 SLICE R19C24B )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~D+(~A+~C)) K0::H0=((C*(B*~A))+D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*B)+(C*D) K0::H0=(B*~A)+(C*A)+(C*B)+~D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 } NGID1 NGID2 cpu0/regs/path_left_data[5]/SLICE_516 SLICE R22C24C )
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n NGID1
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~A*B)+(A*C) K0::H0=(B*~C)+(A*C)+(A*B)+~D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[4]/SLICE_517 SLICE R23C24B )
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textctrl/SLICE_651 SLICE R24C30C )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*C)+(D*A) K0::H0=(D*~C)+(B*C)+(B*D)+~A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[3]/SLICE_518 SLICE R16C27D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(A*(B*C)) K0::H0=(~C*~A+C*(~A*(~D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*A)+(C*B) K0::H0=(C*~A)+(D*A)+(D*C)+~B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[1]/SLICE_519 SLICE R22C26D )
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s NGID1
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~A*D)+(A*C) K0::H0=(A*~D)+(B*D)+(B*A)+~C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[0]/SLICE_520 SLICE R23C27A )
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textctrl/SLICE_652 SLICE R23C29A )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~A*C)+(A*B) K0::H0=(B*~A)+(C*A)+(C*B)+~D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data[7]/SLICE_521 SLICE R23C26C )
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! " # $ % & ' (
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*D)+(C*A) K0::H0=(B*~C)+(A*C)+(A*B)+~D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[6]/SLICE_522 SLICE R19C25D )
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u NGID1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(D*~B)+(A*B)+(A*D)+C K0::H0=(~D*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 ! REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[5]/SLICE_523 SLICE R21C23A )
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textctrl/SLICE_653 SLICE R24C30A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(D*~B)+(C*B)+(C*D)+A K0::H0=(~C*B)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 # REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[3]/SLICE_524 SLICE R18C27B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*(~D*~C))) K0::H0=(~B*A+B*(A+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(B*~C)+(A*C)+(A*B)+D K0::H0=(~B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 % REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[1]/SLICE_525 SLICE R22C26A )
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v NGID1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(A*~B)+(D*B)+(D*A)+C K0::H0=(~B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 ' REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[0]/SLICE_526 SLICE R21C27A )
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textctrl/SLICE_654 SLICE R23C31B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(C*~A)+(B*A)+(B*C)+D K0::H0=(~B*A)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 ) REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_right_data[7]/SLICE_527 SLICE R22C26B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*~C) K0::H0=(A*(C*(B*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(B*~A)+(C*A)+(C*B)+D K0::H0=(~A*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 + REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_7[6]/SLICE_528 SLICE R19C24A )
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z NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(C*B)+(C*D) K0::H0=(B*~D)+(C*D)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 - REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_7[5]/SLICE_529 SLICE R22C24D )
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textctrl/SLICE_655 SLICE R23C30A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(D*A)+(D*B) K0::H0=(A*~D)+(C*D)+(C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 / REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_7[4]/SLICE_530 SLICE R23C23B )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(C*(A*B)) K0::H0=(D*((B+C)+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~B)+(D*B)+(D*A) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 1 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_7[3]/SLICE_531 SLICE R17C27D )
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} NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(A*~D)+(C*D)+(C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 3 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_7[1]/SLICE_532 SLICE R21C26D )
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textctrl/SLICE_656 SLICE R23C28D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(C*~B)+(D*B)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 5 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_7[0]/SLICE_533 SLICE R21C28A )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~A*(C*(D*B))) K0::H0=(~C*(~B*(D*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 7 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_7[8]/SLICE_534 SLICE R22C28A )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(B*A)+(B*C) K0::H0=(B*~D)+(C*D)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 9 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_6[8]/SLICE_535 SLICE R22C27A )
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textctrl/SLICE_657 SLICE R21C27D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(D*~A)+(B*A)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 ; REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/path_left_data_7[12]/SLICE_536 SLICE R18C27C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*(~C*~D))) K0::H0=(~A*(B*C)+A*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(A*~D)+(B*D)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 = REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 !cpu0/regs/path_left_data_6[12]/SLICE_537 SLICE R18C24C )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(B*D)+(B*A) K0::H0=(D*~A)+(C*A)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 ? REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 # NGID2 $cpu0/regs/path_left_data_7[13]/SLICE_538 SLICE R23C25B )
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textctrl/SLICE_658 SLICE R19C29A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 A REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 & NGID2 'cpu0/regs/path_left_data_6[13]/SLICE_539 SLICE R23C24A )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~D*(A*B)+D*(~B+A)) K0::H0=(~D*B+D*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(C*D)+(C*A) K0::H0=(B*~A)+(D*A)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 C REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ) NGID2 *cpu0/regs/path_left_data_7[10]/SLICE_540 SLICE R23C28C )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 E REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 , NGID2 -cpu0/regs/path_left_data_7[9]/SLICE_541 SLICE R17C26C )
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textctrl/SLICE_659 SLICE R19C27D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~D)+(C*D)+(C*B) K0::H0=(A*~B)+(D*B)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 G REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 / NGID2 0cpu0/regs/path_left_data_7[14]/SLICE_542 SLICE R16C26B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~D*C+D*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(C*A)+(C*B) K0::H0=(B*~C)+(A*C)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 I REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 2 NGID2 3cpu0/regs/path_left_data_7[11]/SLICE_543 SLICE R18C28B )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~B)+(A*B)+(A*D) K0::H0=(C*~B)+(D*B)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 K REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 5 NGID2 6cpu0/regs/path_left_data_6[11]/SLICE_544 SLICE R18C28D )
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textctrl/SLICE_660 SLICE R9C26D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~D)+(C*D)+(C*B) K0::H0=(C*~D)+(A*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 M REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 8 NGID2 9cpu0/regs/path_left_data_7[15]/SLICE_545 SLICE R19C28D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~C*B+C*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(B*~D)+(A*D)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 O REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ; NGID2
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(D*A)+(D*B) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 Q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 > NGID2 ?cpu0/regs/path_left_data_6[1]/SLICE_547 SLICE R22C25B )
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textctrl/SLICE_661 SLICE R9C26A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(C*~D)+(A*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 S REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 A NGID2 Bcpu0/regs/path_left_data_6[2]/SLICE_548 SLICE R22C24B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~B*(A*D)+B*(~D+A)) K0::H0=(~C*A+C*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(B*C)+(B*A) K0::H0=(C*~D)+(B*D)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 U REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 D NGID2 Ecpu0/regs/path_left_data_6[3]/SLICE_549 SLICE R16C27C )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(D*A)+(D*B) K0::H0=(C*~D)+(B*D)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 W REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 G NGID2 Hcpu0/regs/path_left_data_6[4]/SLICE_550 SLICE R23C23A )
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textctrl/SLICE_662 SLICE R12C26C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(B*D)+(B*A) K0::H0=(B*~A)+(C*A)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 Y REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 J NGID2 Kcpu0/regs/path_left_data_6[5]/SLICE_551 SLICE R22C23C )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~C*(A*D)+C*(~D+A)) K0::H0=(~B*A+B*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(C*~A)+(B*A)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 [ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 M NGID2 Ncpu0/regs/path_left_data_6[6]/SLICE_552 SLICE R21C24A )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~D)+(A*D)+(A*C) K0::H0=(D*~A)+(C*A)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 ] REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 P NGID2 Qcpu0/regs/path_left_data_7[7]/SLICE_553 SLICE R23C26B )
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textctrl/SLICE_663 SLICE R9C26C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~B)+(D*B)+(D*A) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 _ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 S NGID2 Tcpu0/regs/path_left_data_6[7]/SLICE_554 SLICE R23C26A )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~B*(C*D)+B*(~D+C)) K0::H0=(~C*D+C*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~D)+(A*D)+(A*B) K0::H0=(C*~A)+(D*A)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 a REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 V NGID2 Wcpu0/regs/path_right_data_6[12]/SLICE_555 SLICE R18C24B )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~A)+(C*A)+(C*D) K0::H0=(C*~A)+(B*A)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 c REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ^ NGID2 _cpu0/regs/path_right_data_6[4]/SLICE_556 SLICE R23C23D )
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textctrl/SLICE_664 SLICE R19C26C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(B*D)+(B*A) K0::H0=(D*~C)+(B*C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 e REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 a NGID2 bcpu0/regs/path_right_data_7[6]/SLICE_557 SLICE R19C25B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~C*(B*D)+C*(~D+B)) K0::H0=(~B*C+B*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~B)+(D*B)+(D*A) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 g REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 d NGID2 ecpu0/regs/path_right_data_7[5]/SLICE_558 SLICE R21C23D )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(D*C)+(D*A) K0::H0=(A*~C)+(D*C)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 i REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ( NGID1 g NGID2 hcpu0/regs/path_right_data_7[4]/SLICE_559 SLICE R23C23C )
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textctrl/SLICE_665 SLICE R19C29B )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(A*~C)+(D*C)+(D*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 k REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 + NGID1 j NGID2 kcpu0/regs/path_right_data_7[3]/SLICE_560 SLICE R17C27C )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~B*(D*A)+B*(~A+D)) K0::H0=(~D*C+D*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(B*~D)+(C*D)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 m REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1 m NGID2 ncpu0/regs/path_right_data_7[1]/SLICE_561 SLICE R21C26B )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(B*D)+(B*A) K0::H0=(C*~A)+(D*A)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 o REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 1 NGID1 p NGID2 qcpu0/regs/path_right_data_7[0]/SLICE_562 SLICE R21C28D )
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textctrl/SLICE_666 SLICE R24C29D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 s NGID2 tcpu0/regs/path_right_data_7[12]/SLICE_563 SLICE R18C24A )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(C+B) K0::H0=(~B*(~D*(~C*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(C*~D)+(B*D)+(B*C) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 s REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 7 NGID1 v NGID2 wcpu0/regs/path_right_data_6[6]/SLICE_564 SLICE R21C25C )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(D*C)+(D*A) K0::H0=(A*~D)+(C*D)+(C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 u REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ; NGID1 z NGID2 {cpu0/regs/path_right_data_6[5]/SLICE_565 SLICE R22C22B )
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textctrl/SLICE_667 SLICE R23C27B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~D)+(A*D)+(A*C) K0::H0=(B*~A)+(D*A)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 w REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 } NGID2 ~cpu0/regs/path_right_data_6[2]/SLICE_566 SLICE R22C23B )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~B*~D) K0::H0=(~D*(~B*(A*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(C*~A)+(B*A)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 y REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 A NGID1 NGID2 cpu0/regs/path_right_data_6[1]/SLICE_567 SLICE R22C25A )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~A)+(B*A)+(B*D) K0::H0=(D*~B)+(A*B)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 { REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 D NGID1 NGID2 cpu0/regs/path_right_data_6[0]/SLICE_568 SLICE R23C27D )
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textctrl/SLICE_668 SLICE R24C29A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~D)+(A*D)+(A*B) K0::H0=(C*~A)+(D*A)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 } REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 G NGID1 NGID2 cpu0/regs/path_right_data_7[7]/SLICE_569 SLICE R23C26D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D*(~A*B))+C*(~D*B)) K0::H0=(~D*~C) REG0::::SD=0 Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(B*~D)+(C*D)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 J NGID1 NGID2 cpu0/regs/path_right_data_6[7]/SLICE_570 SLICE R22C26C )
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NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~A)+(C*A)+(C*D) K0::H0=(C*~D)+(A*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 M NGID1 NGID2 cpu0/regs/path_right_data_7[14]/SLICE_571 SLICE R18C26C )
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NGID2
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(A*~D)+(C*D)+(C*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 P NGID1 NGID2 cpu0/regs/path_right_data_6[14]/SLICE_572 SLICE R18C26D )
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_cpu0/test_cond/SLICE_669 SLICE R15C30D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(C*D)+(C*A) K0::H0=(B*~A)+(C*A)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 S NGID1 NGID2 cpu0/regs/path_right_data_7[11]/SLICE_573 SLICE R18C29A )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(C*(D*(~A*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_670 SLICE R14C30B )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(C*~A)+(D*A)+(D*C) K0::H0=(B*~D)+(C*D)+(C*B) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 V NGID1 NGID2 cpu0/regs/path_right_data_6[11]/SLICE_574 SLICE R18C29B )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~C*(~B*A)+C*(A+B)) K0::H0=(D*(B*(C*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_671 SLICE R15C30A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(D*C)+(D*A) K0::H0=(C*~D)+(A*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Y NGID1 NGID2 cpu0/regs/path_right_data_7[13]/SLICE_575 SLICE R23C24C )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~C*(~D*A)+C*(A+D)) K0::H0=(~A*(~B*(D*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_672 SLICE R14C30A )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~A)+(C*A)+(C*B) K0::H0=(A*~C)+(D*C)+(D*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \ NGID1 NGID2 cpu0/regs/path_right_data_6[13]/SLICE_576 SLICE R23C24D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~C*(~B*A)+C*(A+B)) K0::H0=(A*(~D*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_673 SLICE R14C30C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~B)+(C*B)+(C*A) K0::H0=(C*~B)+(D*B)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _ NGID1 NGID2 cpu0/regs/path_right_data_7[15]/SLICE_577 SLICE R19C29C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~A*(~D*C)+A*(C+D)) K0::H0=(A*(~C*(D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_674 SLICE R14C29C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~B)+(D*B)+(D*A) K0::H0=(B*~D)+(C*D)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 b NGID1 NGID2 cpu0/regs/path_right_data_6[15]/SLICE_578 SLICE R18C29C )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*(~C*B)+D*(B+C)) K0::H0=(~C*(~D+~B)+C*(B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_675 SLICE R9C31C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~D)+(C*D)+(C*A) K0::H0=(B*~C)+(A*C)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 NGID2 cpu0/regs/right_0_m2_1[9]/SLICE_579 SLICE R17C26A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~D*(~B*C+B*A)+D*C) K0::H0=(~B*(~D*~A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_676 SLICE R10C27C )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(B*~D)+(C*D)+(C*B) K0::H0=(B*~A)+(D*A)+(D*B) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 h NGID1 NGID2 cpu0/regs/right_0_m2_2[9]/SLICE_580 SLICE R17C26B )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~B*(A*(~C*D))) K0::H0=(~B*(D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_677 SLICE R10C29D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(D*A)+(D*B) K0::H0=(D*~A)+(C*A)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 NGID2 cpu0/regs/path_right_data_6[8]/SLICE_581 SLICE R22C28D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(~A*B+A*(B*~D))+C*(B*~D)) K0::H0=(A*(C*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_678 SLICE R15C29C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(A*~C)+(D*C)+(D*A) K0::H0=(B*~A)+(C*A)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 n NGID1 NGID2 cpu0/regs/path_right_data_7[8]/SLICE_582 SLICE R22C28C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~C*~D+C*(~D*~A+D*(B*~A))) K0::H0=(C*(D*(A*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Pcpu0/dec_alu/SLICE_679 SLICE R10C30A YMODE:LOGIC K1::H1=(~D*(~C*A+C*B)+D*(C*B)) K0::H0=(~D*(C*(~B*A))+D*(~C*(~B*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_680 SLICE R14C27C )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(C*~B)+(D*B)+(D*C) K0::H0=(B*~D)+(A*D)+(A*B) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 q NGID1 NGID2 cpu0/regs/PC_9[12]/SLICE_583 SLICE R19C28B )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(B*(D*(C*A))) K0::H0=(~C*(~A+~D)+C*(~B*~D+B*(~A+~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_681 SLICE R8C30B )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*B)+(C*D) K0::H0=(C*A)+(B*~A)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/PC_9[14]/SLICE_584 SLICE R21C27B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~D*(C*B))+A*(~D*~C)) K0::H0=(~A*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_682 SLICE R10C29B )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*C)+(D*A) K0::H0=(D*A)+(B*~A)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/PC_9[11]/SLICE_585 SLICE R18C25C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(((C*A)+D)*B)+(D*~B) K0::H0=(D*(~A*(~B*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_683 SLICE R12C26A )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*B)+(C*A) K0::H0=(D*C)+(A*~C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/PC_9[13]/SLICE_586 SLICE R19C23D )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(C*(~B*(D*A))) K0::H0=(C*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_684 SLICE R12C27B )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*D)+(C*A) K0::H0=(D*C)+(B*~C)+(B*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/PC_9[15]/SLICE_587 SLICE R18C28C )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(B*(~A*(D*C))) K0::H0=(D*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_685 SLICE R12C27D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*A)+(C*D) K0::H0=(C*A)+(D*~A)+(D*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 " NGID2 #cpu0/regs/PC_9[10]/SLICE_588 SLICE R18C27D )
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! " # $ % & ' ( 7MODE:LOGIC K1::H1=(D*(A*(B*C))) K0::H0=(D*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_686 SLICE R9C28D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*B)+(C*D) K0::H0=(C*B)+(A*~B)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ( NGID2 )cpu0/regs/PC_9[9]/SLICE_589 SLICE R18C25D )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=((C*(B*~A))+D) K0::H0=(D+B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ycpu0/SLICE_687 SLICE R8C29A )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*D)+(C*A) K0::H0=(A*C)+(B*~C)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 . NGID2 /cpu0/regs/PC_9[8]/SLICE_590 SLICE R21C27C )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~D*A+D*(~C*A+C*(A+B))) K0::H0=(~A*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_688 SLICE R18C31B )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*B)+(C*A) K0::H0=(C*D)+(A*~D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 5 NGID2 6cpu0/regs/path_left_data_7[2]/SLICE_591 SLICE R22C24A )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~B*(~C*(D*~A))) K0::H0=(~A*(~D*(C*B)+D*B)+A*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 qcpu0/SLICE_689 SLICE R15C40A )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(D*~C)+(B*C)+(B*D) K0::H0=(A*~D)+(C*D)+(C*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 K NGID1 NGID2 cpu0/regs/path_left_data_6[10]/SLICE_592 SLICE R22C23D )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~C*~A) K0::H0=(~A*C+A*(C*(B+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_690 SLICE R19C35A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(C*~A)+(B*A)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 L NGID1 NGID2 cpu0/regs/path_left_data_6[9]/SLICE_593 SLICE R17C26D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(B*(~D*C+D*(A*C))) K0::H0=(~D*A+D*(A*(~C*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Jcpu0/SLICE_691 SLICE R19C28B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~A)+(D*A)+(D*B) K0::H0=(D*~C)+(A*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 M NGID1 NGID2 cpu0/regs/path_left_data_6[14]/SLICE_594 SLICE R18C26B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=((B*(~C*~D))+A) K0::H0=(D*(C*(B*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Ycpu0/SLICE_692 SLICE R21C28C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~B)+(A*B)+(A*C) K0::H0=(B*~C)+(A*C)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 N NGID1 NGID2 cpu0/regs/path_left_data_6[15]/SLICE_595 SLICE R18C28A )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~C*B*A)*~D K0::H0=(A*(D*(~C*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 xcpu0/SLICE_693 SLICE R21C16D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~D)+(A*D)+(A*B) K0::H0=(B*~C)+(A*C)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 O NGID1 NGID2 cpu0/regs/path_right_data_7[2]/SLICE_596 SLICE R22C23A )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(D*(~B*(A*C)+B*C)) K0::H0=(~D*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_694 SLICE R14C22B )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(D*~A)+(B*A)+(B*D) K0::H0=(C*~A)+(D*A)+(D*C) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 P NGID1 NGID2 cpu0/regs/path_right_data_6[3]/SLICE_597 SLICE R16C27B )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~A*(~D*(~C*B)+D*(B+C))+A*B) K0::H0=(D*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C)+(D*C)+(D*B) K0::H0=(A*~D)+(B*D)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Q NGID1 NGID2 cpu0/regs/path_right_data_7[10]/SLICE_598 SLICE R23C28B )
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cpu0/SLICE_695 SLICE R22C19C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(D*~C)+(A*C)+(A*D) K0::H0=(A*~B)+(D*B)+(D*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 R NGID1 NGID2 cpu0/regs/path_right_data_6[10]/SLICE_599 SLICE R21C23B )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~B*(A*D)+B*(A*(D+C))) K0::H0=(A*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_696 SLICE R11C29D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(C*~D)+(B*D)+(B*C) K0::H0=(C*~A)+(B*A)+(B*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 S NGID1 NGID2 4cpu0/alu/alu16/a16/overflow_out/SLICE_600 SLICE R12C31C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*A+B*(~C*(D+A)+C*A)) K0::H0=(A*(D*(C*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ccpu0/dec_op/SLICE_697 SLICE R15C32A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(B*~C*D)+(~A*~B*C) K0::H0=(B*C*~A)+(~B*~C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 & NGID2 'cpu0/alu/alu16/q_out_3[14]/SLICE_601 SLICE R16C32A )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(D*(A*(B*C))) K0::H0=(D*(C*(~A*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 {cpu0/dec_op/SLICE_698 SLICE R16C35D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(A*B)+(~A*D) K0::H0=D*A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 s NGID1 NGID2 cpu0/alu/alu16/q_out_3[13]/SLICE_602 SLICE R17C32D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~A*(C*D)+A*(~C*B+C*(D+B))) K0::H0=(~A*(~C*(D@B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 zcpu0/SLICE_699 SLICE R15C32D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(C*B)+(~C*A) K0::H0=C*A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 v NGID1 NGID2 cpu0/alu/alu16/q_out_3[12]/SLICE_603 SLICE R14C29D )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~C*(~D*(~B*A)+D*A)+C*A) K0::H0=(D*(~A*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_700 SLICE R14C27B )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(B*A)+(~B*C) K0::H0=C*A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 y NGID1 NGID2 cpu0/alu/alu16/q_out_3[11]/SLICE_604 SLICE R17C32A )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~A+(~C*(~B*D))) K0::H0=(~C*(D*A)+C*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Lcpu0/SLICE_701 SLICE R15C36D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(D*B)+(~D*C) K0::H0=C*A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 NGID2 cpu0/alu/alu16/q_out_3[10]/SLICE_605 SLICE R17C31B )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(C*B) K0::H0=(~C*(B*(A@D))+C*(~B*~A+B*(A@D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(D*A)+(~D*C) K0::H0=B*A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[9]/SLICE_606 SLICE R12C31B )
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NGID1 ucpu0/dec_op/SLICE_702 SLICE R7C26B )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(D*B)+(~D*C) K0::H0=D*A OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[8]/SLICE_607 SLICE R12C32A )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~D+~C) K0::H0=(D*(A*(~C*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_703 SLICE R12C31C )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(A*C)+(~A*D) K0::H0=A*D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out_3[15]/SLICE_608 SLICE R17C30D )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(A*B) K0::H0=(~D*(~A*(B*C))) F1:F F0:F 4 MODE K1 K0
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(C*B)+(~C*D) K0::H0=C*B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[0]/SLICE_609 SLICE R14C28B )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_704 SLICE R17C27A )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~A*D)+(A*C) K0::H0=(B*~D*C)+(A*B*C)+(A*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[1]/SLICE_610 SLICE R12C28B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(B*D) K0::H0=(~A*(D*(~B*C))) F1:F F0:F 4 MODE K1
K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~C*D)+(C*A) K0::H0=(C*~A*D)+(B*C*D)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[2]/SLICE_611 SLICE R12C28C )
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cpu0/SLICE_705 SLICE R14C31A )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*C)+(B*A) K0::H0=(C*~B*D)+(A*C*D)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[3]/SLICE_612 SLICE R15C28C )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(A+C) K0::H0=(B*(A*(~D*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_706 SLICE R16C35C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*B)+(D*A) K0::H0=(B*~D*A)+(C*B*A)+(C*D) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[4]/SLICE_613 SLICE R12C29A )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(A*(D*(~C+~B))) K0::H0=(C*(~A*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ^cpu0/SLICE_707 SLICE R19C31B )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*D)+(B*A) K0::H0=(D*~A*C)+(B*D*C)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[5]/SLICE_614 SLICE R14C31D )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~D*(~B*(~C*A))) K0::H0=(C*(D*(B*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 vcpu0/SLICE_708 SLICE R17C28B )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*D)+(B*C) K0::H0=(A*~B*C)+(D*A*C)+(D*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[6]/SLICE_615 SLICE R14C32D )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(A+C) K0::H0=(~C*(A*(B*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_709 SLICE R16C26B )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*D)+(B*A) K0::H0=(C*~B*D)+(A*C*D)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu16/q_out[7]/SLICE_616 SLICE R14C32A )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=((D*(~C*A))+B) K0::H0=(A*(D*(~C*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_710 SLICE R12C27C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*D)+(B*C) K0::H0=(C*~A*D)+(B*C*D)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/un1_state_104_i_o4_RNI188S5/SLICE_617 SLICE R19C15D )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~B*(D*(~C+~A))+B*D) K0::H0=(~D+(~A+(C+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_711 SLICE R21C32A )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(B*C)+(~D*C)+(~A*C) K0::H0=(~D*C)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 kcpu0/alu/alu8/datamux_o_dest[1]/SLICE_618 SLICE R14C27B )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~C*D+C*A) K0::H0=(~D*(~C*(A*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_712 SLICE R21C35D )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*A)+(D*C) K0::H0=(~B*C*D)+(C*A)+(~D*A)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_619 SLICE R14C28C )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(D*C) K0::H0=(~A*(~C*(D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_713 SLICE R21C31A )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~A*D)+(A*C) K0::H0=(~A*C*D)+(C*B)+(~D*B)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/datamux_o_dest[3]/SLICE_620 SLICE R15C27C )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~C*D+C*B) K0::H0=(~D*(~A*(~B*~C))+D*(~B*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_714 SLICE R22C33A )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*A)+(D*B) K0::H0=(~A*C*D)+(C*B)+(~D*B)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/datamux_o_dest[6]/SLICE_621 SLICE R16C29A )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~B*C+B*D) K0::H0=(C*(~A*(~B*D))) F1:F F0:F 4 MODE K1 ! K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_715 SLICE R15C34A )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*C)+(D*A) K0::H0=(~B*D*C)+(D*A)+(~C*A)+(B*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/datamux_o_dest[7]/SLICE_622 SLICE R14C30B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(B*(D*(~A*~C))) K0::H0=(B*(~C*(D*A))) F1:F F0:F 4 MODE K1 # K0 " REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ! NGID1 cpu0/SLICE_716 SLICE R17C25B )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*A)+(D*C) K0::H0=(~A*C*D)+(C*B)+(~D*B)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/datamux_o_dest[15]/SLICE_623 SLICE R14C29A )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~A*(C*D)+A*(~C+D)) K0::H0=(~A*(C*D)+A*(~B*(C*D)+B*(~D+C))) F1:F F0:F 4 MODE K1 % K0 $ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 cpu0/SLICE_717 SLICE R16C31A )
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! " # $ % & ' ( ^MODE:LOGIC K1::H1=(A*B*D)+(C*~B*D)+(A*C*D) K0::H0=(~A*D*C)+(D*B)+(~C*B)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/CCRo[1]/SLICE_624 SLICE R8C28C )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(A*(~B*(C*~D))) K0::H0=(~B*(~C*(A*D))) F1:F F0:F 4 MODE K1 ' K0 & REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 $ NGID1 [cpu0/dec_op/SLICE_718 SLICE R14C23D )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(A*~D)+(C*~D)+(C*A) K0::H0=(C*D*A)+(~D*B)+(~C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 " NGID2 #cpu0/alu/alu8/q_out_4[7]/SLICE_625 SLICE R8C29C )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~C*(A*(B*D))) K0::H0=(~A*(B+C)+A*(~D+(B+C))) F1:F F0:F 4 MODE K1 ) K0 ( REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 & NGID1 cpu0/dec_op/SLICE_719 SLICE R17C28A )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(B*D)+(A*D)+(A*~B) K0::H0=(~D*C)+(D*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 9 NGID1 ' NGID2 (cpu0/alu/alu8/q_out_5[5]/SLICE_626 SLICE R9C29D )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(D*(~B*(~C*A)+B*(C*A))) K0::H0=(~C*(~A*B+A*(~D+B))) F1:F F0:F 4 MODE K1 + K0 * REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 1cpu0/SLICE_720 SLICE R15C31A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(B*A*~C)+(~A*C)+(~B*C) K0::H0=~A*D*~B*~C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @ NGID1 . NGID2 /cpu0/alu/alu8/q_out_5[6]/SLICE_627 SLICE R9C29B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(C*(B*D))) K0::H0=(~B*(D*~A)+B*(D*(~A+C))) F1:F F0:F 4 MODE K1 - K0 , REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 + NGID1 cpu0/SLICE_721 SLICE R18C34B )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(D*~B*C*~A)+(B*A)+(~C*A)+(~D*A) K0::H0=~A*D OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 C NGID1 1 NGID2 2cpu0/alu/alu8/CCRo[0]/SLICE_628 SLICE R8C25D )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~B*(~A*(~C*D))) K0::H0=(~A*(B*C)+A*C) F1:F F0:F 4 MODE K1 / K0 . REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 cpu0/SLICE_722 SLICE R17C34C )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(A*~D)+(C*~D)+(C*A) K0::H0=(~C*D)+(C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 F NGID1 4 NGID2 5cpu0/alu/alu8/q_out_5[7]/SLICE_629 SLICE R8C29D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A+(~B+(~C+D))) K0::H0=(B*(~A*(D*~C))) F1:F F0:F 4 MODE K1 1 K0 0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1 cpu0/SLICE_723 SLICE R17C30B )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(A*D*~B)+(C*D*~B)+(~C*~A*B)+(~D*B) K0::H0=~B*C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 I NGID1 7 NGID2 8cpu0/alu/alu8/q_out_4[0]/SLICE_630 SLICE R10C27D )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~B*(~D+(A*~C))+B*(A*~C)) K0::H0=(B*(A*(C*~D))) F1:F F0:F 4 MODE K1 3 K0 2 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 / NGID1 $cpu0/SLICE_724 SLICE R19C33D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(B*~D)+(C*D)+(C*B) K0::H0=(~A*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 L NGID1 : NGID2 ;cpu0/alu/alu8/q_out_5[1]/SLICE_631 SLICE R10C28B )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(A*(B*(C*~D))) K0::H0=(D*(~A*C+A*(B*C))) F1:F F0:F 4 MODE K1 5 K0 4 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 0 NGID1 cpu0/SLICE_725 SLICE R17C34D )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(~D*~B*A)+(C*B*~A)+(D*C*~A)+(~C*A) K0::H0=~A*C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 O NGID1 = NGID2 >cpu0/alu/alu8/q_out_5[2]/SLICE_632 SLICE R11C28D )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~(D+C)*A)*B K0::H0=(C*(~A+(~B+D))) F1:F F0:F 4 MODE K1 7 K0 6 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 2 NGID1 NGID2 cpu0/SLICE_726 SLICE R18C31C )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(B*~C*D*~A)+(C*A)+(~D*A)+(~B*A) K0::H0=~A*C OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 R NGID1 @ NGID2 Acpu0/alu/alu8/q_out_5[3]/SLICE_633 SLICE R9C28D )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~B*(D*(A*C))) K0::H0=(((C*D)+A)+B) F1:F F0:F 4 MODE K1 9 K0 8 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 3 NGID1 cpu0/SLICE_727 SLICE R17C32C )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(C*B*~D)+(A*B*~D)+(~A*~C*D)+(~B*D) K0::H0=~C*B OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 U NGID1 C NGID2 Dcpu0/alu/alu8/q_out_4[1]/SLICE_634 SLICE R10C28A )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(B*(C*(D*~A))) K0::H0=(~C*(~B*(D*A))) F1:F F0:F 4 MODE K1 ; K0 : REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 9 NGID1 pcpu0/SLICE_728 SLICE R15C32B )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(D*B)+(A*B)+(A*~D) K0::H0=(~B*D)+(B*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Z NGID1 H NGID2 Icpu0/alu/alu8/q_out_4[2]/SLICE_635 SLICE R11C28C )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~D*~A) K0::H0=(C*(B*(~D*A))) F1:F F0:F 4 MODE K1 = K0 < REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 : NGID1 cpu0/dec_op/SLICE_729 SLICE R18C30D )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(C*B)+(A*B)+(A*~C) K0::H0=(~B*D)+(B*C) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ] NGID1 K NGID2 Lcpu0/alu/alu8/q_out_4[3]/SLICE_636 SLICE R9C28C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~B*(~D+C)+B*(~D*~A+D*(C*~A))) K0::H0=(~B*(~C*~A)) F1:F F0:F 4 MODE K1 ? K0 > REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 < NGID1 cpu0/SLICE_730 SLICE R17C29C )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(B*C)+(A*C)+(A*~B) K0::H0=(~B*C)+(B*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ` NGID1 N NGID2 Ocpu0/alu/alu8/q_out_4[5]/SLICE_637 SLICE R9C29C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=~B*~((A*D)*~C) K0::H0=(~A*D+A*(D*(~C*~B))) F1:F F0:F 4 MODE K1 A K0 @ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 F NGID1 NGID2 Icpu0/SLICE_731 SLICE R17C29D )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(B*C)+(A*C)+(A*~B) K0::H0=(~B*A)+(B*D) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 d NGID1 R NGID2 Scpu0/alu/alu8/q_out_4[6]/SLICE_638 SLICE R9C29A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~B*(~C+~D)+B*~C) K0::H0=(~D*C+D*(~C*(~A*B)+C*~A)) F1:F F0:F 4 MODE K1 C K0 B REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 G NGID1 =cpu0/SLICE_732 SLICE R19C32C )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(C*B)+(D*B)+(D*~C) K0::H0=(~B*D)+(B*A) OFX1:F OFX0:F M1MUX:M1 M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 g NGID1 U NGID2 Vcpu0/alu/alu8/CCRo[4]/SLICE_639 SLICE R11C26B )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~C*((A+B)+D)+C*(A+B)) K0::H0=(((B*C)+D)+A) F1:F F0:F 4 MODE K1 E K0 D REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 I NGID1 cpu0/SLICE_733 SLICE R15C27D )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(C*~D)+(B*~D)+(B*C) K0::H0=(A*B)+(D*B)+(D*~A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 j NGID1 X NGID2 Ycpu0/alu/alu8/v8_0/SLICE_640 SLICE R8C30D )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(~B*(~A+(~C+D))+B*(~A*(D+C)+A*D)) K0::H0=(~C+(~A*D)) F1:F F0:F 4 MODE K1 G K0 F REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 K NGID1 cpu0/SLICE_734 SLICE R22C34D )
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! " # $ % & ' ( ^MODE:LOGIC K1::H1=A*C*~B*~D K0::H0=(~B*D*C)+(B*~D*C)+(A*B*~D)+(A*~B*D)+(A*~C) OFX0:F M0MUX:M0 4 MODE K1 K0
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 n NGID1 \ NGID2 ]cpu0/alu/alu8/q_out_1[4]/SLICE_641 SLICE R8C26C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(A*(B*C)) K0::H0=(~D*(~B*C)) F1:F F0:F 4 MODE K1 I K0 H REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 N NGID1 cpu0/dec_op/SLICE_735 SLICE R17C29B )
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! " # $ % & ' ( aMODE:LOGIC K1::H1=(D*~B*C)+(~D*B*C)+(D*B*~C)+(D*C*~A)+(B*~A) K0::H0=(~C*A)+(C*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 t NGID1 b NGID2 ccpu0/alu/alu8/c8_1/SLICE_642 SLICE R8C26D )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~C*~B+C*(~D*~B)) K0::H0=(~D*~A+D*C) F1:F F0:F 4 MODE K1 K K0 J REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 S NGID1 acpu0/SLICE_736 SLICE R18C28D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(C*D)+(C*A) K0::H0=(~A*D)+(A*C) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 j NGID2 kcpu0/alu/alu8/q_out[4]/SLICE_643 SLICE R8C28D )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~C*B+C*(~A*(B+D)+A*(~D+B))) K0::H0=(B*~C) F1:F F0:F 4 MODE K1 M K0 L REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 T NGID1 cpu0/dec_op/SLICE_737 SLICE R14C32A )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~C*A)+(C*D) K0::H0=(~C*~A*B)+(C*A) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 i NGID2 Qcpu0/alu/alu8/datamux_o_dest[4]/SLICE_644 SLICE R14C29B )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*B+C*(~D+B)) K0::H0=(~D*(~A*(~C+B)+A*B)+D*B) F1:F F0:F 4 MODE K1 O K0 N REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 W NGID1 ncpu0/dec_op/SLICE_738 SLICE R16C35B )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~A*B)+(A*D) K0::H0=(~A*D*C)+(D*B)+(~C*B)+(A*B) OFX0:F M0MUX:M0 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/test_cond/SLICE_645 SLICE R17C10B )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(~B*(~C*(D*A))) K0::H0=((D+C)+B) F1:F F0:F 4 MODE K1 Q K0 P REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \ NGID1 ucpu0/dec_op/SLICE_739 SLICE R14C26C )
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! " # $ % & ' ( WMODE:LOGIC K1::H1=(~B*(~D*(C*~A)+D*(~C+~A))) K0::H0=(~B*(~D*C+D*(~A+C))+B*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_646 SLICE R15C17C )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~C*(~B*(A*D))) K0::H0=(~B*(D*~C)) F1:F F0:F 4 MODE K1 S K0 R REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ] NGID1 cpu0/dec_op/SLICE_740 SLICE R14C32C )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=C+((~A+~D)*B) K0::H0=(C*(~D*(~A+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_regs/SLICE_647 SLICE R21C11B )
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(~C+(~B*~A+B*(~D*~A))) K0::H0=(~C*(~D*~B)+C*(~D*~B+D*A)) F1:F F0:F 4 MODE K1 U K0 T REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 cpu0/SLICE_741 SLICE R19C32B )
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! " # $ % & ' ( \MODE:LOGIC K1::H1=(~C*D+C*(~B*D+B*(A+D))) K0::H0=(~C*(A*(B@D))+C*(~A*~B+A*(B@D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_648 SLICE R14C19B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~D*(~C+(A+B))+D*A) K0::H0=((~C+B)+D) F1:F F0:F 4 MODE K1 W K0 V REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 g NGID1 cpu0/SLICE_742 SLICE R17C31C )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~B*(~A*(D*C))) K0::H0=(~B*((A*D)+C)+B*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_649 SLICE R14C19A )
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! " # $ % & ' (
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~B*(~D*(C*A))) K0::H0=(~C*((B*A)+D)+C*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_650 SLICE R12C16A )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(D*(C*(B*A))) K0::H0=(~C*(~D*~A)) F1:F F0:F 4 MODE K1 [ K0 Z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 m NGID1 cpu0/SLICE_744 SLICE R15C28C )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(C*(~D*(A*B))) K0::H0=(~C*B+C*(~D*(A+B)+D*B)) F1:F F0:F 4 MODE K1 ! K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_651 SLICE R21C18B )
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! " # $ % & ' ( `MODE:LOGIC K1::H1=(~C*(~A*(~D*B)+A*B)+C*(A*(D*B))) K0::H0=(~A*~C+A*(~B*(~D*~C)+B*~C)) F1:F F0:F 4 MODE K1 ] K0 \ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 p NGID1 cpu0/SLICE_745 SLICE R16C32B )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~B*((~C+D)+A)+B*(~C+D)) K0::H0=(A*(D*(B*C))) F1:F F0:F 4 MODE K1 # K0 " REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 2 NGID1 >cpu0/SLICE_652 SLICE R18C19D )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(((~A+~B)+D)+C) K0::H0=(~A*~C) F1:F F0:F 4 MODE K1 _ K0 ^ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 r NGID1 cpu0/SLICE_746 SLICE R10C27D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=((B+C)*D)+((((B+C)*A)+(C*~A))*~D) K0::H0=(~C*(~B*A+B*(D*A))+C*A) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 % K0 $ REG1 ' REG0 & Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 G NGID4 Hcpu0/regs/SLICE_653 SLICE R18C20A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(C*~D)*A K0::H0=(~D*B+D*(~A*B+A*(B+C))) F1:F F0:F 4 MODE K1 a K0 ` REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 t NGID1 NGID2 cpu0/dec_op/SLICE_747 SLICE R12C31D )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~B*A+B*(~C*A+C*(~D+A))) K0::H0=(~D*(~A*(~B*~C))) F1:F F0:F 4 MODE K1 ) K0 ( REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/SLICE_654 SLICE R7C28A )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~D*(C*(~A*B))) K0::H0=(~B*(~A*(D*C)+A*(~D*C))+B*(A*(~D*C))) F1:F F0:F 4 MODE K1 c K0 b REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 v NGID1 cpu0/SLICE_748 SLICE R21C28B )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=((B+~(D*C))*A)+((B*D*C)*~A) K0::H0=(~A*B+A*(~C*D+C*B)) F1:F F0:F 4 MODE K1 , K0 + REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 n NGID2 |cpu0/alu/alu8/SLICE_655 SLICE R8C25A )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~A*(B*~C)) K0::H0=(D*(B*(~C*~A))) F1:F F0:F 4 MODE K1 e K0 d REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 w NGID1 cpu0/dec_op/SLICE_749 SLICE R16C31B )
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! " # $ % & ' ( eMODE:LOGIC K1::H1=(~B*(~C+(D@A))+B*(~C*(D*~A)+C*(D@A))) K0::H0=(~D*(B*(~A*C))+D*(B*(A@C))) F1:F F0:F 4 MODE K1 . K0 - REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 textctrl/SLICE_656 SLICE R24C10D )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~D+A) K0::H0=(~B*((~D+C)+A)+B*~D) F1:F F0:F 4 MODE K1 g K0 f REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 cpu0/SLICE_750 SLICE R16C28A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(C*(D*(B+A))) K0::H0=(A*(~C*B+C*(B+D))) F1:F F0:F 4 MODE K1 0 K0 / REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( ZMODE:LOGIC K1::H1=(~A*C+A*(~D*C+D*(~B*C))) K0::H0=(~D*(A*(B*~C))+D*(A*(~B*~C))) F1:F F0:F 4 MODE K1 i K0 h REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 } NGID1 cpu0/SLICE_751 SLICE R19C34A )
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NGID1
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*~D) K0::H0=(A*(D*(C*B))) F1:F F0:F 4 MODE K1 k K0 j REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 zcpu0/SLICE_752 SLICE R8C27C )
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textctrl/SLICE_657 SLICE R23C7D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~A*~C+A*(~D*(~B*~C)+D*~C)) K0::H0=(A*(D*C)) F1:F F0:F 4 MODE K1 m K0 l REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_753 SLICE R18C29A )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(B*(C*(D*A))) K0::H0=(~B*~C+B*(~D*(~A*~C))) F1:F F0:F 4 MODE K1 2 K0 1 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( =MODE:LOGIC K1::H1=((C+B)+A) K0::H0=(D*(C*(~B*~A))) F1:F F0:F 4 MODE K1 o K0 n REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_754 SLICE R16C29B )
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NGID1
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~C*(~B*~D+B*(~A*~D))+C*(~B*(A*~D))) K0::H0=(A*C) F1:F F0:F 4 MODE K1 q K0 p REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_755 SLICE R14C28D )
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cpu0/test_cond/SLICE_658 SLICE R17C10C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(D+C)+A*(~C+(~D+B))) K0::H0=(~A*~D) F1:F F0:F 4 MODE K1 s K0 r REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_756 SLICE R16C36B )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=((~B*(D*C))+A) K0::H0=(A*(C*(D*B))) F1:F F0:F 4 MODE K1 4 K0 3 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_659 SLICE R10C21D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~A+D)+B*(~C*(~A+D))) K0::H0=(~B*D) F1:F F0:F 4 MODE K1 u K0 t REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_757 SLICE R22C33C )
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(~A*D+A*B) K0::H0=(~B*(~D*C+D*(A@~C))+B*(~D*(A@C)+D*~C)) F1:F F0:F 4 MODE K1 6 K0 5 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 2cpu0/test_cond/SLICE_660 SLICE R15C15A )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(C*(~B*(A*D))) K0::H0=(~A*~D) F1:F F0:F 4 MODE K1 w K0 v REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_758 SLICE R14C33A )
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! " # $ % & ' ( VMODE:LOGIC K1::H1=(C*(~B*(A*~D)+B*(~A*~D))) K0::H0=(~A*(C*~B)+A*(C*(~B*D))) F1:F F0:F 4 MODE K1 8 K0 7 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_661 SLICE R15C11C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(~D+(~A+B))+C*(~D*A+D*(A*B))) K0::H0=(B+D) F1:F F0:F 4 MODE K1 y K0 x REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_759 SLICE R18C30B )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(D*(~A*C)) K0::H0=(~B*C+B*(~A*(D+C)+A*C)) F1:F F0:F 4 MODE K1 : K0 9 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_662 SLICE R15C9C )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(~B*D+B*((A*~C)+D)) K0::H0=(B*D) F1:F F0:F 4 MODE K1 { K0 z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_760 SLICE R21C34A )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~B*~C+B*(~A*(~C*~D)+A*~C)) K0::H0=(~D*C+D*(~A*(C*~B)+A*C)) F1:F F0:F 4 MODE K1 < K0 ; REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_663 SLICE R18C14C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(((C*A)+D)+B) K0::H0=(~D*~C) F1:F F0:F 4 MODE K1 } K0 | REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_761 SLICE R17C36B )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=((C*B)*~A)*~D K0::H0=(~B*(~A*~D+A*(~D*~C))+B*(~A+~C)) F1:F F0:F 4 MODE K1 > K0 = REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_alu/SLICE_664 SLICE R11C19B )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~D*(B*A)+D*(~B*~C+B*(~C+A))) K0::H0=(B*C) F1:F F0:F 4 MODE K1 K0 ~ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_762 SLICE R15C31C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*~B+D*(~C*~B)) K0::H0=(~D*(~C*A+C*(B+A))+D*A) F1:F F0:F 4 MODE K1 @ K0 ? REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 'cpu0/dec_alu/SLICE_665 SLICE R9C19B )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~B*(~A*(D*C)+A*D)+B*D) K0::H0=(~B+(A+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 "cpu0/SLICE_763 SLICE R21C35C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~A*D+A*C)+B*(A*C)) K0::H0=(~B*(~D*C+D*A)) F1:F F0:F 4 MODE K1 B K0 A REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 0 NGID1 8cpu0/dec_alu/SLICE_666 SLICE R9C17A )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(A*(~C*(~B*~D))) K0::H0=(((~B+D)+C)+A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_764 SLICE R21C35B )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~D*(~C*B+C*A)+D*(C*A)) K0::H0=(~D*B+D*C) F1:F F0:F 4 MODE K1 D K0 C REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 2 NGID1 7cpu0/dec_alu/SLICE_667 SLICE R9C16A )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~C*(~B*(A*D))) K0::H0=(C*(~B*(~D*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_765 SLICE R16C28B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*~C)+A*(B*D)) K0::H0=(~D*~B+D*C) F1:F F0:F 4 MODE K1 F K0 E REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 3 NGID1 9cpu0/SLICE_668 SLICE R15C21A )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(D*(A*(B*C))) K0::H0=(A*(C*(~D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_766 SLICE R14C35D )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=((~D+(~B+C))+A) K0::H0=(~A*((~D+C)+B)+A*(~B+(~D+C))) F1:F F0:F 4 MODE K1 H K0 G REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 C NGID1 cpu0/dec_alu/SLICE_669 SLICE R11C14B )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*(B*A)+C*(~B*D+B*(D+A))) K0::H0=(~C*(~A*~B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_767 SLICE R18C36B )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~D*(~C*(B*~A))) K0::H0=(~C*B+C*((D*~A)+B)) F1:F F0:F 4 MODE K1 J K0 I REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 D NGID1 Jcpu0/dec_alu/SLICE_670 SLICE R11C21C )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~A*((B*~C)+D)+A*D) K0::H0=(A*(~B*~D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 \cpu0/dec_regs/SLICE_768 SLICE R8C28A )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~B*(C*D)+B*(~C*(A*D)+C*D)) K0::H0=(~B*(C*(A*D))) F1:F F0:F 4 MODE K1 L K0 K REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 I NGID1 \cpu0/dec_ea/SLICE_671 SLICE R21C13D )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(C*D*~B)*A K0::H0=(A*(D*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_769 SLICE R15C34D )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*~C+B*(~D*~C+D*(~A*~C))) K0::H0=(D*(C*(A*B))) F1:F F0:F 4 MODE K1 N K0 M REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 g NGID1 scpu0/SLICE_672 SLICE R18C12C )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(B*(~D*(A*C))) K0::H0=(D*(~B*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_770 SLICE R18C28A )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~A*(B*(D*C))) K0::H0=((B*(C*D))+A) F1:F F0:F 4 MODE K1 P K0 O REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_673 SLICE R22C12B )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~C*~A) K0::H0=(~C*(~D*(A*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_771 SLICE R16C33B )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~D*(~C*B)) K0::H0=(~D*(A*C)+D*(~B*(A*C)+B*(~A+C))) F1:F F0:F 4 MODE K1 R K0 Q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_674 SLICE R16C13A )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~A*B+A*(B*(~D+C))) K0::H0=(~C*(B*(~D*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_772 SLICE R19C35B )
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(((D+~C)*B)*A)+(((~D*~C)*B)*~A) K0::H0=(~B*~C+B*(~C+A)) F1:F F0:F 4 MODE K1 T K0 S REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 1 NGID2 cpu0/dec_op/SLICE_675 SLICE R12C14A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~C*D+C*((~B*A)+D)) K0::H0=(~C*(~B*(D*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_773 SLICE R15C32C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*((~D+A)+B)+C*(A+B)) K0::H0=(~C*(B*(D*~A))) F1:F F0:F 4 MODE K1 V K0 U REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_676 SLICE R12C17A )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~A*C+A*~D) K0::H0=(B*(C*(~A*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ncpu0/dec_regs/SLICE_774 SLICE R7C28B )
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(~C*(~B*~D+B*A)+C*(~B+A)) K0::H0=(~D*(~B+(~A+~C))+D*~C) F1:F F0:F 4 MODE K1 X K0 W REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_677 SLICE R12C18A )
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(~B*(~D*C+D*(C+A))+B*(~D*(C+A)+D*C)) K0::H0=(~C*(~D*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 wcpu0/dec_regs/SLICE_775 SLICE R17C29A )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*(A+B)+D*((A+B)+C)) K0::H0=(B*(~C*(D*A))) F1:F F0:F 4 MODE K1 Z K0 Y REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 xcpu0/dec_regs/SLICE_678 SLICE R21C14B )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(C*~B) K0::H0=(D*(B*(C*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_776 SLICE R19C32D )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*(~C*(A+D)+C*A)+B*A) K0::H0=(A*(~C*~B)) F1:F F0:F 4 MODE K1 \ K0 [ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_679 SLICE R19C11B )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(C+D) K0::H0=(~B*(~D*(A+C)+D*A)+B*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_777 SLICE R15C35C )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(~A*(~C+~D)+A*(~C*D))+B*(~A+D)) K0::H0=(D*(~B*~C)) F1:F F0:F 4 MODE K1 ^ K0 ] REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_680 SLICE R11C15B )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~B*D) K0::H0=(~C*~A+C*(~D*(~A*B)+D*~A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 |cpu0/dec_regs/SLICE_778 SLICE R15C33C )
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~C*(~A*(B+D)+A*B)+C*B) K0::H0=(~D*(~C*A+C*(B*A))+D*(~C*(~B*A))) F1:F F0:F 4 MODE K1 ` K0 _ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_681 SLICE R18C13A )
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! " # $ % & ' ( ^MODE:LOGIC K1::H1=(~D*(C+B)+D*((C+A)+B)) K0::H0=(~D*(~B*(C*~A)+B*~A)+D*(B*(~C*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_779 SLICE R15C33A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*A+D*(~C*A+C*(A+B))) K0::H0=(~A*(~D*(B*C))) F1:F F0:F 4 MODE K1 b K0 a REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_682 SLICE R14C17B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(B*(C*(~D*~A))) K0::H0=(D*(B*(C*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ]cpu0/dec_regs/SLICE_780 SLICE R7C27B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(D*(~C*(A*~B))) K0::H0=(~A*(C+D)+A*C) F1:F F0:F 4 MODE K1 d K0 c REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(((C+D)+A)+B) K0::H0=(~D*(~C*(B*A))+D*(B*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_781 SLICE R16C32A )
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NGID1 cpu0/dec_regs/SLICE_683 SLICE R18C15A )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~C*~D) K0::H0=(C*(A*(D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ~cpu0/dec_regs/SLICE_782 SLICE R16C33A )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~C*(A*B)+C*(~A*(B*~D)+A*B)) K0::H0=(~D*(A*(~C+B))) F1:F F0:F 4 MODE K1 f K0 e REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ,cpu0/SLICE_684 SLICE R17C10A )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~A*(B+D)+A*((B+C)+D)) K0::H0=(~C*(~A*(D+B)+A*D)+C*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_783 SLICE R15C30C )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~B*(~C*A+C*(A*D))+B*(C*(A*D))) K0::H0=(~B*~C+B*(A*(D*~C))) F1:F F0:F 4 MODE K1 h K0 g REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_685 SLICE R16C16C )
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! " # $ % & ' ( WMODE:LOGIC K1::H1=(~C+((~A+D)+B)) K0::H0=(~A*(~C*(~D*~B)+C*~B)+A*(C*(D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 )cpu0/SLICE_784 SLICE R18C34C )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(B*A*C)*D K0::H0=(((B*D)+A)+C) F1:F F0:F 4 MODE K1 j K0 i REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1 NGID2 cpu0/SLICE_686 SLICE R17C17D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~A*B) K0::H0=(~D*(B*(A*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ycpu0/dec_regs/SLICE_785 SLICE R15C31D )
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! " # $ % & ' ( hMODE:LOGIC K1::H1=(~A*(~B*~D+B*(~C+D))+A*(~B*~D+B*(C*~D))) K0::H0=(~B*(A*D)+B*(~A*C+A*(C+D))) F1:F F0:F 4 MODE K1 l K0 k REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 f NGID1 cpu0/dec_regs/SLICE_687 SLICE R11C15C )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*(B*A)+D*(~B*(A*~C)+B*A)) K0::H0=(~C*(~D*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 !cpu0/dec_regs/SLICE_786 SLICE R14C31D )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~(~B*A)*D*C)+((~B*A)*D) K0::H0=(~D*(A*B)+D*(~A*C+A*(B+C))) F1:F F0:F 4 MODE K1 n K0 m REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 NGID2 cpu0/SLICE_688 SLICE R15C12B )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~D*(~A*C)+D*(B*C)) K0::H0=(C*(~A*~D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 #cpu0/dec_regs/SLICE_787 SLICE R19C33A )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(A*(~C*B+C*(D*B))) K0::H0=(~D*A+D*(C*A)) F1:F F0:F 4 MODE K1 p K0 o REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_689 SLICE R17C16D )
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(~C*(~B*A+B*(~D+A))) K0::H0=(~A*(C*B)+A*(~D*(C*B)+D*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_788 SLICE R17C33B )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~D*((B+C)+A)+D*(B+C)) K0::H0=(A*(~C*(B*~D))) F1:F F0:F 4 MODE K1 r K0 q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Jcpu0/dec_regs/SLICE_690 SLICE R10C17C )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(A*~C) K0::H0=(~D*(A+C)+D*((A+B)+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_789 SLICE R17C34A )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=((~C+B)+D) K0::H0=(B*(D*(~C*A))) F1:F F0:F 4 MODE K1 t K0 s REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_691 SLICE R19C10C )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(((A+D)+B)+C) K0::H0=(~B*(~D*A+D*(C+A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_790 SLICE R17C34B )
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! " # $ % & ' ( WMODE:LOGIC K1::H1=(~C*(A*(D*B))+C*(~A*(D*B))) K0::H0=(~D*(~B*C+B*(A+C))+D*C) F1:F F0:F 4 MODE K1 v K0 u REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_692 SLICE R21C15D )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(B*(~C*(~A*~D)+C*~D)) K0::H0=(~D*(C*(~A*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_791 SLICE R17C35C )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(C*(A*(~D*B))) K0::H0=(~B*(~A*C+A*(D+C))+B*C) F1:F F0:F 4 MODE K1 x K0 w REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_693 SLICE R10C17A )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~A*(~C*(B+D)+C*B)) K0::H0=(~A*(C*(~B*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_792 SLICE R11C28A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(B*(A*~D))) K0::H0=(~B*(~C*D+C*(D+A))+B*D) F1:F F0:F 4 MODE K1 z K0 y REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_694 SLICE R10C16B )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~B*((C+D)+A)) K0::H0=(C*((~D+A)+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_793 SLICE R9C26B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*D+B*C) K0::H0=(A*(~B*(~C+~D)+B*~D)) F1:F F0:F 4 MODE K1 | K0 { REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_695 SLICE R21C10D )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~B*(~A*D)+B*(~A*D+A*C)) K0::H0=(~A*(~D+(~C+~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_794 SLICE R16C33C )
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! " # $ % & ' ( aMODE:LOGIC K1::H1=(~D*(~A*~C+A*(~C*~B))+D*(~A*~C+A*~B)) K0::H0=(~A*(~B*D+B*(D*C))+A*D) F1:F F0:F 4 MODE K1 ~ K0 } REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_696 SLICE R18C16B )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~B*(~A*D)+B*(C*(~A*D))) K0::H0=(((A+B)+C)+D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_795 SLICE R16C32C )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~D*((~C+~B)+A)+D*(~C+A)) K0::H0=(~A*~C+A*(~D*~C+D*(~C+~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_697 SLICE R22C14C )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~D*(~A*(~B*C))) K0::H0=(~B*(A*D)+B*(~A*C+A*(C+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_796 SLICE R17C32A )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*((B+C)+A)+D*(B+A)) K0::H0=(~D*A+D*((B*C)+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_698 SLICE R17C24D )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=((D+C)+A) K0::H0=((~C*A+C*(~B+A))+D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_797 SLICE R15C33D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*~D)) K0::H0=(~D*(A*(C*~B))+D*(C*~B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 < NGID2 NGID3 cpu0/SLICE_699 SLICE R12C17D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~B*(D*(~A*~C))) K0::H0=(A*((B*D)+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 Dcpu0/SLICE_798 SLICE R18C35C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A*(B*(D*C))) K0::H0=(~D*(A*(~C*B))+D*(~A*(C*B)+A*B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 A NGID3 Bcpu0/SLICE_700 SLICE R17C21A )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=((D*~B)*C)*~A K0::H0=(~D*(B+C)+D*((A+B)+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 NGID2 |cpu0/SLICE_799 SLICE R14C34D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*C+D*B) K0::H0=(~A*(~C*~B+C*(D*~B))+A*(~C*(~D*~B))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_701 SLICE R14C24B )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(A*~D) K0::H0=(~D*B+D*(~C*B+C*(~A+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 + NGID1 cpu0/SLICE_800 SLICE R19C34C )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~D*C+D*A) K0::H0=(~A*(D*(~B*~C))+A*(~D*(B*~C)+D*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_702 SLICE R14C22A )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=((~C*(B*A)+C*A)+D) K0::H0=(((A*~C)+B)+D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 - NGID1 cpu0/dec_regs/SLICE_801 SLICE R15C34C )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~D*B+D*C) K0::H0=(~C*(~A*B+A*(D*B))+C*(~A*(~D*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_703 SLICE R18C21C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*(C*~B)+D*C) K0::H0=(C*(~A*~B+A*(~D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1 Xcpu0/dec_regs/SLICE_802 SLICE R19C32A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~A+~C)+D*~C) K0::H0=(~B*(C*A)+B*((C*A)+D)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Q NGID1 NGID2 d NGID3 ecpu0/SLICE_704 SLICE R18C21A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(~D*B+D*(~C+B))+A*B) K0::H0=(~C*(B*(D*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 9 NGID1 cpu0/dec_regs/SLICE_803 SLICE R18C33A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*(C*A)) K0::H0=(~C*B+C*(~D*B+D*(B+A))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 b NGID3 ccpu0/regs/SLICE_705 SLICE R21C25A )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(C*(~B*(A*D))) K0::H0=(~D*(C+B)+D*(~A+(C+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 E NGID1 cpu0/dec_regs/SLICE_804 SLICE R18C33D )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~A*(D*B)+A*(~B+D)) K0::H0=(~C*(~A*(D*B)+A*B)+C*((~B+D)+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_706 SLICE R21C13C )
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! " # $ % & ' ( [MODE:LOGIC K1::H1=(~B*(C*~D)+B*(~C*~A+C*(~A+~D))) K0::H0=(~A*(C+B)+A*((~D+C)+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 F NGID1 icpu0/dec_regs/SLICE_805 SLICE R18C33C )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~A*(C+D)+A*((B+C)+D)) K0::H0=(~D*((B*~A)+C)+D*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_707 SLICE R14C9D )
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! " # $ % & ' ( VMODE:LOGIC K1::H1=(~D*(A*C)+D*(~A*B+A*(C+B))) K0::H0=(~B*(C+A)+B*((C+D)+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 G NGID1 kcpu0/SLICE_806 SLICE R15C29D )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~A*C+A*(B+C)) K0::H0=(~A*D+A*(~C*(D+B)+C*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_708 SLICE R19C9A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~D*(~C*A)+D*(A+C))+B*A) K0::H0=(~D*(C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 I NGID1
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(~B*~D+B*(~C*(~A*~D)+C*(A*~D))) K0::H0=(~D*(C*~A)+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Z NGID1 cpu0/alu/alu16/SLICE_709 SLICE R22C16A )
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cpu0/dec_regs/SLICE_807 SLICE R7C29C )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(~C*(A*~B)+C*(~A*(~D*~B)+A*~B)) K0::H0=(~D*(~C*(B*A)+C*B)+D*(B*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 i NGID1 pcpu0/alu/alu16/SLICE_710 SLICE R15C10B )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(B*((~A+D)+C)) K0::H0=(~C*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 N NGID1 Scpu0/dec_regs/SLICE_808 SLICE R8C29C )
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! " # $ % & ' ( VMODE:LOGIC K1::H1=(~B*(A*(~D*~C))+B*(A*~C)) K0::H0=(~D*(~A*C)+D*(~A*(B*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 o NGID1 rcpu0/alu/alu16/SLICE_711 SLICE R11C27A )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~B*~A+B*(~C*~A+C*(~D*~A))) K0::H0=(~D+C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 V NGID1 cpu0/dec_regs/SLICE_809 SLICE R14C34C )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~A*(~B*(~D*C))) K0::H0=(~D*A+D*(~B*A+B*(A+C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/a8/SLICE_712 SLICE R8C29B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~B*(~A*(D*~C))) K0::H0=(((D+A)+C)+B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 W NGID1 cpu0/dec_regs/SLICE_810 SLICE R8C29B )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(~D*C+D*A) K0::H0=(~A*(~D*(~B*C)+D*(B*~C))+A*(~D*(B*~C)+D*(~B*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/SLICE_713 SLICE R9C30D )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(A*(~C*(~B*D))) K0::H0=(~A*((C+B)+D)+A*(B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 d NGID1 cpu0/SLICE_811 SLICE R17C36D )
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! " # $ % & ' ( _MODE:LOGIC K1::H1=(~D*(A@C)+D*(~A*(C*~B))) K0::H0=(~B*(~C*(A*D))+B*(~C*(~D+A)+C*~D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 G NGID1 ocpu0/alu/alu8/SLICE_714 SLICE R9C28B )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(D*B)*~C*~A K0::H0=(~B*((D*~A)+C)+B*(D+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 NGID2 zcpu0/dec_regs/SLICE_812 SLICE R15C35A )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~B*(~D+C)+B*~D) K0::H0=(~B*(C@D)+B*(~C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 tcpu0/alu/alu8/SLICE_715 SLICE R8C26A )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~C+A) K0::H0=(~A*(C+D)+A*((C+D)+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 g NGID1 cpu0/dec_regs/SLICE_813 SLICE R17C35D )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(C*(D+A)) K0::H0=((~A*B+A*(D+B))+C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 g NGID1 pcpu0/alu/alu8/SLICE_716 SLICE R8C30B )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*D+B*(~C*(A+D)+C*D)) K0::H0=(((B*D)+A)+C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 h NGID1 cpu0/dec_regs/SLICE_814 SLICE R9C28C )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(((C+D)+A)+B) K0::H0=(~D*(C+A)+D*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 m NGID1 xcpu0/SLICE_717 SLICE R19C10B )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(A*D) K0::H0=(~C*B+C*(~D*(A+B)+D*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 v NGID1 cpu0/dec_regs/SLICE_815 SLICE R16C36D )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(D*(~B+C)) K0::H0=(~B*(A*D)+B*(~C*(A*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_718 SLICE R16C10A )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(D*C) K0::H0=((~C*A+C*(~B+A))+D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 cpu0/dec_regs/SLICE_816 SLICE R16C36C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(C*(~B*(A*~D))) K0::H0=(~D*C+D*((~B*A)+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 textctrl/SLICE_719 SLICE R16C15A )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~B+~(D*A))*C K0::H0=(~A*(~B*D+B*(~C*D))+A*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 NGID2 ucpu0/dec_regs/SLICE_817 SLICE R14C30D )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(D*(C*(B*~A))) K0::H0=(~A*(D*B)+A*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(B*(C*D)) K0::H0=(~B*(~D*(~A*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_818 SLICE R8C27D )
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( NGID1
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~A*D) K0::H0=(~B*(~A*D)+B*(C*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_819 SLICE R16C33D )
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textctrl/SLICE_720 SLICE R17C15A )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=((D*A)*~B)*C K0::H0=(~D*(A*(B*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 ucpu0/SLICE_820 SLICE R15C36A )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(D*(C*(B*A))) K0::H0=(((~D*~A)+C)+B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' (
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) NGID1
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(B*(D*~C)) K0::H0=(~B*(~C*~D+C*(~A*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 7cpu0/dec_regs/SLICE_822 SLICE R18C32A )
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textctrl/SLICE_721 SLICE R23C8C )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(C*(B*(D*A))) K0::H0=(~D*(~C*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_823 SLICE R12C29C )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(((C+A)+B)+D) K0::H0=(D*(~A*(~B*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( @MODE:LOGIC K1::H1=((D*C)*A)*B K0::H0=(~D*(~A*(~B*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_824 SLICE R15C29B )
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- NGID1
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(B*(A*(D*~C))) K0::H0=(B*(C*(A*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_825 SLICE R14C34A )
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textctrl/SLICE_722 SLICE R23C10C )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(C*~A) K0::H0=(~B*(~D*(C+A))+B*(~D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_826 SLICE R11C30B )
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! " # $ % & ' (
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~C*(~A*~D+A*(~D+~B))) K0::H0=((~A+B)+D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_827 SLICE R8C27B )
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. NGID1
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~A*~D+A*(~B*~D+B*(~D+C))) K0::H0=(B*(D*(A*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_828 SLICE R16C29C )
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textctrl/SLICE_723 SLICE R23C10B )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(D*(C*(~B*A))) K0::H0=(C*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_829 SLICE R16C27C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~C*A+C*(~D*A+D*(A*B))) K0::H0=(~D*(~B*(~A*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~B*(D*(~A*~C))) K0::H0=(B*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_830 SLICE R19C28A )
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NGID1
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=((D*(~C*~A))+B) K0::H0=(~C+~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_831 SLICE R14C28B )
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textctrl/SLICE_724 SLICE R23C9C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A+((~D+C)+B)) K0::H0=(D*A) F1:F F0:F 4 MODE K1 K0
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(((~B+C)+D)+A) K0::H0=(~B*(D*(~A*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_832 SLICE R18C35B )
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NGID1
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~D*(~C*(~A+~B))+D*(~A+~B)) K0::H0=(~C*B) F1:F F0:F 4 MODE K1
K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 _cpu0/regs/ea/SLICE_833 SLICE R21C20C )
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textctrl/SLICE_725 SLICE R22C9A )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~C*(B*A)+C*(~B*D+B*(D+A))) K0::H0=(C*(A*(~B*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 f NGID1 cpu0/regs/ea/SLICE_834 SLICE R22C17B )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(C*(A*(D*B))) K0::H0=(~A*(C*(B*D))+A*(~C*~D+C*(~D+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' (
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NGID1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(~A*C)+D*(C+A)) K0::H0=(~B*A+B*(~D*A+D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 h NGID1 cpu0/regs/ea/SLICE_836 SLICE R16C24C )
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textctrl/SLICE_726 SLICE R23C8D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~A*C)+B*(C+A)) K0::H0=(~C*B+C*(~D*B+D*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 i NGID1 cpu0/regs/SLICE_837 SLICE R16C23C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~A*(~B*(~D*~C))) K0::H0=(~C*(A*D)+C*(~D+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(~C*B)+A*(B+C)) K0::H0=(~B*A+B*(~D*A+D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 j NGID1 cpu0/regs/SLICE_838 SLICE R16C23D )
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NGID1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(~C*A)+D*(A+C)) K0::H0=(~A*B+A*(~C*B+C*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 cpu0/regs/ea/SLICE_839 SLICE R21C25C )
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textctrl/SLICE_727 SLICE R24C11C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(~B*C)+A*(C+B)) K0::H0=(~C*D+C*(~A*D+A*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 l NGID1 cpu0/regs/ea/SLICE_840 SLICE R19C25A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(A*(B*C)) K0::H0=(~D*~B+D*(~B*(~A*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(~D*A)+C*(A+D)) K0::H0=(~D*A+D*(~B*A+B*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 m NGID1 cpu0/regs/SLICE_841 SLICE R23C22C )
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NGID1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(~A*C)+D*(C+A)) K0::H0=(~B*D+B*(~A*D+A*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 n NGID1 cpu0/regs/ea/SLICE_842 SLICE R21C17D )
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textctrl/SLICE_728 SLICE R19C8B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=((~A*C+A*(C+B))+D) K0::H0=(A*(D*(C*B))) F1:F F0:F 4 MODE K1 ! K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 o NGID1 cpu0/regs/ea/SLICE_843 SLICE R21C19B )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~B+(~C+(~A+D))) K0::H0=(C+A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*(A+C)+B*((A+C)+D)) K0::H0=(~D*(A*(C*B))) F1:F F0:F 4 MODE K1 # K0 " REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 p NGID1 cpu0/regs/ea/SLICE_844 SLICE R22C17A )
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NGID1
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! " # $ % & ' ( FMODE:LOGIC K1::H1=((~D*C+D*(C+A))+B) K0::H0=(~A*(D*(~C*B))) F1:F F0:F 4 MODE K1 % K0 $ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 q NGID1 cpu0/regs/ea/SLICE_845 SLICE R21C18A )
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textctrl/SLICE_729 SLICE R23C10D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*(C+B)+D*((C+B)+A)) K0::H0=(~D*(C*(A*B))) F1:F F0:F 4 MODE K1 ' K0 & REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 t NGID1 cpu0/regs/ea/SLICE_846 SLICE R21C18D )
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! " # $ % & ' ( 7MODE:LOGIC K1::H1=(B*(C*(D*A))) K0::H0=(C*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( FMODE:LOGIC K1::H1=((~A*B+A*(B+C))+D) K0::H0=(~D*(C*(~B*A))) F1:F F0:F 4 MODE K1 ) K0 ( REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 u NGID1 cpu0/regs/ea/SLICE_847 SLICE R19C16D )
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NGID1
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(~D*(~C*(~B+A)+C*~B)+D*((~B+A)+C)) K0::H0=(~A*(C*(D*B))) F1:F F0:F 4 MODE K1 + K0 * REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 v NGID1 cpu0/regs/ea/SLICE_848 SLICE R15C28B )
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textctrl/SLICE_730 SLICE R23C6D )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(B*(~A*(D*C))) K0::H0=(~A*(~B*C)) F1:F F0:F 4 MODE K1 - K0 , REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 w NGID1 "cpu0/regs/SLICE_849 SLICE R14C23B )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(C*(D*A)) K0::H0=(D*((B+A)+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(A*(B*(~C*~D))) K0::H0=(~D*(~A*(C*B)+A*(~C+B))+D*B) F1:F F0:F 4 MODE K1 / K0 . REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 x NGID1 fcpu0/regs/ea/SLICE_850 SLICE R22C18D )
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NGID1
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~B*(D*~C)) K0::H0=(C*(A*(~D+B))) F1:F F0:F 4 MODE K1 1 K0 0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 } NGID1 ,cpu0/regs/ea/SLICE_851 SLICE R21C17C )
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textctrl/SLICE_731 SLICE R23C7A )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(C*(A*~D)) K0::H0=(~C*B+C*(~D*B+D*A)) F1:F F0:F 4 MODE K1 3 K0 2 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ~ NGID1 /cpu0/regs/ea/SLICE_852 SLICE R21C18C )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~A*(~D*(B*C))) K0::H0=(A*(D*(~B*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( VMODE:LOGIC K1::H1=(~C*(~B*(D@~A)+B*~D)+C*(~B*A)) K0::H0=(~D*C+D*(~A*C+A*B)) F1:F F0:F 4 MODE K1 5 K0 4 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_853 SLICE R16C26A )
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NGID1
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~A*(~C*D+C*(~B+D))+A*(~B+D)) K0::H0=(~B*A+B*(A+D)) F1:F F0:F 4 MODE K1 7 K0 6 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_854 SLICE R12C23A )
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textctrl/SLICE_732 SLICE R22C9B )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~A*(C*B)+A*(~C*D+C*(D+B))) K0::H0=(~C*D+C*(D+B)) F1:F F0:F 4 MODE K1 9 K0 8 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_855 SLICE R12C25B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~B*(A*(C*D))) K0::H0=(~D*(~A*(B*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~B*(D*A)+B*(~D*C+D*(C+A))) K0::H0=(~B*C+B*(C+A)) F1:F F0:F 4 MODE K1 ; K0 : REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_856 SLICE R12C24C )
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NGID1
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~D*(C*B)+D*(~C*A+C*(A+B))) K0::H0=(~D*C+D*(C+A)) F1:F F0:F 4 MODE K1 = K0 < REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_857 SLICE R12C23B )
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textctrl/SLICE_733 SLICE R23C9D )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~D*(C*A)+D*(~C*B+C*(B+A))) K0::H0=(~D*C+D*(C+A)) F1:F F0:F 4 MODE K1 ? K0 > REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_858 SLICE R9C16B )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(~B*D) K0::H0=(((A+C)+B)+D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*C+B*D) K0::H0=(~D*(~A*B)+D*(~A*B+A*C)) F1:F F0:F 4 MODE K1 A K0 @ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 vcpu0/regs/SLICE_859 SLICE R15C26C )
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NGID1
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(~C*~D+C*(~D+(A*~B))) K0::H0=(~A*(C*B)+A*(~C*D+C*(D+B))) F1:F F0:F 4 MODE K1 C K0 B REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_860 SLICE R18C22C )
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textctrl/SLICE_734 SLICE R23C10A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(~B*C)+A*(C+B)) K0::H0=(~D*(A*C)+D*(~A+C)) F1:F F0:F 4 MODE K1 E K0 D REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_861 SLICE R21C25A )
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! " # $ % & ' (
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(A*~D)+C*(D+A)) K0::H0=(~C*(~D*B)+C*(B+D)) F1:F F0:F 4 MODE K1 G K0 F REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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NGID1
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cpu0/regs/SLICE_862 SLICE R16C14A )
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textctrl/SLICE_735 SLICE R22C9C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*(~B+C)+D*A) K0::H0=(~B*(~C*~D)+B*(~D+C)) F1:F F0:F 4 MODE K1 I K0 H REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_863 SLICE R11C24D )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~C*~B) K0::H0=(~D*(~A*(B*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(~D*(B*~C)+D*(C+B)) K0::H0=(~C*(~B*A)+C*(~D+(~B*A))) F1:F F0:F 4 MODE K1 K K0 J REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_864 SLICE R19C16C )
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NGID1
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! " # $ % & ' ( `MODE:LOGIC K1::H1=((~D*(~C+~B)+D*(~C*B))+A) K0::H0=(~A*(~D*(~C+B)+D*~C)+A*((~C+B)+D)) F1:F F0:F 4 MODE K1 M K0 L REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 %cpu0/SLICE_865 SLICE R17C24A )
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textctrl/SLICE_736 SLICE R23C7C )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(D*C)+B*(~D*A+D*(C+A))) K0::H0=(~D*(C*~B)+D*(B+C)) F1:F F0:F 4 MODE K1 O K0 N REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_866 SLICE R22C16D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*(~D*~B+D*(~A*~B))+C*~B) K0::H0=((C+B)+A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' (
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NGID1
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~D*(C*~A)) K0::H0=(A*(~C*(D*B)+C*B)) F1:F F0:F 4 MODE K1 S K0 R REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 1cpu0/regs/ea/SLICE_868 SLICE R21C17B )
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cpu0/SLICE_737 SLICE R16C8A )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(C*D*~B)*A K0::H0=(~A*(D+C)+A*((D+C)+B)) F1:F F0:F 4 MODE K1 U K0 T REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 r NGID2 cpu0/regs/ea/SLICE_869 SLICE R22C18B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~C*(B*~D))) K0::H0=(~C*(~A*(D*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 [cpu0/SLICE_738 SLICE R16C15C )
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! " # $ % & ' (
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(C*(D*(~A*~B))) K0::H0=(D*(~C*(B*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_739 SLICE R17C9B )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=((C*D)*~B)*A K0::H0=(~C*(A*D)+C*(~A*B+A*(B+D))) F1:F F0:F 4 MODE K1 Y K0 X REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 e NGID2 5cpu0/regs/SLICE_871 SLICE R18C26D )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(D+C) K0::H0=(B*(~C*(A*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_740 SLICE R16C14B )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(B*~C) K0::H0=(~C*(~A*(~B*D))+C*~B) F1:F F0:F 4 MODE K1 [ K0 Z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ( NGID1 vcpu0/SLICE_872 SLICE R9C24A )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*C) K0::H0=(C*(D*(B*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_741 SLICE R15C10A )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~A*(~B*C)+A*(~B*C+B*D)) K0::H0=(~C*(~D*(~A*B)+D*(B+A))+C*B) F1:F F0:F 4 MODE K1 ] K0 \ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ; NGID1 cpu0/regs/SLICE_873 SLICE R23C23B )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*(~B*(~C*~A))) K0::H0=(~D*(B*C)+D*(~A*(B*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_742 SLICE R17C14D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(~B*C)+D*(C+B)) K0::H0=(~C*B+C*(~A*B+A*D)) F1:F F0:F 4 MODE K1 _ K0 ^ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_874 SLICE R18C25D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(((C+D)+A)+B) K0::H0=(~C*(~D*(B*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ?cpu0/SLICE_743 SLICE R15C15D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*B)+C*(~A*(D*B)+A*B)) K0::H0=(~C*(~B*(A*D)+B*D)+C*D) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 a K0 ` REG1 c REG0 b Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 . NGID3 /cpu0/regs/SLICE_875 SLICE R18C25A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(D*(B*(A*C))) K0::H0=(~A*(D*(~B*~C))+A*(D*~B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_744 SLICE R17C14B )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~C*(D*(A*~B))+C*(D*A)) K0::H0=(((A*~C)+D)+B) F1:F F0:F 4 MODE K1 e K0 d REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_876 SLICE R19C31A )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~(D+A)*B)*C K0::H0=(~D*(A*~C)+D*(A*(~B*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(((B*C)+A)+D) K0::H0=(C*(A*(D*~B))) F1:F F0:F 4 MODE K1 g K0 f REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_877 SLICE R21C34B )
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NGID2 cpu0/SLICE_745 SLICE R15C16A )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(D*(C*~B)) K0::H0=(D*(A*(~B*~C))) F1:F F0:F 4 MODE K1 i K0 h REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_878 SLICE R21C31C )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~B*(~A*(D+C)+A*D)+B*D) K0::H0=(D*(B*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_746 SLICE R16C10D )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(((A+D)+B)+C) K0::H0=(~C*(~A*D)) F1:F F0:F 4 MODE K1 k K0 j REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_879 SLICE R19C34D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(D*(A*(B*~C))) K0::H0=(~C*(~A*D)+C*(B*(~A*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_747 SLICE R15C15B )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~D*(~C*(B*A))) K0::H0=(~A*(~B*D)) F1:F F0:F 4 MODE K1 m K0 l REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_880 SLICE R16C30C )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~A*(~B*~C)) K0::H0=(A*(B*(C*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_748 SLICE R16C14D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*B+C*(B+D)) K0::H0=(~A*(~D*(~B*~C))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 o K0 n REG1 q REG0 p Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/regs/SLICE_881 SLICE R16C25B )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=((D*B)*~A)*C K0::H0=(B*(~D*~A+D*(~A*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/test_cond/SLICE_749 SLICE R15C9A )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~A*(C*(~D*~B))) K0::H0=(~B*(~D*(~A*~C))) F1:F F0:F 4 MODE K1 s K0 r REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_882 SLICE R16C28D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(B*(~A*(~D*C))) K0::H0=(~A*(~C*(~B*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_750 SLICE R16C9A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(D*(A*~C))) K0::H0=(~B*(~A*(~C*D))) F1:F F0:F 4 MODE K1 u K0 t REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_883 SLICE R17C30A )
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! " # $ % & ' ( 7MODE:LOGIC K1::H1=((A+C)+D) K0::H0=((A+D)+B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_751 SLICE R15C9B )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(~C*(D*A)+C*A)+B*A) K0::H0=(~C*A+C*(~D*(A+B)+D*A)) F1:F F0:F 4 MODE K1 w K0 v REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 0cpu0/regs/SLICE_884 SLICE R18C25B )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(((A+C)+B)+D) K0::H0=(A*(~C*(B*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_752 SLICE R17C11C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(B+D) K0::H0=(~C*(B*(~A*D))) F1:F F0:F 4 MODE K1 y K0 x REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 tcpu0/regs/SLICE_885 SLICE R19C26B )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~B*C+B*((~D*A)+C)) K0::H0=(~C*A+C*(D+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_753 SLICE R15C11D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~A*B+A*D) K0::H0=(~D*(~B*(A*~C)+B*~C)+D*~C) F1:F F0:F 4 MODE K1 { K0 z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_886 SLICE R21C34C )
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(~C*(~D*B+D*(~A*B))+C*(~D*(A*B))) K0::H0=(A*(~C*(B*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_754 SLICE R14C18D )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(((A+C)+B)+D) K0::H0=(C*(D*(A*~B))) F1:F F0:F 4 MODE K1 } K0 | REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 /cpu0/regs/SLICE_887 SLICE R19C25D )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~D*(~B*~A)) K0::H0=(D*(~C*B+C*(A*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_755 SLICE R15C14C )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(~B*D+B*C) K0::H0=(D*(~C*(B*A))) F1:F F0:F 4 MODE K1 K0 ~ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_888 SLICE R22C34A )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(C*(A*(~D*~B))) K0::H0=(A*(D*(~B+~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_756 SLICE R15C10C )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~B*(~A*C)) K0::H0=(~C*(A*B)+C*((A*B)+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_889 SLICE R12C21A )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(C+D) K0::H0=(A*(~C*(~B*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_757 SLICE R19C14A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(B*C)+A*(~C+B)) K0::H0=(~A*(~D*C+D*B)+A*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 wcpu0/regs/SLICE_890 SLICE R11C20D )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(A*B) K0::H0=(C*(~B*~A+B*(~D*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_758 SLICE R10C20B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(B*D)+C*(~D+B)) K0::H0=(~A*(~B*D+B*C)+A*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 # NGID1 ucpu0/regs/SLICE_891 SLICE R14C20D )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~D*(~C*A)+D*(A+C)) K0::H0=(~D*(~C*(B*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_759 SLICE R9C20B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(B*A)+C*(~A+B)) K0::H0=(~B*(~A*D+A*C)+B*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 qcpu0/regs/SLICE_892 SLICE R9C19C )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~B*(~D*C)+B*(C+D)) K0::H0=(~D*(~C*(~B*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_760 SLICE R9C20A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(B*D)+C*(~D+B)) K0::H0=(~D*(~A*C+A*B)+D*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 & NGID1 ocpu0/regs/SLICE_893 SLICE R16C20A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*(~A*C)+B*(C+A)) K0::H0=(~C*(~A*(D*B))) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(C*B)+A*(~B+C)) K0::H0=(~C*(~B*D+B*A)+C*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ' NGID1 mcpu0/regs/SLICE_894 SLICE R16C21B )
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K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_761 SLICE R17C12D )
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! " # $ % & ' ( hMODE:LOGIC K1::H1=(~C*(~B*(D*~A)+B*(D*A))+C*(~B*(~D+~A)+B*(~D+A))) K0::H0=(~A*(~B*D+B*C)+A*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ( NGID1 kcpu0/regs/SLICE_895 SLICE R10C23B )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(D*(~B*(C*A))) K0::H0=(C*(~D*~A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/test_cond/SLICE_762 SLICE R14C15B )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=((D+A)*C)+((D+(A*B))*~C) K0::H0=(~B*~D+B*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_896 SLICE R10C20B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*~B) K0::H0=(B*(C*(A*D))) F1:F F0:F 4 MODE K1 K0
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_763 SLICE R21C14D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*C)+A*(C+B)) K0::H0=(~D*~C+D*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_897 SLICE R9C18D )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(B+A) K0::H0=(~B*(~A+C)+B*(~A*D+A*(C*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_764 SLICE R21C18A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~A*D)+B*(D+A)) K0::H0=(~D*~C+D*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_898 SLICE R12C20D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~D*(A*(B*C))) K0::H0=(~D*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_765 SLICE R15C8A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~A*D)+B*(D+A)) K0::H0=(~D*~C+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_899 SLICE R10C17D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~A*(B*(~C*~D))) K0::H0=(D+B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 {cpu0/SLICE_766 SLICE R16C12A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~D*C)+A*(C+D)) K0::H0=(~D*~C+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_900 SLICE R8C18A )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=((B*(C*D))+A) K0::H0=(A*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_767 SLICE R16C13D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*D)+A*(D+B)) K0::H0=(~B*~D+B*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_901 SLICE R10C17B )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~A*(~C*(D*B))) K0::H0=(((A+C)+D)+B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_768 SLICE R16C9B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~C*(~B*D)+C*(D+B)) K0::H0=(~D*~C+D*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_902 SLICE R12C18B )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(C*(~A*(~D*B)+A*B)) K0::H0=(((D+C)+A)+B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 xcpu0/dec_alu/SLICE_769 SLICE R11C21D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*D)+A*(D+B)) K0::H0=(~A*~C+A*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_903 SLICE R11C23D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B+C) K0::H0=(~C*(~B*(A*~D)+B*~A)+C*(B*~A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Qcpu0/SLICE_770 SLICE R12C20A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=((D+~B)*A)+((D+(~B*C))*~A) K0::H0=(~B*~C+B*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_904 SLICE R9C18C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*~D+B*(~D*~A+D*(C*~A))) K0::H0=(C*(A*(D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 cpu0/dec_alu/SLICE_771 SLICE R10C20D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~A*C)+B*(C+A)) K0::H0=(~C*~A+C*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_905 SLICE R9C17C )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(C*~(A+B))*D K0::H0=(~B+(~C+(~A+~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 # NGID1 4 NGID2 cpu0/SLICE_772 SLICE R15C24D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~C*B)+A*(B+C)) K0::H0=(~D*~C+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_906 SLICE R12C18A )
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! " # $ % & ' ( fMODE:LOGIC K1::H1=((((A*D)*B)+(~D*~B))*C)+((~D*~B)*~C) K0::H0=(~D*(~A+(~B+C))+D*((~B+C)+A)) F1:F F0:F 4 MODE K1 " K0 ! REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 $ NGID1 = NGID2
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~D*C)+A*(C+D)) K0::H0=(~D*~B+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_907 SLICE R12C18C )
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cpu0/SLICE_773 SLICE R12C19C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~C*(~A*D)+C*(D+A)) K0::H0=(~D*~C+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_908 SLICE R9C20B )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(C*(D*(A*B))) K0::H0=(~D*C+D*(~A*(B+C))) F1:F F0:F 4 MODE K1 $ K0 # REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ) NGID1 cpu0/SLICE_774 SLICE R11C17C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~C*D)+B*(D+C)) K0::H0=(~A*~C+A*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_909 SLICE R12C17B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~B*((~D*~A)+C)) K0::H0=(((C*A)+B)+D) F1:F F0:F 4 MODE K1 & K0 % REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 5 NGID1 cpu0/dec_alu/SLICE_775 SLICE R10C20C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(~A*~C+A*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_910 SLICE R12C19A )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~A*(D*(~C*B))) K0::H0=(~C*D+C*A) F1:F F0:F 4 MODE K1 ( K0 ' REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 6 NGID1 Gcpu0/dec_alu/SLICE_776 SLICE R10C17D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~C*D)+B*(D+C)) K0::H0=(~A*~D+A*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_911 SLICE R10C20D )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(~C*(~B*(~A+D)+B*(~A+~D))+C*(B@(A*D))) K0::H0=(D*~C) F1:F F0:F 4 MODE K1 * K0 ) REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 < NGID1 Acpu0/dec_alu/SLICE_777 SLICE R9C16C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*C)+A*(C+B)) K0::H0=(~B*~C+B*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 $cpu0/regs/SLICE_912 SLICE R8C19B )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(~B*(~D*~C)) K0::H0=(~A*~C+A*~D) F1:F F0:F 4 MODE K1 , K0 + REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 E NGID1 Mcpu0/SLICE_778 SLICE R11C19D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~C*(~D*B)+C*(B+D)) K0::H0=(~D*~C+D*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 &cpu0/regs/SLICE_913 SLICE R10C21A )
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! " # $ % & ' ( 7MODE:LOGIC K1::H1=(B*(A*(D*C))) K0::H0=(A*C) F1:F F0:F 4 MODE K1 . K0 - REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 F NGID1 cpu0/SLICE_779 SLICE R11C19C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~C*(~B*D)+C*(D+B)) K0::H0=(~C*~D+C*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 +cpu0/regs/SLICE_914 SLICE R12C19D )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(B*(~C*(D*A))) K0::H0=(~D*(~A*C)) F1:F F0:F 4 MODE K1 0 K0 / REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 H NGID1 cpu0/SLICE_780 SLICE R14C19D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~A*D)+B*(D+A)) K0::H0=(~D*~C+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 /cpu0/regs/SLICE_915 SLICE R8C19C )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~D*(~A*(C*B))) K0::H0=(C*~A) F1:F F0:F 4 MODE K1 2 K0 1 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 S NGID1 cpu0/SLICE_781 SLICE R10C18C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~D*C)+A*(C+D)) K0::H0=(~D*~C+D*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 3cpu0/regs/SLICE_916 SLICE R10C21C )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(~D*(B*(A*C))) K0::H0=(D*B) F1:F F0:F 4 MODE K1 4 K0 3 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 T NGID1 cpu0/SLICE_782 SLICE R15C12A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*D)+A*(D+B)) K0::H0=(~B*~C+B*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 7cpu0/regs/SLICE_917 SLICE R8C20B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~C*(~D+~A))+B*(~C*~D)) K0::H0=(~A*(C*~D)) F1:F F0:F 4 MODE K1 6 K0 5 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _ NGID1 cpu0/SLICE_783 SLICE R22C14A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~C*B)+A*(B+C)) K0::H0=(~A*~C+A*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 :cpu0/regs/SLICE_918 SLICE R9C23A )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=((~A*(D*B))+C) K0::H0=(C*(A*(B*~D))) F1:F F0:F 4 MODE K1 8 K0 7 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 b NGID1 gcpu0/SLICE_784 SLICE R19C13C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~A*D)+B*(D+A)) K0::H0=(~A*~D+A*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 >cpu0/regs/SLICE_919 SLICE R11C20C )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=((~B*A+B*(~D+A))+C) K0::H0=(~A*(~B*C)) F1:F F0:F 4 MODE K1 : K0 9 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 c NGID1 cpu0/dec_ea/SLICE_785 SLICE R22C12C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~D*(~A*C)+D*(C+A)) K0::H0=(~A*~C+A*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 %cpu0/regs/SLICE_920 SLICE R8C20C )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=((~B*~A)*C)*D K0::H0=(B*(C*(~A+D))) F1:F F0:F 4 MODE K1 < K0 ; REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 d NGID1 ` NGID2 cpu0/dec_ea/SLICE_786 SLICE R22C13C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~C*D)+B*(D+C)) K0::H0=(~D*~C+D*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 'cpu0/regs/SLICE_921 SLICE R9C24B )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(~C*((A*B)+D)+C*D) K0::H0=(~A*~C+A*(~B*(~C*D)+B*~C)) F1:F F0:F 4 MODE K1 > K0 = REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 cpu0/SLICE_787 SLICE R22C14D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~A*C)+B*(C+A)) K0::H0=(~D*~C+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 *cpu0/regs/SLICE_922 SLICE R12C20B )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~A*(D*C)+A*B) K0::H0=(~C*(A*B)+C*(~D*(A*B)+D*B)) F1:F F0:F 4 MODE K1 @ K0 ? REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 f NGID1 pcpu0/SLICE_788 SLICE R21C17B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*C)+A*(C+B)) K0::H0=(~A*~C+A*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 .cpu0/regs/SLICE_923 SLICE R9C19A )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(B*(~A*~C)) K0::H0=(~D*(~B*(C*A))) F1:F F0:F 4 MODE K1 B K0 A REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 h NGID1 cpu0/SLICE_789 SLICE R17C15D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~D*C)+A*(C+D)) K0::H0=(~A*~D+A*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 2cpu0/regs/SLICE_924 SLICE R12C19B )
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! " # $ % & ' ( WMODE:LOGIC K1::H1=(~D*(B*A)+D*(~B*(~C*A)+B*A)) K0::H0=(~C*((D+B)+A)+C*(D+B)) F1:F F0:F 4 MODE K1 D K0 C REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 i NGID1 9cpu0/SLICE_790 SLICE R17C13B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~C*D)+B*(D+C)) K0::H0=(~D*~C+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 6cpu0/regs/SLICE_925 SLICE R6C20A )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(((C+D)+A)+B) K0::H0=(~B*(C*(A*D))) F1:F F0:F 4 MODE K1 F K0 E REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 4cpu0/SLICE_791 SLICE R21C11D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(~A*~D+A*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ;cpu0/regs/SLICE_926 SLICE R9C20C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(D*(B*~C))+A*~C) K0::H0=(B*(~C*A+C*(D*A))) F1:F F0:F 4 MODE K1 H K0 G REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 l NGID1 cpu0/SLICE_792 SLICE R18C14B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~D*(~A*C)+D*(C+A)) K0::H0=(~D*~C+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ?cpu0/regs/SLICE_927 SLICE R10C20C )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(~B*C)*D*A K0::H0=(C*(~B*(D+A))) F1:F F0:F 4 MODE K1 J K0 I REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 n NGID1 NGID2 cpu0/dec_ea/SLICE_793 SLICE R19C13B )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(C*(~D*(~A*~B))) K0::H0=(~B*(D*C)+B*(~C+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 O NGID1 cpu0/regs/SLICE_928 SLICE R9C20A )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(B*~D)*A*~C K0::H0=(~B*(~A+(~D+C))+B*(~D+C)) F1:F F0:F 4 MODE K1 L K0 K REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 o NGID1 a NGID2 cpu0/SLICE_794 SLICE R15C18D )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~A*(D*(~C*~B))) K0::H0=(~C*(D*B)+C*(~B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 P NGID1 cpu0/SLICE_929 SLICE R18C22D )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~C*D+C*(~D*(~A*~B)+D*(~B+A))) K0::H0=(D*(~B+(~A+C))) F1:F F0:F 4 MODE K1 N K0 M REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 p NGID1 cpu0/SLICE_795 SLICE R16C13C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(C*(~B*~D)) K0::H0=(~D*(~A*(B*~C)+A*(B*C))+D*(~A*(~B+~C)+A*(~B+C))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 j NGID1 b NGID2 & NGID3 'cpu0/regs/SLICE_930 SLICE R17C20B )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~D*(B*C)+D*C) K0::H0=(~C*(A*B)+C*(~A*B)) F1:F F0:F 4 MODE K1 P K0 O REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 q NGID1 cpu0/SLICE_796 SLICE R15C13D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(A*(~D*C)) K0::H0=(~B*(C*D)+B*(~D+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 l NGID1 ccpu0/SLICE_931 SLICE R21C22C )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=((~B*~D)*C)*A K0::H0=(~D*C+D*(~B*(C*~A)+B*C)) F1:F F0:F 4 MODE K1 R K0 Q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 r NGID1 NGID2 cpu0/SLICE_797 SLICE R19C14C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(A*D)+B*(~A*C+A*(C+D))) K0::H0=(~B*(D*A)+B*((D*A)+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 { NGID1 NGID2 7 NGID3 8cpu0/SLICE_932 SLICE R19C22A )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=((~C*D+C*(A+D))+B) K0::H0=((A*C)+B) F1:F F0:F 4 MODE K1 T K0 S REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 t NGID1 cpu0/SLICE_798 SLICE R21C12B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*B)+C*(~A*D+A*(D+B))) K0::H0=(~A*(C*B)+A*((C*B)+D)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 NGID2 ? NGID3 @cpu0/SLICE_933 SLICE R19C22C )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~(A+D)*~B)*~C K0::H0=(~B*(C*D)+B*(C*(D*~A))) F1:F F0:F 4 MODE K1 V K0 U REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 u NGID1 NGID2 ~cpu0/SLICE_799 SLICE R17C15B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*C)+A*(~D*B+D*(B+C))) K0::H0=(~A*(B*C)+A*((B*C)+D)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 } NGID1 NGID2 ; NGID3
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(A*(C*(~D*B))) K0::H0=(~C*D) F1:F F0:F 4 MODE K1 X K0 W REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 v NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(A*D)+B*(~A*C+A*(C+D))) K0::H0=(~A*(D*C)+A*((D*C)+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ~ NGID1 NGID2 ( NGID3 )cpu0/SLICE_935 SLICE R19C21C )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~D*(B*C)+D*(~B*A+B*(C+A))) K0::H0=(~A*C+A*(C+D)) F1:F F0:F 4 MODE K1 Z K0 Y REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 w NGID1 }cpu0/dec_ea/SLICE_801 SLICE R21C13B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*D)+B*(~C*A+C*(A+D))) K0::H0=(~D*(B*A)+D*((B*A)+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 3 NGID3 4cpu0/SLICE_936 SLICE R19C22B )
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(~C*(~A*~B+A*D)+C*(~A+D)) K0::H0=(~D*(B*C)+D*(A*(B*C))) F1:F F0:F 4 MODE K1 \ K0 [ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 { NGID1 cpu0/SLICE_802 SLICE R21C12C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(A*D)+B*(~A*C+A*(C+D))) K0::H0=(~B*(A*C)+B*((A*C)+D)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 = NGID3 >cpu0/SLICE_937 SLICE R19C22D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*C) K0::H0=(~D*(~B*~A+B*(~C*~A))+D*(~B+~C)) F1:F F0:F 4 MODE K1 ^ K0 ] REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 cpu0/dec_ea/SLICE_803 SLICE R17C16B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(C*A)+D*(~C*B+C*(B+A))) K0::H0=(~B*(A*C)+B*((A*C)+D)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 5 NGID3 6cpu0/regs/SLICE_938 SLICE R9C21C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=((~C*B)*~A)*D K0::H0=(~B*C+B*((A*D)+C)) F1:F F0:F 4 MODE K1 ` K0 _ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ~ NGID2 _cpu0/SLICE_804 SLICE R19C17B )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~A*C+A*(~B+D)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_939 SLICE R7C18D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~D*~A) K0::H0=(C*(D*(B*~A))) F1:F F0:F 4 MODE K1 b K0 a REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_805 SLICE R17C16C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*D+B*(~A+C)) K0::H0=(~D*(C*A)+D*(~A+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_940 SLICE R9C24C )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(A*(D*(~C*~B))) K0::H0=((C+A)+B) F1:F F0:F 4 MODE K1 d K0 c REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_806 SLICE R19C15B )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~A*D+A*(~C+B)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_941 SLICE R12C22A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(((~A*~B)*~D)*C)+((~B*~D)*~C) K0::H0=((B*(C*D))+A) F1:F F0:F 4 MODE K1 f K0 e REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_807 SLICE R22C19B )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~C*D+C*(~B+A)) K0::H0=(~C*(D*B)+C*(~B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_942 SLICE R8C21C )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~A*(~C*D)+A*~C) F1:F F0:F 4 MODE K1 h K0 g REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_808 SLICE R22C18A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*A+B*(~C+D)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_943 SLICE R12C21B )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~A*(~B*C)+A*~B) K0::H0=(C*(~A*~B)) F1:F F0:F 4 MODE K1 j K0 i REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_809 SLICE R17C12A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*D+B*(~C+A)) K0::H0=(~B*(C*D)+B*(~D+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_944 SLICE R7C20A )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~A*(~C*(B*D))) K0::H0=(D*~C) F1:F F0:F 4 MODE K1 l K0 k REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_810 SLICE R22C11C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*D+B*(~C+A)) K0::H0=(~D*(B*C)+D*(~C+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_945 SLICE R9C23B )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~D*(A*B)+D*(~A*C+A*(C+B))) K0::H0=(~D+A) F1:F F0:F 4 MODE K1 n K0 m REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_811 SLICE R21C11A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~C*D+C*(~B+A)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_946 SLICE R15C28A )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~A*(~C*(D*~B))) K0::H0=(B*D) F1:F F0:F 4 MODE K1 p K0 o REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_812 SLICE R11C14D )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~D*(~B*~C)) K0::H0=(~B*((~C+D)+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_947 SLICE R14C21A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~D*(C*~A))) K0::H0=(C*(D*(~B*~A))) F1:F F0:F 4 MODE K1 r K0 q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_813 SLICE R11C14C )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~B*(~D*(~A*C)+D*(C+A))+B*C) K0::H0=(~C*(~A*B)+C*(~A*B+A*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_948 SLICE R16C25A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~A*C+A*((~D*~B)+C)) K0::H0=(A*(D*(~C*B))) F1:F F0:F 4 MODE K1 t K0 s REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_814 SLICE R15C19C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=((~C*A)*~B)*D K0::H0=(~B*(~D*~A+D*(~A+C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 hcpu0/SLICE_949 SLICE R18C24D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(D*C) K0::H0=(~B*~C+B*(~D*~C+D*(~C*A))) F1:F F0:F 4 MODE K1 v K0 u REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_815 SLICE R12C17C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*~D+A*(~B*~D+B*(~D*~C))) K0::H0=(~C*(~A*~B+A*(~B+D))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~A*(D*C)) K0::H0=(~B*(~A+D)+B*(~C*(D*A)+C*(~A+D))) F1:F F0:F 4 MODE K1 x K0 w REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_816 SLICE R12C19D )
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REG1
REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 $ NGID3 %cpu0/regs/SLICE_950 SLICE R19C25B )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~A*~C+A*D) K0::H0=(A*(~D*(~B+~C))) F1:F F0:F 4 MODE K1 z K0 y REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_817 SLICE R15C20B )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=((C+B)+A) K0::H0=(~B*(~A*~D+A*(~D+C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 hcpu0/SLICE_951 SLICE R19C23A )
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! " # $ % & ' ( \MODE:LOGIC K1::H1=(~A*(C*B)+A*(~C*(D*B)+C*B)) K0::H0=(~C*D+C*(~D*(B*~A)+D*(A+B))) F1:F F0:F 4 MODE K1 | K0 { REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_818 SLICE R15C18B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=((A+C)+D) K0::H0=(~D*(~C*A+C*(B+A))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 g NGID2 , NGID3 -cpu0/SLICE_952 SLICE R19C35C )
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! " # $ % & ' ( WMODE:LOGIC K1::H1=(((~D*A)+C)+B) K0::H0=(~A*(~C+~B)+A*(~D*(C*~B)+D*(~C+~B))) F1:F F0:F 4 MODE K1 ~ K0 } REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_819 SLICE R15C20A )
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! " # $ % & ' ( [MODE:LOGIC K1::H1=(~C*(~A*(~B+~D)+A*(~D+B))+C*(A*(~D+B))) K0::H0=(~C*(D*(A*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~D+(C*B)) K0::H0=(~B*(~D*(~C+A)+D*(C*A))+B*(~D*(C*A)+D*(~C+A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_820 SLICE R15C26A )
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cpu0/SLICE_953 SLICE R18C24A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=~B*~((D*C)*~A) K0::H0=(~B*A+B*(A*(~D*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*(~A*D))) K0::H0=(~B*(~C*D+C*(D+A))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 " NGID3 #cpu0/SLICE_954 SLICE R16C26D )
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NGID2 cpu0/SLICE_821 SLICE R15C21B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C*(A*~B)+C*~B)+D*~B) K0::H0=(~C*~D+C*(~D*(~B+~A))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/regs/SLICE_955 SLICE R16C14C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~D*(~B+~C)+D*~B) K0::H0=(~C*D+C*(~D*(~A*B)+D*~A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_822 SLICE R15C19D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*(~D+C)+B*A) K0::H0=(~C*(~A*~D)+C*(~D+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_956 SLICE R18C16C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(A*(~B*(~C*~D))) K0::H0=(~B*C+B*(~A*(~D*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_823 SLICE R15C17A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*(~D+A)+B*C) K0::H0=(~C*(D*B)+C*(~B+D)) F1:F F0:F 4 MODE K1 ! K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_957 SLICE R15C25B )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~B+~D) K0::H0=(~A*(~D*(C*~B))+A*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_824 SLICE R12C20B )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(A*(D*B)) K0::H0=(~D*(~A*~B)+D*(~C*(~A*~B))) F1:F F0:F 4 MODE K1 # K0 " REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 dcpu0/regs/SLICE_958 SLICE R15C24C )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~D*(A*(~B*C))) K0::H0=(~C*(~A*(B*D)+A*(~B*D))+C*(A*(~B*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_825 SLICE R15C19A )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(A*(D*~B)) K0::H0=(~D*(~C*~B)+D*(~A*(~C*~B))) F1:F F0:F 4 MODE K1 % K0 $ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 acpu0/SLICE_959 SLICE R17C26C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~D*(~A*(~C*~B))) K0::H0=(~A*~D+A*(~B*~D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_826 SLICE R14C21A )
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! " # $ % & ' ( ZMODE:LOGIC K1::H1=(~B*(C*D)+B*(~C*A+C*(D+A))) K0::H0=(~A*(~B*(D*~C)+B*~C)+A*~C) F1:F F0:F 4 MODE K1 ' K0 & REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 cpu0/regs/SLICE_960 SLICE R18C16B )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(D*C) K0::H0=(~C*(~D*~B+D*~A)+C*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_827 SLICE R14C19C )
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! " # $ % & ' ( \MODE:LOGIC K1::H1=(~B*(~D+~C)+B*(~D*C)) K0::H0=(~D*(~C*~B+C*(A*~B))+D*(~C+(B+A))) F1:F F0:F 4 MODE K1 ) K0 ( REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 # NGID1 pcpu0/SLICE_961 SLICE R22C33B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(C+D) K0::H0=(~A*(~B*(C*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ucpu0/SLICE_828 SLICE R14C13B )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~D*(~A*(B*C))) K0::H0=(((B*C)+D)+A) F1:F F0:F 4 MODE K1 + K0 * REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1 scpu0/regs/SLICE_962 SLICE R18C23D )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(D*(~C*(A*~B))) K0::H0=(~A+~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_829 SLICE R14C16C )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~D*A+D*C) K0::H0=(~D*(~B*(~C*A)+B*(~C+~A))+D*(~C+~A)) F1:F F0:F 4 MODE K1 - K0 , REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_963 SLICE R21C32C )
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! " # $ % & ' (
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! " # $ % & ' ( OMODE:LOGIC K1::H1=((~B*A+B*(C+A))+D) K0::H0=(~D*C+D*(~A*C+A*(~B+C))) F1:F F0:F 4 MODE K1 / K0 . REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_964 SLICE R17C15C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(C+D)+A*(~D+(~C+B))) K0::H0=(~B*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_831 SLICE R11C15D )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~C*(~A*(~B*D)+A*(~B+~D))+C*(~B+~D)) K0::H0=(~A+(~C*D+C*B)) F1:F F0:F 4 MODE K1 1 K0 0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 `cpu0/SLICE_965 SLICE R10C26C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*(~B*(~D*~A))) K0::H0=(~C*(D*~A)+C*(A+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_832 SLICE R21C10A )
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(~D*(~B*C)+D*(~A+(~B*C))) K0::H0=(~C*(B*~D)+C*(D+B)) F1:F F0:F 4 MODE K1 3 K0 2 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 $cpu0/SLICE_966 SLICE R17C25A )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~A*(~B*(D*C)+B*D)+A*(D*C)) K0::H0=(B*(D*(A*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_833 SLICE R12C16C )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(D*A)+B*(~D*C+D*(C+A))) K0::H0=(~C*(B*~D)+C*(D+B)) F1:F F0:F 4 MODE K1 5 K0 4 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_967 SLICE R15C24D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~D*(~B*(~A*~C)+B*~A)+D*(~A*~C)) K0::H0=(~A*(C*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_834 SLICE R11C16C )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(A*C)+B*(~A*D+A*(D+C))) K0::H0=(~C*(B*~D)+C*(D+B)) F1:F F0:F 4 MODE K1 7 K0 6 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_968 SLICE R16C23B )
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! " # $ % & ' ( WMODE:LOGIC K1::H1=((~D*(B+A)+D*A)+C) K0::H0=(~D*(~C*(~B+A)+C*(B*A))+D*(B*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ycpu0/dec_regs/SLICE_835 SLICE R17C10D )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~A*(D*B)+A*(~D*C+D*(C+B))) K0::H0=(~C*(A*~D)+C*(D+A)) F1:F F0:F 4 MODE K1 9 K0 8 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_969 SLICE R15C23B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(A*B) K0::H0=(~D*(B*(C*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_836 SLICE R21C14A )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(C*D)+B*(~C*A+C*(A+D))) K0::H0=(~B*(D*~A)+B*(A+D)) F1:F F0:F 4 MODE K1 ; K0 : REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_970 SLICE R17C23D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=((C*(~B*D))+A) K0::H0=(~A*(~D*(C*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_837 SLICE R14C14B )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~D*(C*A)+D*(~C*B+C*(B+A))) K0::H0=(~B*(C*~D)+B*(D+C)) F1:F F0:F 4 MODE K1 = K0 < REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_971 SLICE R17C23A )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=((~A+D)+C) K0::H0=(C*(D*(~B*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_838 SLICE R23C12D )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~C*(D*B)+C*(~D*A+D*(B+A))) K0::H0=(~A*(B*~D)+A*(D+B)) F1:F F0:F 4 MODE K1 ? K0 > REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_972 SLICE R15C23C )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(D*B) K0::H0=(~C*(~D*(B*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_839 SLICE R21C16B )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~D*(C*A)+D*(~C*B+C*(B+A))) K0::H0=(~C*(B*~D)+C*(D+B)) F1:F F0:F 4 MODE K1 A K0 @ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_973 SLICE R17C24C )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=((D*(~A*B))+C) K0::H0=(~C*(~D*(B*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_840 SLICE R15C14A )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(C*D)+B*(~C*A+C*(A+D))) K0::H0=(~A*(C*~D)+A*(D+C)) F1:F F0:F 4 MODE K1 C K0 B REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 $cpu0/regs/SLICE_974 SLICE R18C23B )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~A*(~D*C+D*(~B+C))+A*C) K0::H0=(~B*(A*(C*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_841 SLICE R15C13C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*A+B*D) K0::H0=(~C*(~D+~A)+C*(~D*A)) F1:F F0:F 4 MODE K1 E K0 D REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_975 SLICE R17C30D )
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! " # $ % & ' ( WMODE:LOGIC K1::H1=(C*(~B*(A+D))) K0::H0=(~B*(~D*(~C+A)+D*(~C*~A))+B*(~C*~A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 6cpu0/dec_regs/SLICE_842 SLICE R11C17D )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(A+C) K0::H0=(~A*(D+C)+A*((D+C)+B)) F1:F F0:F 4 MODE K1 G K0 F REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_976 SLICE R19C35D )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~A+((B+D)+C)) K0::H0=(~B*(~D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 }cpu0/dec_regs/SLICE_843 SLICE R11C16A )
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! " # $ % & ' ( `MODE:LOGIC K1::H1=(~C*(~B*~D+B*(A*~D))+C*(~B*(~A*~D))) K0::H0=(~D*(A*(B*~C))+D*(A*B)) F1:F F0:F 4 MODE K1 I K0 H REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_977 SLICE R19C31D )
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~A*(~C*D+C*(B+D))+A*(~C+(B+D))) K0::H0=(~A*D+A*(~C*D+C*(~B+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 pcpu0/dec_regs/SLICE_844 SLICE R21C16D )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~(B+D)*A)*C K0::H0=(B*((C*A)+D)) F1:F F0:F 4 MODE K1 K K0 J REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_978 SLICE R17C31D )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~B*~D) K0::H0=(~A*(~B*(D*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_845 SLICE R18C11A )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=((A*D)*C)+(~A*~C) K0::H0=(~C*(D*(~B*A))) F1:F F0:F 4 MODE K1 M K0 L REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(B+D) K0::H0=(~B*D+B*(~A*(D+C)+A*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 cpu0/SLICE_846 SLICE R17C9A )
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cpu0/SLICE_979 SLICE R16C34D )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(D*C) K0::H0=(A*(B*(D*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_847 SLICE R21C12D )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~A*(C*B)+A*(C*(B*~D))) K0::H0=(~C*~D+C*(~D*(~B*~A))) F1:F F0:F 4 MODE K1 O K0 N REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_980 SLICE R19C31C )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(((D+A)+B)+C) K0::H0=(B*(C*(~A+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 scpu0/SLICE_848 SLICE R15C15C )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(A*D) K0::H0=(B*(~D*(C*A))) F1:F F0:F 4 MODE K1 Q K0 P REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Z NGID1 cpu0/SLICE_981 SLICE R16C29D )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~D*(A*C)) K0::H0=(~B*(A*~D)+B*(~C*(D+A)+C*(A*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ncpu0/dec_regs/SLICE_849 SLICE R12C18C )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~D*(C*(A*~B))) K0::H0=(~C*~D) F1:F F0:F 4 MODE K1 S K0 R REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 q NGID1 cpu0/SLICE_982 SLICE R8C21A )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*B+D*(~C*B)) K0::H0=(~B*A+B*(~C*(~D+A)+C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 bcpu0/SLICE_850 SLICE R17C11B )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~D*(~A*B)+D*(~A*B+A*C)) K0::H0=(~C*(~D*(~A*B)+D*(B+A))+C*B) F1:F F0:F 4 MODE K1 U K0 T REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_983 SLICE R9C16A )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~D*(~C*(~A*B))) K0::H0=(~D*(~B*(A*~C)+B*~C)+D*(A*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_851 SLICE R17C15C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~C*A+C*B) K0::H0=(~A*C+A*D) F1:F F0:F 4 MODE K1 W K0 V REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 cpu0/alu/alu16/SLICE_984 SLICE R7C16A )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(A*D) K0::H0=(D*(A*(C*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_852 SLICE R22C12D )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~C*D+C*A) K0::H0=(~C*B+C*D) F1:F F0:F 4 MODE K1 Y K0 X REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 + NGID1 cpu0/alu/alu16/SLICE_985 SLICE R8C18C )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~A*(~D*~C)+A*(~B*(~D*~C)+B*~D)) K0::H0=(~D*(~A*(C+B)+A*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ( NGID1 cpu0/dec_regs/SLICE_853 SLICE R18C17C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~D*C+D*B) K0::H0=(~A*B+A*D) F1:F F0:F 4 MODE K1 [ K0 Z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 cpu0/alu/alu16/SLICE_986 SLICE R7C22D )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~D*(A*B)+D*A) K0::H0=(~D*(C*B)+D*(~C*(B*~A)+C*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 - NGID1 2cpu0/SLICE_854 SLICE R18C16A )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~C*B+C*D) F1:F F0:F 4 MODE K1 ] K0 \ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 - NGID1 cpu0/alu/alu16/SLICE_987 SLICE R6C20C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(B*(D*(A*C))) K0::H0=(~A*(D+B)+A*(~C+(D+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 0 NGID1 hcpu0/SLICE_855 SLICE R18C12D )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~B*A+B*D) F1:F F0:F 4 MODE K1 _ K0 ^ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1 cpu0/alu/alu16/SLICE_988 SLICE R14C19A )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=((~D*C)*~B)*A K0::H0=(~A*((C+B)+D)+A*(B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 1 NGID1 NGID2 cpu0/SLICE_856 SLICE R17C14C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*D+A*B) K0::H0=(~C*A+C*D) F1:F F0:F 4 MODE K1 a K0 ` REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 / NGID1 cpu0/alu/alu16/SLICE_989 SLICE R7C19D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~D+((~A+~B)+C)) K0::H0=(C*(~A*(B*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 3 NGID1 cpu0/dec_regs/SLICE_857 SLICE R16C16B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*C+A*B) K0::H0=(~A*B+A*C) F1:F F0:F 4 MODE K1 c K0 b REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 0 NGID1 cpu0/alu/alu16/SLICE_990 SLICE R9C22D )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~B*(~D*~A)) K0::H0=(((A*D)+C)+B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 5 NGID1 Tcpu0/dec_regs/SLICE_858 SLICE R18C13D )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~D*C+D*A) K0::H0=(~C*B+C*D) F1:F F0:F 4 MODE K1 e K0 d REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 1 NGID1 cpu0/alu/alu16/SLICE_991 SLICE R7C22A )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~A*~D) K0::H0=(~A*(C*D)+A*(C*(D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 : NGID1 cpu0/dec_regs/SLICE_859 SLICE R15C14D )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~D*A+D*C) K0::H0=(~C*A+C*D) F1:F F0:F 4 MODE K1 g K0 f REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 2 NGID1 cpu0/alu/alu16/mulu/SLICE_992 SLICE R12C12C )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(D*(~A*(~C*B))) K0::H0=(A*(D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ? NGID1 cpu0/SLICE_860 SLICE R22C12A )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(A*B) K0::H0=(~C*(A*D)+C*(~B*(A*D)+B*D)) F1:F F0:F 4 MODE K1 i K0 h REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_993 SLICE R11C12A )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~C*B) K0::H0=((~D*(C*~B))+A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @ NGID1 0cpu0/SLICE_861 SLICE R23C19B )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(B*D) K0::H0=(~B*(A*C)+B*(~D*(A*C)+D*C)) F1:F F0:F 4 MODE K1 k K0 j REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_994 SLICE R11C12B )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(~C*B+C*A) K0::H0=(D*(A*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 A NGID1 cpu0/SLICE_862 SLICE R19C14B )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(D*C) K0::H0=(~B*(A*D)+B*(~C*(A*D)+C*D)) F1:F F0:F 4 MODE K1 m K0 l REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_995 SLICE R10C11B )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(D*(A*(~C*B))) K0::H0=(A+C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 C NGID1 cpu0/SLICE_863 SLICE R19C13A )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(C*B) K0::H0=(~C*(A*B)+C*(~D*(A*B)+D*B)) F1:F F0:F 4 MODE K1 o K0 n REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_996 SLICE R10C12C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*(A*(C*D))) K0::H0=(~A*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 M NGID1 {cpu0/dec_regs/SLICE_864 SLICE R11C18A )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(D*B) K0::H0=(~C*(A*D)+C*(~B*(A*D)+B*D)) F1:F F0:F 4 MODE K1 q K0 p REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_997 SLICE R23C22A )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~B*(A*~C)+B*(A*(~D*~C))) K0::H0=(~C*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 U NGID1 Zcpu0/dec_regs/SLICE_865 SLICE R17C12B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~C*A)+B*(A+C)) K0::H0=(~B*D+B*(~A*D+A*C)) F1:F F0:F 4 MODE K1 s K0 r REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [ NGID1 gcpu0/alu/alu16/SLICE_998 SLICE R7C22C )
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! " # $ % & ' ( [MODE:LOGIC K1::H1=(~A*(B*~C)+A*(~B*~D+B*(~D+~C))) K0::H0=(~D*(C+A)+D*((~B+C)+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 V NGID1 tcpu0/dec_regs/SLICE_866 SLICE R11C18D )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(B*D) K0::H0=(C*(A*(B*~D))) F1:F F0:F 4 MODE K1 u K0 t REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \ NGID1 cpu0/alu/SLICE_999 SLICE R14C20B )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~D*(C*A)+D*(C*(B+A))) K0::H0=(~A*B+A*((C*~D)+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 c NGID1 cpu0/dec_regs/SLICE_867 SLICE R15C18C )
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~A*(B*(~C*D))+A*((~C+~D)+B)) K0::H0=(B*(~D*(~A*~C))) F1:F F0:F 4 MODE K1 w K0 v REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 a NGID1 cpu0/alu/alu16/SLICE_1000 SLICE R8C22B )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*(~B*~C)) K0::H0=(~A*(B*C)+A*(~D*(B*C)+D*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 g NGID1 qcpu0/dec_regs/SLICE_868 SLICE R11C15A )
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(~A*(~D*(C*B))) K0::H0=(~A*(D*C)+A*(~B*(D*C)+B*(~C+D))) F1:F F0:F 4 MODE K1 y K0 x REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 d NGID1 cpu0/alu/alu16/SLICE_1001 SLICE R10C22C )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~A*(C+D)+A*((B+C)+D)) K0::H0=(~D*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 h NGID1 ncpu0/dec_regs/SLICE_869 SLICE R19C16A )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(~B*A+B*D) K0::H0=(~C*(B*(D*A))) F1:F F0:F 4 MODE K1 { K0 z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 f NGID1 ycpu0/alu/alu16/SLICE_1002 SLICE R9C22A )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(((C+A)+B)+D) K0::H0=(~B+(~D*A+D*(~C+A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 i NGID1 ocpu0/dec_regs/SLICE_870 SLICE R10C19C )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~B*(~D*(~C*A))) F1:F F0:F 4 MODE K1 } K0 | REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 i NGID1 ucpu0/alu/alu16/SLICE_1003 SLICE R8C21B )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(D@B) K0::H0=(~A+((C+D)+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 v NGID1 cpu0/SLICE_871 SLICE R15C14B )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~C*A+C*D) K0::H0=(~C*(~B*~A)) F1:F F0:F 4 MODE K1 K0 ~ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 zcpu0/alu/alu16/SLICE_1004 SLICE R8C18B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~D*(~A*(C*B))) K0::H0=(A*(C*(B*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 w NGID1 cpu0/dec_regs/SLICE_872 SLICE R12C16B )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~C*(~D*(~A*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 l NGID1 xcpu0/alu/alu16/SLICE_1005 SLICE R8C22D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~A*(~B*~C+B*(~D+~C))+A*~C) K0::H0=((B+C)+D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 { NGID1 cpu0/dec_regs/SLICE_873 SLICE R14C17A )
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! " # $ % & ' ( \MODE:LOGIC K1::H1=(~D*((A*B)+C)+D*C) K0::H0=(~C*(~B*(A*D)+B*A)+C*(~B*(~D+A)+B*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 m NGID1 cpu0/alu/alu16/SLICE_1006 SLICE R7C16C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(C*(~B*(~D+A)+B*(A+D))) K0::H0=((~D*(~C*A))+B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ~ NGID1 cpu0/dec_regs/SLICE_874 SLICE R12C17B )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=((~D*C)*B)+(((~D*C)*~A)*~B) K0::H0=(~C*A+C*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 w NGID1 NGID2 _cpu0/alu/SLICE_1007 SLICE R8C19D )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(C*A) K0::H0=(~C*(A+B)+C*(~B*A+B*(D+A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_875 SLICE R18C9B )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*(~D*A)+B*(~D*A+D*C)) K0::H0=(~A*B+A*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 cpu0/alu/SLICE_1008 SLICE R8C17B )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(~B*A) K0::H0=(C*(A*(D*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_876 SLICE R12C15B )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*(D*~A)) K0::H0=(~C*(~A*(D*B))+C*(~A*(~B+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 } NGID1 _cpu0/alu/alu16/SLICE_1009 SLICE R7C15A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A+~C) K0::H0=(~B*(~D*A+D*(~C+A))+B*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_877 SLICE R10C16D )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~B*(~A*(D@C)+A*(~D*C))) K0::H0=(~A*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_1010 SLICE R7C15C )
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! " # $ % & ' ( VMODE:LOGIC K1::H1=(~C*(~D*(~B*~A)+D*(~A+B))) K0::H0=(~A*(~B*C+B*(D+C))+A*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_878 SLICE R16C11D )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~B*(~D*A)+B*(C*(D*~A))) K0::H0=(~A*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_1011 SLICE R8C22C )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(((D+A)+C)+B) K0::H0=(C*(A*(B*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_879 SLICE R11C14A )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~C*~A) K0::H0=(~D*(A*(~C*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/s8/SLICE_1012 SLICE R14C16B )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(B*(D*(C*A))) K0::H0=(B*(~A*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_880 SLICE R19C15A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~C*A+C*B) K0::H0=(~D*(B*C)+D*(~A*(B*C)+A*(~C+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(B*~C) K0::H0=(~B*(~D*(A*C))+B*(D*(A*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_881 SLICE R10C18B )
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NGID1 cpu0/alu/alu8/SLICE_1013 SLICE R7C21D )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(D*A) K0::H0=(D*(A*(~C*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_882 SLICE R14C16D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~D*C+D*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Jcpu0/alu/alu8/a8/SLICE_1014 SLICE R17C23C )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~(D+B)*C)*A K0::H0=(~B*(D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_883 SLICE R18C16D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~A*C)+B*(C+A)) K0::H0=(~A*B+A*(~D*B+D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 )cpu0/alu/alu8/a8/SLICE_1015 SLICE R7C16D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(A*(~D*(C*~B))) K0::H0=(C*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 dcpu0/SLICE_884 SLICE R18C9A )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~B*(~C*(~D*A)+C*(A+D))+B*A) K0::H0=(~D*(~A*C)+D*(~A*C+A*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 # NGID1 @cpu0/alu/alu8/a8/SLICE_1016 SLICE R12C16C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~D*(C*B)+D*(~C*A+C*(B+A))) K0::H0=(~D*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_885 SLICE R21C13A )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~A*(~B*C)+A*(B*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 0 NGID1 3cpu0/alu/alu8/SLICE_1017 SLICE R17C23B )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~A*B+A*(~D*B+D*(C+B))) K0::H0=(~B*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_886 SLICE R18C9D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(~B*C)+D*(C+B)) K0::H0=(~C*B+C*(~A*B+A*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/SLICE_1018 SLICE R19C24C )
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! " # $ % & ' ( 7MODE:LOGIC K1::H1=(D*(B*(C*A))) K0::H0=(D*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 `cpu0/SLICE_887 SLICE R21C16C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(~B*C)+A*(C+B)) K0::H0=(~B*C+B*(~D*C+D*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/SLICE_1019 SLICE R16C24A )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(A*(~B*(C*D))) K0::H0=(~B*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_888 SLICE R19C12C )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~B*(D*A)+B*(~D*C+D*(C+A))) K0::H0=(~C*B+C*(B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/SLICE_1020 SLICE R9C16D )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~B*(D+A)+B*((C+D)+A)) K0::H0=(A*~D) F1:F F0:F 4 MODE K1
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! " # $ % & ' (
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K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_889 SLICE R18C10C )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(C*~B) K0::H0=(~D*(A*~C)+D*(A*(~C*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 X NGID1 dcpu0/alu/alu8/SLICE_1022 SLICE R7C20D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~C*(~D*(A*B))) K0::H0=(C*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ycpu0/dec_regs/SLICE_890 SLICE R14C14C )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(B*~C) K0::H0=(D*(~B*(A*C)+B*(~A*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Y NGID1 ecpu0/alu/alu8/SLICE_1023 SLICE R8C14B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(((D+C)+B)+A) K0::H0=(~A*((~C+B)+D)+A*(~B*~C)) F1:F F0:F 4 MODE K1 K0
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_891 SLICE R22C13D )
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! " # $ % & ' (
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~A*((D*B)+C)+A*C) K0::H0=(D*(~C*~B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 # NGID1 cpu0/SLICE_892 SLICE R14C24C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(~B*C)+D*(C+B)) K0::H0=(~D*B+D*(~C*B+C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(B*(A*(~D*~C))) K0::H0=(~C*(~D*(B*A)+D*(~B+A))+C*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1 cpu0/regs/ea/SLICE_893 SLICE R21C19C )
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cpu0/alu/SLICE_1025 SLICE R19C25C )
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! " # $ % & ' ( aMODE:LOGIC K1::H1=(~D*(~B*A+B*(C@A))+D*(~B+(C@A))) K0::H0=(~A*(~C*(D*B)+C*(~D+B))+A*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 cpu0/regs/ea/SLICE_894 SLICE R16C15B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(~B*C)+A*(C+B)) K0::H0=(~B*A+B*(~D*A+D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(C+D) K0::H0=(B*(A*(~C*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @ NGID1 cpu0/SLICE_895 SLICE R21C17D )
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cpu0/SLICE_1026 SLICE R19C28D )
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! " # $ % & ' ( ZMODE:LOGIC K1::H1=(~B*(~A*(D*~C)+A*~C)+B*~C) K0::H0=(~C*(B*A)+C*(~B*D+B*(D+A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 T NGID1 cpu0/regs/SLICE_896 SLICE R21C22D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*A)) K0::H0=(D*(A*(B*C))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 A NGID3 Bcpu0/SLICE_1027 SLICE R10C31D )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~C*(D*B)+C*(~D+B)) K0::H0=(~B*(D*A)+B*(~D*C+D*(C+A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 U NGID1 cpu0/regs/SLICE_897 SLICE R22C21A )
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! " # $ % & ' ( ZMODE:LOGIC K1::H1=((B*C)*A)*D K0::H0=(~D*(~B*(~C+~A)+B*~A)+D*(~B*~C+B*(~C*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_1028 SLICE R12C31B )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~A*(C*~D)+A*(D+C)) K0::H0=(~C*(A*D)+C*(~A*B+A*(B+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 V NGID1 cpu0/regs/SLICE_898 SLICE R18C17A )
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! " # $ % & ' ( VMODE:LOGIC K1::H1=(~D*(B*~A)+D*(~A*C)) K0::H0=(~C*(~D*B+D*(~A+B))+C*(~A+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1029 SLICE R10C29A )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~C*(A*~B)+C*(B+A)) K0::H0=(~D*(C*B)+D*(~C*A+C*(A+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 W NGID1 cpu0/regs/SLICE_899 SLICE R17C21D )
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! " # $ % & ' ( iMODE:LOGIC K1::H1=(~A*(~D+(~C+~B))+A*(~D+(~B+C))) K0::H0=(~A*(~B*(~C+~D)+B*~C)+A*(~B*(~C*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1030 SLICE R11C31A )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(A*~D)+B*(D+A)) K0::H0=(~A*(D*B)+A*(~D*C+D*(C+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 X NGID1 cpu0/SLICE_900 SLICE R14C32C )
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! " # $ % & ' ( fMODE:LOGIC K1::H1=(D*(~B*(C*~A))) K0::H0=(~A*(~B*(~D*~C)+B*(D*~C))+A*(~B*(~D+~C)+B*(~D*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_1031 SLICE R9C25A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~D*A+D*C) K0::H0=(~C*(~A*D)+C*(~A*D+A*B)) F1:F F0:F 4 MODE K1 " K0 ! REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [ NGID1 }cpu0/SLICE_901 SLICE R16C33B )
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! " # $ % & ' ( bMODE:LOGIC K1::H1=(~B+(~A*(~D+C)+A*(~D+~C))) K0::H0=(~B*(~A*(D@~C)+A*(~C+D))+B*(~A*~D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_1032 SLICE R14C25D )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~C*A+C*D) K0::H0=(~D*(~A*B)+D*(~A*B+A*C)) F1:F F0:F 4 MODE K1 $ K0 # REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 \ NGID1 cpu0/SLICE_902 SLICE R16C34C )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~C*(~A*(D*~B))) K0::H0=(~D*(~C*(~A*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_1033 SLICE R12C31A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~C*A+C*D) K0::H0=(~A*(~B*D)+A*(~B*D+B*C)) F1:F F0:F 4 MODE K1 & K0 % REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ] NGID1 cpu0/regs/ea/SLICE_903 SLICE R18C14D )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(C*(D*(A*~B))) K0::H0=(C*(D*(~B*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_1034 SLICE R11C30D )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~D*(B*A)) K0::H0=(~D*(~A*C+A*(B*C))+D*(B*C)) F1:F F0:F 4 MODE K1 ( K0 ' REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 d NGID1 zcpu0/SLICE_904 SLICE R16C12C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~A*(~D*(~B*C)+D*C)+A*(D*C)) K0::H0=(A*(D*(~B*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1035 SLICE R18C26C )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=((C*~D)+B) K0::H0=(~B*(D+A)+B*((C+D)+A)) F1:F F0:F 4 MODE K1 * K0 ) REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 f NGID1 cpu0/SLICE_905 SLICE R18C15C )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(D*(~B*(A*~C))) K0::H0=(D*(B*(~C*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_1036 SLICE R11C28D )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~D*A+D*(A*(~C+B))) K0::H0=(~D*A+D*(A*(C+B))) F1:F F0:F 4 MODE K1 , K0 + REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 o NGID1 cpu0/regs/SLICE_906 SLICE R22C25D )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(((C+D)+A)+B) K0::H0=(~D*(~B*(~C+~A)+B*~A)+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_alu/SLICE_1037 SLICE R11C29B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(B*C)+A*(~C+B)) K0::H0=(~C*(B*~D)+C*(D+B)) F1:F F0:F 4 MODE K1 . K0 - REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 } NGID1 cpu0/regs/SLICE_907 SLICE R22C21C )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*A+D*((A+C)+B)) K0::H0=(~A*B+A*((B+C)+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1038 SLICE R11C31D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(A*C)+B*(~C+A)) K0::H0=(~C*(B*~A)+C*(A+B)) F1:F F0:F 4 MODE K1 0 K0 / REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ~ NGID1 cpu0/regs/SLICE_908 SLICE R22C25C )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~C*(A*(~B*D))) K0::H0=(~C*(~B*~A+B*(A*~D))+C*(~B*~A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 jcpu0/SLICE_1039 SLICE R8C31A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(A*C)+B*(~C+A)) K0::H0=(~C*(D*~A)+C*(A+D)) F1:F F0:F 4 MODE K1 2 K0 1 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_909 SLICE R21C15B )
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(D*(~A*(~C*B)+A*B)) K0::H0=(~D*(A*(~C*~B))+D*(A*(C*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_1040 SLICE R9C30A )
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! " # $ % & ' ( 7MODE:LOGIC K1::H1=(C*(A*(D*B))) K0::H0=(C+D) F1:F F0:F 4 MODE K1 4 K0 3 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_910 SLICE R21C15C )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~A*(~C*(~B*~D))) K0::H0=(~D*(~C*(A*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1041 SLICE R16C34B )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(B*(~C*(A*D))) K0::H0=(~D*(~A*C+A*(C+B))+D*C) F1:F F0:F 4 MODE K1 6 K0 5 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_911 SLICE R19C24C )
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~B*(~A*D+A*(~C+D))+B*D) K0::H0=(~D*(A*B)+D*(~A*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 5 NGID1 cpu0/dec_op/SLICE_1042 SLICE R17C31A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(D*C)+B*(~D+C)) K0::H0=(~C*(~A*D)+C*(D+A)) F1:F F0:F 4 MODE K1 8 K0 7 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_912 SLICE R21C22A )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(D*(~A*(B*~C)+A*(~B*~C))) K0::H0=(D*(~A+(~C+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 6 NGID1 8cpu0/dec_op/SLICE_1043 SLICE R19C29D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(B*C)+D*(~B+C)) K0::H0=(~B*(~D*C)+B*(C+D)) F1:F F0:F 4 MODE K1 : K0 9 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_913 SLICE R21C21A )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~D*(~A*(~C*B))) K0::H0=(~D*(~A*(~C*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [ NGID1 `cpu0/SLICE_1044 SLICE R14C28C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(B*A)+D*(~B+A)) K0::H0=(~B*(~A*D)+B*(D+A)) F1:F F0:F 4 MODE K1 < K0 ; REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_914 SLICE R19C20C )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(B*(C*(D*A))) K0::H0=(A*(C*(D*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1045 SLICE R8C26A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)+D*(~C+A)) K0::H0=(~C*(~B*D)+C*(D+B)) F1:F F0:F 4 MODE K1 > K0 = REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_915 SLICE R21C21B )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~B*(~A*(D*C)+A*C)+B*(D*C)) K0::H0=(B*(~A*(D*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1046 SLICE R14C25C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(A*B)+C*(~A+B)) K0::H0=(~C*(~D*A)+C*(A+D)) F1:F F0:F 4 MODE K1 @ K0 ? REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(A*(D*(C*B))) K0::H0=(~A*(~B*(~D*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1047 SLICE R14C26B )
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cpu0/regs/SLICE_916 SLICE R19C20B )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~D*(~B*(~C*~A))) K0::H0=(D*(~B*(A*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1048 SLICE R14C32B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)+D*(~C+A)) K0::H0=(~B*(~C*D)+B*(D+C)) F1:F F0:F 4 MODE K1 B K0 A REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_917 SLICE R21C19D )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=((A*B)*~D)*~C K0::H0=(C*(B*(~D*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_1049 SLICE R16C28C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(B*C)+D*(~B+C)) K0::H0=(~C*(~B*D)+C*(D+B)) F1:F F0:F 4 MODE K1 D K0 C REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_918 SLICE R22C20A )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~(~A+~D)*B)*C K0::H0=(C*(D*(B*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_1050 SLICE R16C32D )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~B*(A*C)+B*(~C+A)) K0::H0=(~C*(~B*A)+C*~B) F1:F F0:F 4 MODE K1 F K0 E REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ~cpu0/regs/SLICE_919 SLICE R22C22A )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~C*(A*(B*D))+C*B) K0::H0=(~C*(D*A)+C*(~D*B+D*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 cpu0/dec_regs/SLICE_1051 SLICE R18C32D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~C*D+C*A) K0::H0=(~B*(C*~D)+B*(D+C)) F1:F F0:F 4 MODE K1 H K0 G REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 zcpu0/SLICE_920 SLICE R21C16A )
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! " # $ % & ' ( [MODE:LOGIC K1::H1=(~D*(B*A)+D*(~B*C+B*(C+A))) K0::H0=(~D*(B*A)+D*(~B*C+B*(C+A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Y NGID1 Zcpu0/dec_regs/SLICE_1052 SLICE R10C29C )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(B*D) K0::H0=(~C*(~D*(A+B))+C*(~D*A)) F1:F F0:F 4 MODE K1 J K0 I REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_921 SLICE R22C16C )
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! " # $ % & ' ( WMODE:LOGIC K1::H1=((D*A)*C)*B K0::H0=(~C*((~B+D)+A)+C*(~A*(~D*~B)+A*(~B+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 rcpu0/SLICE_1053 SLICE R14C31C )
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! " # $ % & ' ( \MODE:LOGIC K1::H1=(~A*(C*B)+A*(~D+(C*B))) K0::H0=(~C*(~D+~A)+C*(~D*~B+D*(~A*~B))) F1:F F0:F 4 MODE K1 L K0 K REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 ncpu0/regs/SLICE_922 SLICE R16C32D )
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~B*(~D+~A)+B*~D) K0::H0=(~B*(~C*(A+D)+C*(~D*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_1054 SLICE R12C29A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)) K0::H0=(~B*(~D*(~C*A)+D*(A+C))+B*A) F1:F F0:F 4 MODE K1 N K0 M REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @ NGID1 cpu0/regs/SLICE_923 SLICE R19C10A )
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! " # $ % & ' (
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~A*(B*(D*C))+A*C) K0::H0=(~B*(~D*(~A*C))) F1:F F0:F 4 MODE K1 P K0 O REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_924 SLICE R18C20B )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*(D*~A)+C*(A+D)) K0::H0=(~A*(D*~B)+A*(C*~B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1056 SLICE R9C23C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*A)+C*(~B*(D*A)+B*A)) K0::H0=(~C*(~A*(D*B)+A*B)+C*B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 R K0 Q REG1 T REG0 S Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ] NGID2 K NGID3 Lcpu0/regs/SLICE_925 SLICE R18C10B )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*(A*~C)+D*(C+A)) K0::H0=(~C*(A*~B)+C*(D*~B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1057 SLICE R12C23C )
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! " # $ % & ' (
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*(B*~A)+C*(A+B)) K0::H0=(~A*(B*~D)+A*(C*~D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1058 SLICE R11C23B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~C*~A)+D*(~B*(~C*~A))) K0::H0=(~B*(~D*(~A*~C))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 X K0 W REG1 Z REG0 Y Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/regs/SLICE_927 SLICE R14C20B )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~A*(B*~D)+A*(D+B)) K0::H0=(~D*(B*~C)+D*(A*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1059 SLICE R12C28C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~B*C)+A*(~D*(~B*C)+D*C)) K0::H0=(~A*(~D*(~B*~C))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 \ K0 [ REG1 ^ REG0 ] Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/regs/SLICE_928 SLICE R18C18D )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*(D*(~C+~A))+B*D) K0::H0=(~B*(A*(~C+~D))+B*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1060 SLICE R22C18C )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=((D+C)+A) K0::H0=(~B*(~C*(A*~D))) F1:F F0:F 4 MODE K1 ` K0 _ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ?cpu0/regs/SLICE_929 SLICE R18C12B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~C+(D*~B)) K0::H0=(~C*A+C*(~D*(~B*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 & NGID1 .cpu0/SLICE_1061 SLICE R17C26D )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~A*((B+C)+D)) K0::H0=(B*(~D*(~C*~A))) F1:F F0:F 4 MODE K1 b K0 a REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_930 SLICE R17C20C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~C*(~D*(~B*A))+C*~B) K0::H0=(~C*(~D*(~B*A))+C*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ) NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A+D*C) K0::H0=(~C*(~A*(B*D))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 d K0 c REG1 f REG0 e Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 Q NGID3 Rcpu0/regs/SLICE_931 SLICE R11C25D )
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cpu0/SLICE_1062 SLICE R18C26A )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=((D+C)*B)+((D+(C*A))*~B) K0::H0=(~C*~D+C*~B) F1:F F0:F 4 MODE K1 h K0 g REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_932 SLICE R12C22A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~C*(~D*(~A*B))+C*~A) K0::H0=(~C*(~D*(~B*A))+C*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 ]cpu0/regs/SLICE_1063 SLICE R10C22B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(~A*~B+A*~D) F1:F F0:F 4 MODE K1 j K0 i REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 +cpu0/regs/SLICE_933 SLICE R12C21A )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=((~A*D)+((~A+~B)*~D))*C K0::H0=(~A*(D*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 - NGID2 cpu0/SLICE_1064 SLICE R18C36A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~C*(~B*D)+C*(D+B)) K0::H0=(~C*~D+C*~A) F1:F F0:F 4 MODE K1 l K0 k REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 .cpu0/regs/SLICE_934 SLICE R12C27D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=((A*D)*C)+(~A*~C) K0::H0=(~C*~D+C*(~D*(A*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 xcpu0/SLICE_1065 SLICE R19C24A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~D*C)+A*(C+D)) K0::H0=(~A*~C+A*~B) F1:F F0:F 4 MODE K1 n K0 m REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 0cpu0/regs/SLICE_935 SLICE R12C21B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(D*(A*(~B*C))) K0::H0=(D*(A*(~B*C))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 !cpu0/SLICE_1066 SLICE R14C24D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~D*(~B*C)+D*(C+B)) K0::H0=(~A*~C+A*~D) F1:F F0:F 4 MODE K1 p K0 o REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 1cpu0/regs/SLICE_936 SLICE R9C22D )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*(A*~C)+D*(B*~C)) K0::H0=(~B*(A*~C)+B*(C+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1067 SLICE R16C25D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~A*D)+B*(D+A)) K0::H0=(~D*~C+D*~B) F1:F F0:F 4 MODE K1 r K0 q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~C*(~B*(~D*A))) K0::H0=(~A*(~B*(~D*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1068 SLICE R17C27D )
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NGID1 3cpu0/regs/SLICE_937 SLICE R11C25A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~D*(~C*(~B*A))+D*~B) K0::H0=(~D*(~C*(~A*B))+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ! NGID1 \cpu0/alu/alu16/mulu/SLICE_1069 SLICE R10C11D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(~B*~D+B*~C) F1:F F0:F 4 MODE K1 t K0 s REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 5cpu0/regs/SLICE_938 SLICE R11C21A )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(((D*C)@A)*B)+((D*C)*~B) K0::H0=(B*(C*(D*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 j NGID2 cpu0/alu/alu16/mulu/SLICE_1070 SLICE R9C12D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~C*(~A*D)+C*(D+A)) K0::H0=(~A*~D+A*~C) F1:F F0:F 4 MODE K1 v K0 u REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 7cpu0/regs/SLICE_939 SLICE R16C25B )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(C*(D*(B*A))) K0::H0=(C*(A*(B*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 l NGID1 mcpu0/alu/alu16/mulu/SLICE_1071 SLICE R9C13C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=((C+~D)*B)+((C+(~D*A))*~B) K0::H0=(~C*~D+C*~B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 x K0 w REG1 z REG0 y Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 NGID2 NGID3 } NGID4 zcpu0/regs/SLICE_940 SLICE R15C25B )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(C*(B*(D*A))) K0::H0=(C*(A*(B*D))) F1:F F0:F 4 MODE K1 K0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~B*C)+D*(C+B)) K0::H0=(~D*~C+D*~A) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 | K0 { REG1 ~ REG0 } Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 , NGID2 l NGID3 jcpu0/regs/SLICE_941 SLICE R12C25D )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 n NGID1 ocpu0/alu/alu8/s8/SLICE_1072 SLICE R8C15D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~B*C)+A*(C+B)) K0::H0=(~D*~C+D*~B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 - NGID2 i NGID3 gcpu0/regs/SLICE_942 SLICE R12C27C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*B+C*(~D*A+D*B)) K0::H0=(~C*A+C*(~D*B+D*A)) F1:F F0:F 4 MODE K1
K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 cpu0/alu/SLICE_1073 SLICE R10C27A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(~A*~C+A*~B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 / NGID2 f NGID3 ecpu0/regs/SLICE_943 SLICE R12C24C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*(C*(~B+~A))+D*C) K0::H0=(~D*(B*(~C+~A))+D*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ! NGID1 cpu0/alu/alu8/SLICE_1074 SLICE R7C20C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~B*C)+D*(C+B)) K0::H0=(~B*~C+B*~D) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 2 NGID2 c NGID3 bcpu0/regs/SLICE_944 SLICE R10C23B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~D*(B*(~C*~A))) K0::H0=(A*(~D*(C*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Zcpu0/alu/SLICE_1075 SLICE R11C25C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~B*C)+D*(C+B)) K0::H0=(~B*~C+B*~D) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 4 NGID2 ` NGID3 _cpu0/regs/SLICE_945 SLICE R10C24B )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~C*(D*(~B+~A))+C*D) K0::H0=(~B*(D*(~C+~A))+B*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1076 SLICE R10C26B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*D)+B*(D+C)) K0::H0=(~D*~C+D*~A) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 6 NGID2 \ NGID3 [cpu0/regs/SLICE_946 SLICE R12C23B )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*(D*(~C+~A))+B*D) K0::H0=(~B*(D*(~C+~A))+B*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1077 SLICE R11C25A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D*A)+C*(A+D)) K0::H0=(~B*~C+B*~D) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 8 NGID2 Y NGID3 Xcpu0/regs/SLICE_947 SLICE R12C25A )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*(C*(~B+~A))+D*C) K0::H0=(~A*(D*(~B+~C))+A*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1078 SLICE R11C26B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(~C*~B+C*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 @cpu0/regs/SLICE_948 SLICE R11C24D )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*(D*(~C+~A))+B*D) K0::H0=(~B*(D*(~C+~A))+B*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1079 SLICE R10C26D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~D*A)+B*(A+D)) K0::H0=(~D*~C+D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Bcpu0/regs/SLICE_949 SLICE R10C23D )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~B*(D*(~A+~C))+B*D) K0::H0=(~B*(D*(~A+~C))+B*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 textctrl/SLICE_1080 SLICE R24C29B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*D)+A*(D+B)) K0::H0=(~A*~C+A*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Dcpu0/regs/SLICE_950 SLICE R12C26A )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~B*(~D*(~C*A))) K0::H0=(((D+A)+C)+B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~C*D)+B*(D+C)) K0::H0=(~C*~D+C*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Fcpu0/regs/SLICE_951 SLICE R10C22B )
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NGID1
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~B*D)+A*(D+B)) K0::H0=(~D*~C+D*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Hcpu0/regs/SLICE_952 SLICE R10C23C )
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cpu0/SLICE_1081 SLICE R17C28D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~D*(~A*C)+D*(C+A)) K0::H0=(~A*~C+A*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Jcpu0/regs/SLICE_953 SLICE R9C24A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~B*(C*~A))) K0::H0=(D@A) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 ! REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 9 NGID3 :cpu0/SLICE_1082 SLICE R9C30B )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(~A*~D+A*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Lcpu0/regs/SLICE_954 SLICE R9C24C )
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! " # $ % & ' ( 7MODE:LOGIC K1::H1=(C*(B*(D*A))) K0::H0=(D@C) F1:F F0:F 4 MODE K1 # K0 " REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1083 SLICE R8C30A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~C*D)+B*(D+C)) K0::H0=(~A*~C+A*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Ncpu0/regs/SLICE_955 SLICE R14C25C )
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! " # $ % & ' ( 5MODE:LOGIC K1::H1=(A@(~D+C)) K0::H0=(~A*D) F1:F F0:F 4 MODE K1 % K0 $ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1084 SLICE R21C25D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~D*B)+C*(B+D)) K0::H0=(~C*~D+C*~B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 A NGID2 V NGID3 Ucpu0/regs/SLICE_956 SLICE R10C24A )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(A*(B*~D)) K0::H0=(~C*(~B*D)+C*D) F1:F F0:F 4 MODE K1 ' K0 & REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 2cpu0/SLICE_1085 SLICE R17C27B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~C*D)+B*(D+C)) K0::H0=(~A*~D+A*~B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 C NGID2 S NGID3 Rcpu0/regs/SLICE_957 SLICE R11C24C )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~A*(B*(~D*~C))) K0::H0=(~D*(~C*A)) F1:F F0:F 4 MODE K1 ) K0 ( REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_1086 SLICE R14C33B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(~A*D)+B*(D+A)) K0::H0=(~B*~C+B*~A) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 E NGID2 O NGID3 Ncpu0/regs/SLICE_958 SLICE R12C26D )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=((~C*~B)*D)+((~C@B)*~D) K0::H0=(C*B) F1:F F0:F 4 MODE K1 + K0 * REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/dec_regs/SLICE_1087 SLICE R19C36D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(~B*D)+C*(D+B)) K0::H0=(~D*~C+D*~B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 G NGID2 L NGID3 Kcpu0/regs/SLICE_959 SLICE R10C24D )
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! " # $ % & ' ( 6MODE:LOGIC K1::H1=(~A+~C) K0::H0=(C*(~A*B)) F1:F F0:F 4 MODE K1 - K0 , REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_1088 SLICE R9C29D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(~A*~C+A*~D) REG0::::SD=0 Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ! NGID1 I NGID2 Jcpu0/regs/SLICE_960 SLICE R10C22A )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~C*(~B*A+B*(D*A))) K0::H0=(C*(~B*D)) F1:F F0:F 4 MODE K1 / K0 . REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 mcpu0/SLICE_1089 SLICE R17C32D )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~C*D)+B*(D+C)) K0::H0=(~B*~D+B*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 Kcpu0/regs/SLICE_961 SLICE R9C25A )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(C*(D*(A@B))) K0::H0=(C*(A*(~D*B))) F1:F F0:F 4 MODE K1 1 K0 0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Ycpu0/dec_regs/SLICE_1090 SLICE R11C30C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(~C*~D+C*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 # NGID1 Mcpu0/regs/SLICE_962 SLICE R9C27B )
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! " # $ % & ' ( 3MODE:LOGIC K1::H1=~D*~(A*B) K0::H0=(D*A) F1:F F0:F 4 MODE K1 3 K0 2 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 O NGID1 H NGID2 Ocpu0/dec_regs/SLICE_1091 SLICE R10C28C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~B*(~D*C)+B*(C+D)) K0::H0=(~B*~C+B*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 $ NGID1 Ocpu0/SLICE_963 SLICE R19C21D )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(C*(~A*(B*D)+A*B)) K0::H0=(~D*C+D*(~B*C)) F1:F F0:F 4 MODE K1 5 K0 4 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 U NGID1 bcpu0/SLICE_1092 SLICE R16C34C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(B*(~C*(~D*~A))) K0::H0=(~D*(B*A)+D*((B*A)+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 R NGID1 NGID2 f NGID3 gcpu0/SLICE_964 SLICE R19C22B )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~A*D*B)*~C K0::H0=(B*(A*(~D*C))) F1:F F0:F 4 MODE K1 7 K0 6 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 o NGID1 s NGID2 xcpu0/dec_regs/SLICE_1093 SLICE R9C28A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*D)+A*(~B*C+B*(C+D))) K0::H0=(~B*(A*D)+B*((A*D)+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 S NGID1 NGID2 X NGID3 Ycpu0/SLICE_965 SLICE R18C22A )
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! " # $ % & ' ( 6MODE:LOGIC K1::H1=(~C*~A) K0::H0=(C*(A*~B)) F1:F F0:F 4 MODE K1 9 K0 8 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1094 SLICE R16C25C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*D)+B*(~C*A+C*(A+D))) K0::H0=(~B*(D*A)+B*((D*A)+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 T NGID1 NGID2 Z NGID3 [cpu0/SLICE_966 SLICE R18C22D )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(~D*(B*(~C*A))+D*B) K0::H0=(C*A) F1:F F0:F 4 MODE K1 ; K0 : REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1095 SLICE R8C23D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C*D)+A*(~C*B+C*(B+D))) K0::H0=(~A*(B*C)+A*((B*C)+D)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 U NGID1 NGID2 \ NGID3 ]cpu0/SLICE_967 SLICE R18C22C )
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~A*(~D*(C*B)+D*(~C+B))+A*B) K0::H0=(~A*(~D*(C*B)+D*(~C+B))+A*B) F1:F F0:F 4 MODE K1 = K0 < REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 y NGID1 cpu0/SLICE_1096 SLICE R14C22D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(A*D)+B*(~A*C+A*(C+D))) K0::H0=(~D*(A*C)+D*((A*C)+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 V NGID1 NGID2 ^ NGID3 _cpu0/SLICE_968 SLICE R19C21B )
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(~C*D+C*(~B*D+B*A)) K0::H0=(~C*(~D*(B*A)+D*(~B+A))+C*A) F1:F F0:F 4 MODE K1 ? K0 > REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 cpu0/SLICE_1097 SLICE R12C23D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C*B)+A*(~C*D+C*(D+B))) K0::H0=(~D*(B*A)+D*((B*A)+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 W NGID1 NGID2 O NGID3 Pcpu0/regs/SLICE_969 SLICE R12C22B )
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~B*(~C*(D*A)+C*(~D+A))+B*A) K0::H0=(~B*(~D*(C*A)+D*(~C+A))+B*A) F1:F F0:F 4 MODE K1 A K0 @ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 { NGID1 ]cpu0/regs/ea/SLICE_1098 SLICE R12C16D )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(C*(~A*(~D*~B))) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Y NGID1 cpu0/regs/SLICE_970 SLICE R16C25D )
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~D*(~A*(C*B)+A*(~C+B))+D*B) K0::H0=(~D*(~B*(A*C)+B*(~A+C))+D*C) F1:F F0:F 4 MODE K1 C K0 B REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 cpu0/regs/ea/SLICE_1099 SLICE R19C17C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*(~A*~D))) K0::H0=(~D*(A*C)+D*(~C+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Z NGID1 NGID2 NGID3 cpu0/regs/SLICE_971 SLICE R17C18A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*A+C*(~D*A+D*B)) K0::H0=(~C*B+C*(~D*B+D*A)) F1:F F0:F 4 MODE K1 E K0 D REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1100 SLICE R21C17A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*~B) K0::H0=(~B*A+B*(~D*(~C*A)+D*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 w NGID1 cpu0/regs/SLICE_972 SLICE R17C20B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*C+A*(~D*C+D*B)) K0::H0=(~A*B+A*(~D*B+D*C)) F1:F F0:F 4 MODE K1 G K0 F REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1101 SLICE R19C17B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*~A)+C*(A+B)) K0::H0=(~B*(D*C)+B*(~D*A+D*(A+C))) REG0::::SD=0 Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_973 SLICE R23C20C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*A+B*(~C*A+C*D)) K0::H0=(~D*B+D*(~A*B+A*C)) F1:F F0:F 4 MODE K1 I K0 H REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1102 SLICE R19C17D )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~C*(B*~D)+C*(D+B)) K0::H0=(~A*(D*C)+A*(~D*B+D*(C+B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_974 SLICE R14C33A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*A+B*(~C*A+C*D)) K0::H0=(~B*D+B*(~C*D+C*A)) F1:F F0:F 4 MODE K1 K K0 J REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1103 SLICE R11C25B )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~A*D+A*C) K0::H0=(~D*(~C*B)+D*(~C*B+C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ~cpu0/regs/SLICE_975 SLICE R21C24C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*(A*~C)+D*(B*~C)) K0::H0=(~D*(C*~A)+D*(B*~A)) F1:F F0:F 4 MODE K1 M K0 L REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1104 SLICE R11C24A )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~D*(~A*(B*C)+A*C)+D*((~C+B)+A)) K0::H0=(~C*(A*B)+C*(~B+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_976 SLICE R21C28C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*(A*~C)+D*(B*~C)) K0::H0=(~D*(A*~C)+D*(B*~C)) F1:F F0:F 4 MODE K1 O K0 N REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1105 SLICE R21C24D )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~D*(A+C)+D*(A+B)) K0::H0=(~C*(D*B)+C*(~B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_977 SLICE R18C20D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(C*D)+A*(~D+C)) K0::H0=(~A*(~D*C)+A*(C+D)) F1:F F0:F 4 MODE K1 Q K0 P REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1106 SLICE R22C25D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(A+B) K0::H0=(~C*(~A*D)+C*(~A*D+A*(B*D))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 U NGID3 Vcpu0/SLICE_978 SLICE R18C20C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~D*(B*A)+D*(~A+B)) F1:F F0:F 4 MODE K1 S K0 R REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=((D+C)+B) K0::H0=(~B*(D*A)+B*(~D*(C*A)+D*A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 D NGID2 I NGID3 Jcpu0/regs/SLICE_979 SLICE R22C27C )
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cpu0/regs/ea/SLICE_1107 SLICE R22C25A )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~A*(~B+~C)+A*(~B*C)) K0::H0=(~C*(~A+B)+C*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_980 SLICE R21C28B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(A*D)+C*(~D+A)) K0::H0=(~C*(A*~D)+C*(D+A)) F1:F F0:F 4 MODE K1 U K0 T REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1108 SLICE R22C24D )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~C*(~D*(~A*B)+D*(~A+~B))+C*(~A+~B)) K0::H0=(~B+(~C*D+C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ycpu0/regs/SLICE_981 SLICE R19C29B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(D*B)+A*(~B+D)) K0::H0=(~D*(A*B)+D*(~B+A)) F1:F F0:F 4 MODE K1 W K0 V REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( [MODE:LOGIC K1::H1=(~D*(~B*(~A*C)+B*(~A+~C))+D*(~A+~C)) K0::H0=(~C*(D+B)+C*(D+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ;cpu0/regs/SLICE_982 SLICE R14C20A )
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cpu0/SLICE_1109 SLICE R16C13A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C*(~D*B))) K0::H0=(~A*(~D*(B*C)+D*C)+A*C) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_983 SLICE R14C9A )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~D*(~A*~B)+D*(~B+A)) K0::H0=(~B*(~A*~C)+B*(~C+A)) F1:F F0:F 4 MODE K1 Y K0 X REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 'cpu0/regs/ea/SLICE_1110 SLICE R19C20C )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~D*B+D*(~C*(B+A)+C*B)) K0::H0=(~C*(~B*(~A*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_984 SLICE R14C24D )
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! " # $ % & ' ( iMODE:LOGIC K1::H1=(~C*(~A*(~D+B)+A*~D)+C*((~D+B)+A)) K0::H0=(~D*(~A*(~B+C)+A*~B)+D*((~B+C)+A)) F1:F F0:F 4 MODE K1 [ K0 Z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1111 SLICE R19C20D )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(B*(D*~C)) K0::H0=(~A*(~B*~C)+A*(~D*(~B*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Bcpu0/SLICE_985 SLICE R17C24C )
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! " # $ % & ' ( iMODE:LOGIC K1::H1=(~C*(~A*(~D+B)+A*~D)+C*((~D+B)+A)) K0::H0=(~B*(~A*(~D+C)+A*~D)+B*((~D+C)+A)) F1:F F0:F 4 MODE K1 ] K0 \ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1112 SLICE R21C19A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*A+C*B) K0::H0=(A*(~D*(B*~C))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Y NGID1 NGID2 NGID3 cpu0/regs/SLICE_986 SLICE R14C9C )
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! " # $ % & ' ( [MODE:LOGIC K1::H1=(~D*(C*A)+D*(~C*B+C*(B+A))) K0::H0=(~D*(C*A)+D*(~C*B+C*(B+A))) F1:F F0:F 4 MODE K1 _ K0 ^ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1113 SLICE R21C20A )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*((D+A)+B)+C*(D+A)) K0::H0=((~A*(C*B))+D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_987 SLICE R22C22C )
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! " # $ % & ' ( [MODE:LOGIC K1::H1=(~B*(A*D)+B*(~A*C+A*(C+D))) K0::H0=(~B*(A*C)+B*(~A*D+A*(D+C))) F1:F F0:F 4 MODE K1 a K0 ` REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1114 SLICE R21C20D )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~C*(D*A)+C*(~D*B+D*(B+A))) K0::H0=(~B*(D*~A)+B*(A+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_988 SLICE R21C19B )
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! " # $ % & ' ( [MODE:LOGIC K1::H1=(~B*(D*A)+B*(~D*C+D*(C+A))) K0::H0=(~C*(A*B)+C*(~A*D+A*(D+B))) F1:F F0:F 4 MODE K1 c K0 b REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1115 SLICE R19C16A )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~A*(D*B)+A*(~D*C+D*(B+C))) K0::H0=(~C*(B*~D)+C*(D+B)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C+~D) K0::H0=(~B*(~C*D)+B*(~C*D+C*(D*~A))) F1:F F0:F 4 MODE K1 e K0 d REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ' NGID1 6cpu0/regs/ea/SLICE_1116 SLICE R22C20A )
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K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_989 SLICE R23C20B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(~B*D)+A*(D+B)) K0::H0=(~C*(~B*D)+C*(D+B)) F1:F F0:F 4 MODE K1 g K0 f REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 3 NGID1 4cpu0/SLICE_1117 SLICE R9C19D )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~A*(D*C)+A*(~D*B+D*(B+C))) K0::H0=(~C*(D*~A)+C*(A+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_990 SLICE R23C21C )
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~A*(~C*(~D*B)+C*(B+D))+A*B) K0::H0=(~A*(~C*(~D*B)+C*(B+D))+A*B) F1:F F0:F 4 MODE K1 i K0 h REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 < NGID1 ocpu0/regs/SLICE_1118 SLICE R15C33B )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(D*A)+B*(~D*C+D*(C+A))) K0::H0=(~D*(C*~B)+D*(B+C)) F1:F F0:F 4 MODE K1 K0
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_991 SLICE R23C21B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(D*C) K0::H0=(~D*(C*(A*~B))) F1:F F0:F 4 MODE K1 k K0 j REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1119 SLICE R19C30A )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~A*(D*B)+A*(~D*C+D*(C+B))) K0::H0=(~D*(A*~C)+D*(C+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_992 SLICE R17C19C )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~A*B) K0::H0=(~B*(~A*(D*C))) F1:F F0:F 4 MODE K1 m K0 l REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1120 SLICE R16C26C )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~A*(C*D)+A*(~C*B+C*(B+D))) K0::H0=(~B*(C*~A)+B*(A+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Fcpu0/SLICE_993 SLICE R21C21C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~B*(A*D)+B*(~C+D)) K0::H0=(~D*(A*(~B*C))) F1:F F0:F 4 MODE K1 o K0 n REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1121 SLICE R9C18A )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(D*A)+B*(~D*C+D*(C+A))) K0::H0=(~C*(B*~A)+C*(A+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_994 SLICE R23C21A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*B)+D*(~B+C)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 q K0 p REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Q NGID1 Rcpu0/regs/SLICE_1122 SLICE R12C20A )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(D*C)+B*(~D*A+D*(A+C))) K0::H0=(~B*(D*~A)+B*(A+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_995 SLICE R23C22B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~D*(B*C)+D*(~C+B)) F1:F F0:F 4 MODE K1 s K0 r REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 U NGID1 Vcpu0/regs/SLICE_1123 SLICE R12C17D )
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~A*(C*D)+A*(~C*B+C*(B+D))) K0::H0=(~B*(C*~D)+B*(D+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_996 SLICE R21C24B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~C*(D*A)+C*(~A+D)) F1:F F0:F 4 MODE K1 u K0 t REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Y NGID1 Zcpu0/regs/SLICE_1124 SLICE R9C20D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~D*A+D*C) K0::H0=(~B*(D*~C)+B*(C+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_997 SLICE R18C18A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*B)+D*(~B+C)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 w K0 v REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ] NGID1 ^cpu0/regs/SLICE_1125 SLICE R12C17A )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=((~D*C)*~A)*B K0::H0=(~C*(~D*(B*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_998 SLICE R14C23B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~B*(C*D)+B*(~D+C)) F1:F F0:F 4 MODE K1 y K0 x REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 a NGID1 bcpu0/regs/SLICE_1126 SLICE R12C18D )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=((C+B)+D) K0::H0=(~D*(~C*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 >cpu0/SLICE_999 SLICE R14C22D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(D*C)+B*(~C+D)) K0::H0=(~C*(D*A)+C*(~A+D)) F1:F F0:F 4 MODE K1 { K0 z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 fcpu0/regs/SLICE_1127 SLICE R16C19D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*~D)) K0::H0=(~A*(B*C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 " REG0 ! Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 = NGID2 C NGID3 Dcpu0/SLICE_1000 SLICE R23C13C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(C*D)+A*(~D+C)) K0::H0=(~A*(C*B)+A*(~B+C)) F1:F F0:F 4 MODE K1 } K0 | REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 r NGID1 scpu0/regs/SLICE_1128 SLICE R17C18B )
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(~A*(~C*~D)+A*(~D+C)) K0::H0=(~D*(~B*~C)+D*(~B*(~A+~C))) F1:F F0:F 4 MODE K1 $ K0 # REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1001 SLICE R21C22B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(B*D)+A*(~D+B)) K0::H0=(~A*(B*C)+A*(~C+B)) F1:F F0:F 4 MODE K1 K0 ~ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 x NGID1 ycpu0/regs/SLICE_1129 SLICE R16C21C )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~D*C+D*B) K0::H0=(~A*(C*~B)+A*(B+C)) F1:F F0:F 4 MODE K1 & K0 % REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 [cpu0/regs/SLICE_1002 SLICE R21C24D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1130 SLICE R16C20D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~C*(D*~A)+C*(A+D)) F1:F F0:F 4 MODE K1 ( K0 ' REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 _cpu0/SLICE_1003 SLICE R19C25A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*B)+C*(~B+D)) K0::H0=(~C*(D*B)+C*(~B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1131 SLICE R14C25B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*C)+A*(~C+D)) K0::H0=(~D*(B*~C)+D*(C+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 * K0 ) REG1 , REG0 + Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 G NGID2 9 NGID3 :cpu0/regs/SLICE_1004 SLICE R16C23C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C*D)+A*(~D+C)) K0::H0=(~A*(C*D)+A*(~D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_1132 SLICE R14C26A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(C*B)+D*(~B+C)) K0::H0=(~D*(C*~B)+D*(B+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 . K0 - REG1 0 REG0 / Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 U NGID2 NGID3 cpu0/regs/SLICE_1005 SLICE R16C26D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~D*(C*A)+D*(~A+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_1133 SLICE R14C26D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~D*(C*~B)+D*(B+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 2 K0 1 REG1 4 REG0 3 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 V NGID2 NGID3 cpu0/regs/SLICE_1006 SLICE R15C25D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*D)+A*(~D+B)) K0::H0=(~A*(B*C)+A*(~C+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_1134 SLICE R14C24A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~B*(C*~D)+B*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 6 K0 5 REG1 8 REG0 7 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 X NGID2 NGID3 cpu0/regs/SLICE_1007 SLICE R17C22D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*B)+D*(~B+A)) K0::H0=(~D*(A*C)+D*(~C+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_1135 SLICE R16C24B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(C*B)+D*(~B+C)) K0::H0=(~A*(C*~D)+A*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 : K0 9 REG1 < REG0 ; Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Z NGID2 NGID3 cpu0/regs/SLICE_1008 SLICE R16C23D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*B)+C*(~B+A)) K0::H0=(~C*(A*B)+C*(~B+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_1136 SLICE R17C26A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(D*A)+B*(~A+D)) K0::H0=(~D*(C*~B)+D*(B+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 > K0 = REG1 @ REG0 ? Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 \ NGID2 NGID3 cpu0/regs/SLICE_1009 SLICE R15C24B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~C*(D*A)+C*(~A+D)) REG0::::SD=0 Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~B*(C*~D)+B*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 B K0 A REG1 D REG0 C Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ^ NGID2 NGID3 cpu0/regs/SLICE_1010 SLICE R15C25A )
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cpu0/regs/SLICE_1137 SLICE R21C23D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*D)+C*(~D+B)) K0::H0=(~A*(B*~D)+A*(D+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 F K0 E REG1 H REG0 G Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ` NGID2 NGID3 cpu0/regs/SLICE_1011 SLICE R17C22C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(D*C)+A*(~C+D)) K0::H0=(~A*(D*~C)+A*(C+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1138 SLICE R22C24C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(B*A)+D*(~A+B)) K0::H0=(~B*(C*~D)+B*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 J K0 I REG1 L REG0 K Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 b NGID2 NGID3 cpu0/regs/SLICE_1012 SLICE R16C25A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(D*B)+A*(~B+D)) K0::H0=(~C*(D*~B)+C*(B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1139 SLICE R22C34B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~A*(B*~D)+A*(D+B)) REG0::::SD=0 Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 N K0 M REG1 REG0 O Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 k NGID2 cpu0/regs/SLICE_1013 SLICE R14C21C )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(A*(~D*(B*C))) K0::H0=(~A*(~D*(~B*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1140 SLICE R16C13B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C*D)+A*(~D+C)) K0::H0=(~B*(C*~D)+B*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 Q K0 P REG1 S REG0 R Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 l NGID2 NGID3 cpu0/regs/SLICE_1014 SLICE R12C22C )
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~A*(~C*~B)+A*(~B+C)) K0::H0=(~B*(~C*~A)+B*(~A+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 &cpu0/regs/SLICE_1141 SLICE R19C16B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*D)+B*(~D+C)) K0::H0=(~A*(C*~D)+A*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 U K0 T REG1 W REG0 V Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 m NGID2 NGID3 cpu0/regs/SLICE_1015 SLICE R15C24C )
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! " # $ % & ' ( iMODE:LOGIC K1::H1=(~D*(~C*~A+C*(B*~A))+D*(~C+(A+B))) K0::H0=(~B*(~C*~A+C*(D*~A))+B*(~C+(A+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 $ NGID1 )cpu0/regs/SLICE_1142 SLICE R17C15D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~C*(D*~B)+C*(B+D)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 Y K0 X REG1 [ REG0 Z Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 n NGID2 NGID3 cpu0/regs/SLICE_1016 SLICE R16C22D )
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! " # $ % & ' ( iMODE:LOGIC K1::H1=(~A*(~D*~C+D*(B*~C))+A*(~D+(C+B))) K0::H0=(~A*(~D*~B+D*(C*~B))+A*(~D+(B+C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 (cpu0/regs/SLICE_1143 SLICE R19C15C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*B)+A*(~B+D)) K0::H0=(~D*(C*~B)+D*(B+C)) REG0::::SD=0 Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 ] K0 \ REG1 REG0 ^ Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 o NGID2 cpu0/regs/SLICE_1017 SLICE R17C23A )
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! " # $ % & ' ( iMODE:LOGIC K1::H1=(~B*(~C*~D+C*(A*~D))+B*(~C+(D+A))) K0::H0=(~A*(~C*~B+C*(D*~B))+A*(~C+(B+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 & NGID1 'cpu0/regs/SLICE_1144 SLICE R10C22A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(D*C)+B*(~C+D)) K0::H0=(~D*(B*~A)+D*(A+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 ` K0 _ REG1 b REG0 a Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 p NGID2 NGID3 cpu0/regs/SLICE_1018 SLICE R17C25A )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=((A*B)+((A+~D)*~B))*C K0::H0=(D*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 , NGID2 cpu0/regs/SLICE_1145 SLICE R9C18B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(B*C)+D*(~C+B)) K0::H0=(~C*(B*~D)+C*(D+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 d K0 c REG1 f REG0 e Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 q NGID2 NGID3 cpu0/regs/SLICE_1019 SLICE R17C23B )
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! " # $ % & ' ( 0MODE:LOGIC K1::H1=(C*A) K0::H0=(C*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1146 SLICE R16C14D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*D)+C*(~D+A)) K0::H0=(~A*(C*~B)+A*(B+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 h K0 g REG1 j REG0 i Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 r NGID2 NGID3 cpu0/regs/SLICE_1020 SLICE R18C23C )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(C*~D) K0::H0=(~B*(~D+~A)+B*(~D+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 scpu0/alu/SLICE_1147 SLICE R9C24D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*B)+D*(~B+A)) K0::H0=(~B*(A*~C)+B*(C+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 l K0 k REG1 n REG0 m Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 v NGID2 NGID3 cpu0/regs/SLICE_1021 SLICE R14C23C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~C*(D*~A)+C*(B*~A)) K0::H0=(~C*(B*~D)+C*(A*~D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1148 SLICE R9C15D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*D)+C*(~D+A)) K0::H0=(~D*(C*~B)+D*(B+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 p K0 o REG1 r REG0 q Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 s NGID2 NGID3 cpu0/regs/SLICE_1022 SLICE R12C21D )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~D*(~A*B+A*(B*C))+D*(~A*(C+B)+A*(B@C))) K0::H0=(~D*C+D*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 3 NGID1 Xcpu0/alu/SLICE_1149 SLICE R10C13B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*B)+C*(~B+A)) K0::H0=(~A*C+A*B) REG0::::SD=0 Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 t K0 s REG1 REG0 u Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 M NGID2 cpu0/regs/SLICE_1023 SLICE R16C24D )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~C*(~B*D+B*(D*A))+C*(~B*(A+D)+B*(D@A))) K0::H0=(~C*D+C*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 Ycpu0/alu/SLICE_1150 SLICE R12C20C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~D*(C*~A)+D*(A+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 w K0 v REG1 y REG0 x Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 x NGID2 NGID3 cpu0/regs/SLICE_1024 SLICE R15C26C )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~B*(~D*A+D*(A*C))+B*(~D*(C+A)+D*(A@C))) K0::H0=(~B*D+B*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 5 NGID1 Zcpu0/alu/SLICE_1151 SLICE R11C17C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*D)+C*(~D+A)) K0::H0=(~B*(C*~D)+B*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 { K0 z REG1 } REG0 | Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 R NGID2 NGID3 cpu0/SLICE_1025 SLICE R16C21D )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~B*D+B*~A) K0::H0=(~B*D+B*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 6 NGID1 :cpu0/alu/SLICE_1152 SLICE R10C21B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*B)+A*(~B+D)) K0::H0=(~A*(C*~D)+A*(D+C)) REG0::::SD=0 Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 ~ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 u NGID2 cpu0/regs/SLICE_1026 SLICE R18C23D )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~D*(~B*C+B*(C*A))+D*(~B*(A+C)+B*(C@A))) K0::H0=(~A*D+A*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 7 NGID1 [cpu0/alu/SLICE_1153 SLICE R11C13C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*B)+C*(~B+D)) K0::H0=(~A*(C*~D)+A*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Q NGID2 NGID3 cpu0/regs/SLICE_1027 SLICE R16C24B )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~B*(~C*A+C*(A*D))+B*(~C*(D+A)+C*(A@D))) K0::H0=(~B*D+B*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 8 NGID1 \cpu0/alu/SLICE_1154 SLICE R10C16B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(D*C)+B*(~C+D)) K0::H0=(~B*(A*~C)+B*(C+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 w NGID2 NGID3 cpu0/regs/SLICE_1028 SLICE R16C22B )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~C*(~D*B+D*(B*A))+C*(~D*(A+B)+D*(B@A))) K0::H0=(~C*D+C*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 9 NGID1 ]cpu0/alu/alu16/mulu/SLICE_1155 SLICE R21C30A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~B*(C*~D)+B*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ! NGID1 T NGID2 NGID3 cpu0/regs/SLICE_1029 SLICE R19C23B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(C*~B)+A*(B+C)) K0::H0=(~A*(C*~B)+A*(B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1156 SLICE R9C12C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~D*(C*~B)+D*(B+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 y NGID2 NGID3 cpu0/SLICE_1030 SLICE R16C20D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(((C*A)@D)*B)+((C*A)*~B) K0::H0=(A*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 i NGID2 cpu0/alu/SLICE_1157 SLICE R10C23A )
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! " # $ % & ' ( LMODE:LOGIC K1::H1=(~C*(A*(~B*D))+C*((~B+~D)+A)) K0::H0=(~B*A+B*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 & NGID1 cpu0/regs/SLICE_1031 SLICE R15C25C )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*~D)+B*(A*~D)) K0::H0=(~A*(D*~C)+A*(B*~C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE:::CE=#INV SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ^ NGID1 NGID2 c NGID3 bcpu0/alu/SLICE_1158 SLICE R7C14A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(B*A)+D*(~A+B)) K0::H0=(~A*(C*~D)+A*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ' NGID1 P NGID2 NGID3 cpu0/SLICE_1032 SLICE R15C21D )
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! " # $ % & ' ( 0MODE:LOGIC K1::H1=(D*C) K0::H0=(D*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ccpu0/alu/alu8/SLICE_1159 SLICE R9C14B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~A*(C*~D)+A*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 + NGID1 t NGID2 ; NGID3
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~A*B) K0::H0=(~B*C+B*(~A*D+A*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 bcpu0/alu/alu8/SLICE_1160 SLICE R7C15B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(A*B)+D*(~B+A)) K0::H0=(~D*(B*~A)+D*(A+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 - NGID1 S NGID2 NGID3 cpu0/regs/SLICE_1034 SLICE R17C25C )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~A*(~D*C+D*(C+B))+A*(C+B)) K0::H0=(~D*B+D*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/a8/SLICE_1161 SLICE R22C25B )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*C)+A*(~C+D)) K0::H0=(~D*(C*~B)+D*(B+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 1 NGID1 { NGID2 NGID3 cpu0/regs/SLICE_1035 SLICE R16C23B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(D*C)+A*(~C+D)) K0::H0=(~B*(D*~C)+B*(C+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 +cpu0/alu/alu8/a8/SLICE_1162 SLICE R8C20D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~B*(C*~D)+B*(D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 3 NGID1 } NGID2 NGID3 cpu0/regs/SLICE_1036 SLICE R16C24A )
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! " # $ % & ' ( 0MODE:LOGIC K1::H1=(D*C) K0::H0=(~D*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 ?cpu0/alu/alu8/SLICE_1163 SLICE R7C19A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C*D)+A*(~D+C)) K0::H0=(~A*(B*~D)+A*(D+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 8 NGID1 NGID2 NGID3 cpu0/SLICE_1037 SLICE R8C25B )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=C+D+~(B*A) K0::H0=(~C*(B*~D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 R NGID2 cpu0/alu/alu8/SLICE_1164 SLICE R21C23A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*(B*A))+C*(~D+(~B+A))) K0::H0=(~D*C+D*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 9 NGID1 fcpu0/regs/SLICE_1038 SLICE R17C23C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(C*D)+A*(~D+C)) K0::H0=(~B*(C*~D)+B*(D+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 SLICE_1165 SLICE R18C29D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=((D*A)+((D+~C)*~A))*B K0::H0=(C*(D*B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 C NGID1 NGID2 NGID3 NGID4 cpu0/SLICE_1039 SLICE R9C23C )
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! " # $ % & ' ( 0MODE:LOGIC K1::H1=(~A*B) K0::H0=(B*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*(~A*B+A*(~C+B))+D*((B+C)+A)) K0::H0=(~D*(B*A)+D*(~A+B)) REG0::::SD=0 Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 K NGID1 NGID2 cpu0/SLICE_1040 SLICE R17C19B )
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NGID1 SLICE_1166 SLICE R21C29A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*~B)+C*(B+D)) K0::H0=(~D*(B*C)+D*(~C+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 L NGID1 NGID2 5 NGID3 6cpu0/SLICE_1041 SLICE R17C20D )
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! " # $ % & ' ( ,MODE:LOGIC K1::H1=~B K0::H0=(B*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*~D)+C*(D+A)) K0::H0=(~A*(C*B)+A*(~B+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 7 NGID3 8cpu0/SLICE_1042 SLICE R14C23D )
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NGID1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(B*~D)+C*(D+B)) K0::H0=(~A*(B*C)+A*(~C+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 E NGID3 Fcpu0/SLICE_1043 SLICE R9C25B )
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textctrl/SLICE_1167 SLICE R21C29D )
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~D*(C*(~A*B))+D*(~C*(A*B)+C*B)) K0::H0=(~C*(D*A)+C*(~A+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Icpu0/alu/alu16/SLICE_1044 SLICE R14C33C )
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! " # $ % & ' ( 1MODE:LOGIC K1::H1=(~C*~B) K0::H0=(C*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*C+B*A) K0::H0=(~A*D+A*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 1 NGID1 cpu0/alu/alu16/SLICE_1045 SLICE R14C34C )
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NGID1
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*C+B*D) K0::H0=(~A*C+A*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 2 NGID1 cpu0/alu/alu16/SLICE_1046 SLICE R14C34D )
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textctrl/SLICE_1168 SLICE R23C27A )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*C+B*A) K0::H0=(~A*D+A*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 3 NGID1 cpu0/alu/alu16/SLICE_1047 SLICE R16C34D )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(C@A) K0::H0=(C*(B*(A*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~D*C+D*B) K0::H0=(~B*D+B*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 cpu0/alu/alu16/SLICE_1048 SLICE R14C31B )
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NGID1
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*C+B*D) K0::H0=(~B*A+B*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 5 NGID1 cpu0/alu/alu16/SLICE_1049 SLICE R14C34A )
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cpu0/SLICE_1169 SLICE R14C31B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*D+B*C) K0::H0=(~A*D+A*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 6 NGID1 cpu0/alu/alu16/SLICE_1050 SLICE R14C34B )
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! " # $ % & ' ( WMODE:LOGIC K1::H1=(~A*(~B+C)+A*(~C*(~B*~D)+C*~D)) K0::H0=(~D*(~C*A)+D*(A+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1170 SLICE R12C25D )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*C+B*A) K0::H0=(~B*D+B*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 7 NGID1 cpu0/alu/alu16/SLICE_1051 SLICE R14C31C )
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=(~B+~A) K0::H0=(C*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1171 SLICE R16C29A )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*C+B*A) K0::H0=(~A*B+A*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 8 NGID1 cpu0/alu/alu16/SLICE_1052 SLICE R11C31B )
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! " # $ % & ' ( 4MODE:LOGIC K1::H1=(A*C) K0::H0=(~C*B+C*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 O NGID1 rcpu0/SLICE_1172 SLICE R19C27A )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*C+A*B) K0::H0=(~A*C+A*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 9 NGID1 cpu0/alu/alu16/mulu/SLICE_1053 SLICE R17C9C )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(C*(D*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _ NGID1 cpu0/SLICE_1173 SLICE R19C28C )
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(((A+C)+B)+D) K0::H0=(A*(~C*(B*D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 cpu0/alu/alu16/SLICE_1054 SLICE R14C30D )
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=(C*~B) K0::H0=(~B*~D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 f NGID1 cpu0/SLICE_1174 SLICE R18C27C )
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~A*(~D*B)+A*(~D*B+D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1055 SLICE R16C9C )
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! " # $ % & ' ( 4MODE:LOGIC K1::H1=(D*(~B+A)) K0::H0=(A*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 icpu0/SLICE_1175 SLICE R16C27A )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(((D+C)+B)+A) K0::H0=(D*(~A*(~B*~C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1056 SLICE R16C34B )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~D*(C*B)+D*(~C+B)) K0::H0=(~A*(~C*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 : NGID1 cpu0/SLICE_1176 SLICE R18C36D )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(D*C) K0::H0=(~C*(B*D)+C*(~A*(B*D)+A*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1057 SLICE R11C33C )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(D*~C) K0::H0=(~D*(~C*A+C*(B+A))+D*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 J NGID1 {cpu0/dec_regs/SLICE_1177 SLICE R18C35D IMODE:LOGIC K1::H1=(D*(C*(~B*A))) K0::H0=(~D*((A+B)+C)+D*(B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 f NGID1 cpu0/dec_regs/SLICE_1178 SLICE R18C33B )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(D*B) K0::H0=(~A*(B*D)+A*(~C*(B*D)+C*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1058 SLICE R17C32B )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=((C+D)+B) K0::H0=(~B*(C*A)+B*(~C*D+C*(A+D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 j NGID1 cpu0/dec_regs/SLICE_1179 SLICE R7C28C )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(C*D) K0::H0=(~C*(D*B)+C*(~A*(D*B)+A*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1059 SLICE R17C33A )
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! " # $ % & ' ( 0MODE:LOGIC K1::H1=(A*D) K0::H0=(~A*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1180 SLICE R17C36C )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(B*A) K0::H0=(~D*(B*C)+D*(~A*(B*C)+A*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1060 SLICE R17C31D )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~A*~D) K0::H0=(~D*C+D*((A*B)+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 }cpu0/SLICE_1181 SLICE R17C35B )
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(A*B) K0::H0=(~D*(C*B)+D*(~A*(C*B)+A*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_1061 SLICE R22C16B )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(D*(A*(~C*~B))) K0::H0=(~B*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1182 SLICE R21C33D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(~(D+C)*A)*B K0::H0=(C*(A*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ^ NGID1 Y NGID2 ~cpu0/alu/alu16/SLICE_1062 SLICE R16C16A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(D*(~A*(~C*B))) K0::H0=(~B*(~C*(~D*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 +cpu0/SLICE_1183 SLICE R21C25B )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(C*~B) K0::H0=(D*(B*(A*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 b NGID1 cpu0/alu/alu16/SLICE_1063 SLICE R14C33B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(C*D)+A*(~C+D)) K0::H0=(~B*(C*A)+B*(~C+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1184 SLICE R21C23B )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~C*(~D*(A*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 t NGID1 cpu0/alu/alu16/SLICE_1064 SLICE R16C10C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*A)+C*(~D+A)) K0::H0=(~D*(C*A)+D*(~C+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1185 SLICE R18C24B )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~A*(~C*B)) K0::H0=(A*(~D*(~C*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 u NGID1 cpu0/alu/alu16/SLICE_1065 SLICE R14C32B DMODE:LOGIC K1::H1=(~D*(~C*(~B*~A))) K0::H0=(~D*(C*(B*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 v NGID1 |cpu0/alu/alu16/SLICE_1066 SLICE R14C29C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(C*B)+A*(~C+B)) K0::H0=(~B*(C*A)+B*(~C+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1186 SLICE R21C22A )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~D*C+D*B) K0::H0=(~C*(~A*~B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 z NGID1 cpu0/alu/alu16/SLICE_1067 SLICE R14C30A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(C*~D)+A*(D+C)) K0::H0=(~C*(A*D)+C*(~D+A)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~C*D+C*A) K0::H0=(~A*(~D*~B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 { NGID1 cpu0/alu/alu16/SLICE_1068 SLICE R19C9B )
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K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(B*(~D*~A+D*(~C*~A))) K0::H0=(~D*(C*(A*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_1069 SLICE R12C30C )
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cpu0/SLICE_1187 SLICE R22C24B )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~A*(~C*(B@D)+C*(~B*D))) K0::H0=(~D*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_1070 SLICE R12C30D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(A*B)+D*(~B+A)) K0::H0=(~C*(D*B)+C*(~B+D)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~B*(~A*C)+B*(D*(A*~C))) K0::H0=(~D*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_1071 SLICE R19C16B )
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K0
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! " # $ % & ' ( AMODE:LOGIC K1::H1=((~B*~C)*A)*~D K0::H0=((C*(~B*D))+A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 _ NGID2 cpu0/alu/alu16/SLICE_1072 SLICE R9C30A )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1188 SLICE R21C16C )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(A*D) K0::H0=(D*(A*(~C*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_1073 SLICE R11C27C )
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! " # $ % & ' ( TMODE:LOGIC K1::H1=(~B*(A*~D)+B*(D+A)) K0::H0=(~B*(~A*C)+B*(~A*C+A*(C*D))) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~A*B) K0::H0=(~B*(~D*(~A*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/s8/SLICE_1074 SLICE R8C29A )
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K0
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*D+A*B) K0::H0=(~A*B+A*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/a8/SLICE_1075 SLICE R9C27C )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 lcpu0/regs/SLICE_1189 SLICE R14C18C )
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~D*A+D*C) K0::H0=(~D*(~A*C)+D*(A*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/SLICE_1076 SLICE R9C28A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~A*(B*C)+A*(~C+B)) F1:F F0:F 4 MODE K1
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! " # $ % & ' (
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K0
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~A*(~B*D)+A*B) K0::H0=(~C*(~A*~B+A*(D*~B))+C*(~A*(~D*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 hcpu0/alu/alu8/SLICE_1078 SLICE R9C24D )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 n NGID1 tcpu0/regs/SLICE_1190 SLICE R9C21D )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=(C*(A*(~B*~D))) K0::H0=(~C*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 wcpu0/alu/alu8/SLICE_1079 SLICE R11C26C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(D*A)+B*(~A+D)) K0::H0=(~C*(D*A)+C*(~A+D)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(B*(C*(~D*A))) K0::H0=(~A*(B*~C)+A*(~C+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ` NGID1 rcpu0/alu/alu8/SLICE_1080 SLICE R8C28B )
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K0
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(C*~B) K0::H0=(~C*(D*(~A*~B))) F1:F F0:F 4 MODE K1 K0
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1191 SLICE R6C20D )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 s NGID1 cpu0/SLICE_1081 SLICE R19C13D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~A*(D*C)+A*(~C+D)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(~C*~(D+B))*~A K0::H0=(A+B) F1:F F0:F 4 MODE K1
K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ~ NGID1 NGID2 cpu0/alu/SLICE_1082 SLICE R14C28A )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~A*(~C*(~D*B)+C*(B+D))+A*B) K0::H0=(~D*(~A*B)+D*(~A*B+A*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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K0
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cpu0/alu/SLICE_1083 SLICE R16C33A )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1192 SLICE R10C21D )
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! " # $ % & ' ( YMODE:LOGIC K1::H1=(~A*(~D*(~B*C)+D*(C+B))+A*C) K0::H0=(~A*(~C*B)+A*(~C*B+C*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~B*(C*A)+B*(~A+C)) F1:F F0:F 4 MODE K1
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!cpu0/alu/SLICE_1084 SLICE R16C29B )
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K0
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~A*(~C+~B)+A*(~C+B)) K0::H0=(D*(B*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1193 SLICE R14C19C )
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NGID1
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(D*A)+B*(~D*C+D*(C+A))) K0::H0=(~A*(D*C)+A*(~C+D)) F1:F F0:F 4 MODE K1
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cpu0/alu/SLICE_1085 SLICE R16C19D )
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K0
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~C*(~A*B+A*(D+B))+C*(~A*(D+B)+A*B)) K0::H0=(C*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1194 SLICE R23C23A )
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NGID1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(B*C)+D*(~B+C)) K0::H0=(~A*(B*D)+A*(~B+D)) F1:F F0:F 4 MODE K1
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cpu0/SLICE_1086 SLICE R19C9C )
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K0
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(A*(C*(~B+D))) K0::H0=(D*(A*~C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 %cpu0/SLICE_1195 SLICE R23C22B )
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NGID1 cpu0/SLICE_1087 SLICE R18C13B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(D*A)+B*(~D+A)) K0::H0=(~C*(D*B)+C*(~D+B)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*(D+C)+B*((A+D)+C)) K0::H0=(~B*((D*A)+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1088 SLICE R16C11B )
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K0
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! " # $ % & ' ( \MODE:LOGIC K1::H1=(~A*(D*~C)+A*(~D*~B+D*(~B+~C))) K0::H0=(~D*(~A*C)+D*(~A*(B*C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1089 SLICE R19C11A )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 ecpu0/regs/SLICE_1196 SLICE R18C23C )
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! " # $ % & ' (
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(C*D)+B*(~C+D)) K0::H0=(~B*(C*D)+B*(~C+D)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(~D*(~C*~B))) K0::H0=(~B*(~A+(~D+~C))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 ! REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 ` NGID3 acpu0/SLICE_1091 SLICE R15C9D )
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K0
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(B*(~A*(~C*~D))) K0::H0=(~D*C+D*(A+C)) F1:F F0:F 4 MODE K1 # K0 " REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1092 SLICE R21C11C )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1197 SLICE R23C22D )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(D*B)*~A*~C K0::H0=(((C*B)+D)+A) F1:F F0:F 4 MODE K1 % K0 $ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_1093 SLICE R23C15B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(C*D)+B*(~D+C)) K0::H0=(~A*(B*D)+A*(~D+B)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( EMODE:LOGIC K1::H1=((A*B)*D)+(~A*~D) K0::H0=(~A*(C*(~D*B))) F1:F F0:F 4 MODE K1 ' K0 & REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_1094 SLICE R16C11C )
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K0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(((C+B)+D)+A) K0::H0=(A+C) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 ) K0 ( REG1 + REG0 * Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/SLICE_1095 SLICE R11C17B )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 hcpu0/regs/SLICE_1198 SLICE R23C23C )
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! " # $ % & ' ( MMODE:LOGIC K1::H1=(~A*(~D*(C*B))) K0::H0=(~B*(~A*(C*D))+B*(~A*~C)) F1:F F0:F 4 MODE K1 - K0 , REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 cpu0/dec_alu/SLICE_1096 SLICE R9C18B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(A*~B)+C*(B+A)) K0::H0=(~A*(D*B)+A*(~B+D)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( zMODE:LOGIC K1::H1=(~A*(~D*(~C*~B)+D*(C*~B))+A*(~D*(~C+~B)+D*(~C*B))) K0::H0=(~A*(~D*(C@~B)+D*(~B+C))+A*(~D*~C)) F1:F F0:F 4 MODE K1 / K0 . REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ? NGID1 @cpu0/SLICE_1097 SLICE R16C19B )
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K0
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(C*(B*(D*A))) K0::H0=(~A*(D*(~B*C))) F1:F F0:F 4 MODE K1 1 K0 0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 N NGID1 cpu0/SLICE_1098 SLICE R12C16D )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1199 SLICE R18C14A )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~B*(C*(D*~A))) K0::H0=(~B*(C*(D*A))) F1:F F0:F 4 MODE K1 3 K0 2 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 O NGID1 cpu0/dec_op/SLICE_1099 SLICE R15C20C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(B*D)+C*(~D+B)) K0::H0=(~C*(A*B)+C*(~B+A)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( NMODE:LOGIC K1::H1=(~A*(~D*(B*~C))) K0::H0=(~A*((~C+B)+D)+A*(~B*~C)) F1:F F0:F 4 MODE K1 5 K0 4 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/a16/SLICE_1100 SLICE R9C25C )
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K0
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! " # $ % & ' ( WMODE:LOGIC K1::H1=(~D+(~A*~B+A*~C)) K0::H0=(~C*(~B*D+B*(A*D))+C*(~B*(~A*D))) F1:F F0:F 4 MODE K1 7 K0 6 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 $ NGID1 %cpu0/SLICE_1101 SLICE R16C9D )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1200 SLICE R17C13A )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(~D*(~A*(~B*~C))+D*~C) K0::H0=((C+B)+D) F1:F F0:F 4 MODE K1 9 K0 8 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1102 SLICE R15C16D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(A*D)+C*(~D+A)) K0::H0=(~A*(C*D)+A*(~D+C)) F1:F F0:F 4 MODE K1
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! " # $ % & ' (
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K0
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~B*(~A*C)+B*C) K0::H0=(D*(~B*(A*~C))) F1:F F0:F 4 MODE K1 = K0 < REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
NGID1 cpu0/SLICE_1104 SLICE R9C18A )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1201 SLICE R18C14C )
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! " # $ % & ' ( REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ! NGID1 cpu0/SLICE_1105 SLICE R14C14A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(A*D)+B*(~D+A)) K0::H0=(~A*(D*B)+A*(~B+D)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~C*(~D*(A*B))) K0::H0=(~C*(~B*(D*A))) F1:F F0:F 4 MODE K1 A K0 @ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1106 SLICE R12C14D )
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K0
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~D*(~A*~C)) K0::H0=(~B*(D*~A)+B*(~A*C)) F1:F F0:F 4 MODE K1 C K0 B REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1107 SLICE R14C17D )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1202 SLICE R9C25C )
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! " # $ % & ' ( HMODE:LOGIC K1::H1=(~D+(~C*(~A+~B)+C*~B)) K0::H0=(D*(C*(B*A))) F1:F F0:F 4 MODE K1 E K0 D REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_1108 SLICE R12C19A )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~D*(B*~A)+D*(C*~A)) K0::H0=(A*~D) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(D*(B*(A*C))) K0::H0=(B*(C*(D*A))) F1:F F0:F 4 MODE K1 G K0 F REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_1109 SLICE R12C18D )
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K0
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~C*(~A*B)+C*(~A+B)) K0::H0=(~B*(~A*(~D*~C))) F1:F F0:F 4 MODE K1 I K0 H REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1110 SLICE R19C17C )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1203 SLICE R18C14B )
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! " # $ % & ' ( oMODE:LOGIC K1::H1=(~C*(~D*B+D*(B@A))+C*(~D*(B*A)+D*(~B*A))) K0::H0=(~A*(~B*(D*C)+B*(~D+C))+A*(~D+C)) F1:F F0:F 4 MODE K1 K K0 J REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 cpu0/SLICE_1111 SLICE R22C16D )
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(C*~D) K0::H0=(~A*(B*~D)+A*(D+B)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=((~B*D)*C)*A K0::H0=(~B*(~C*A+C*(~D+A))+B*A) F1:F F0:F 4 MODE K1 M K0 L REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 NGID2 cpu0/regs/SLICE_1112 SLICE R17C21B )
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" K0
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~B*(D*~C)+B*(C+D)) K0::H0=(~D*(C*A)+D*(B*A)) F1:F F0:F 4 MODE K1 O K0 N REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 6 NGID1 cpu0/SLICE_1113 SLICE R16C15D )
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! REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 cpu0/alu/SLICE_1204 SLICE R11C17B )
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! " # $ % & ' ( :MODE:LOGIC K1::H1=((A*C)*B)*D K0::H0=(D*(~C*B)) F1:F F0:F 4 MODE K1 Q K0 P REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_1114 SLICE R14C9B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*C+B*D) K0::H0=(~D*C+D*B) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( =MODE:LOGIC K1::H1=((C+B)+D) K0::H0=(A*(D*(~B*~C))) F1:F F0:F 4 MODE K1 S K0 R REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1115 SLICE R17C33B )
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$ K0
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(((D*C)@B)*A)+((D*C)*~A) K0::H0=(A*(C*(D*B))) F1:F F0:F 4 MODE K1 U K0 T REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 s NGID1 r NGID2 cpu0/alu/alu16/mulu/SLICE_1116 SLICE R17C33D )
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# REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 5cpu0/alu/SLICE_1205 SLICE R9C19B )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(A*(B*(D*C))) K0::H0=(D*(C*(B*A))) F1:F F0:F 4 MODE K1 W K0 V REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 t NGID1 ucpu0/alu/alu16/mulu/SLICE_1117 SLICE R17C33C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*C+B*D) K0::H0=(~C*D+C*B) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(D*(B*(A*C))) K0::H0=(D*(C*(A*B))) F1:F F0:F 4 MODE K1 Y K0 X REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 v NGID1 wcpu0/SLICE_1118 SLICE R19C17A )
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& K0
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~A*(~D*(~B*C))) K0::H0=(~A*(~D*(~B*C))) F1:F F0:F 4 MODE K1 [ K0 Z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 f NGID1 cpu0/alu/alu16/SLICE_1119 SLICE R12C29D )
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% REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 # NGID1 4cpu0/alu/SLICE_1206 SLICE R7C18C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=((~D*A)*C)+(((~D*A)*~B)*~C) K0::H0=(~B*(A*~D)) F1:F F0:F 4 MODE K1 ] K0 \ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/alu/alu8/s8/SLICE_1120 SLICE R9C30C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~C*B+C*A) K0::H0=(~B*C+B*D) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*B+D*(~C*A+C*B)) K0::H0=(~C*D+C*(~A*B+A*D)) F1:F F0:F 4 MODE K1 _ K0 ^ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/SLICE_1121 SLICE R11C28A )
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( K0
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(~D*(C*(~B*~A))) K0::H0=(~D*(B*~A)) F1:F F0:F 4 MODE K1 a K0 ` REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 u NGID1 vcpu0/alu/SLICE_1122 SLICE R19C29A )
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' REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 $ NGID1 2cpu0/alu/SLICE_1207 SLICE R8C16B )
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! " # $ % & ' ( cMODE:LOGIC K1::H1=((((A*B)*C)+(~B*~C))*D)+((~B*~C)*~D) K0::H0=(~B*~D+B*(~A*~D+A*(~D+C))) F1:F F0:F 4 MODE K1 c K0 b REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*C+B*D) K0::H0=(~C*A+C*D) F1:F F0:F 4 MODE K1
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" NGID1 NGID2
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* K0
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cpu0/SLICE_1123 SLICE R19C11D )
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) REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 1cpu0/alu/SLICE_1208 SLICE R7C21C )
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! " # $ % & ' ( JMODE:LOGIC K1::H1=(~A*C+A*(~D*(C+B)+D*C)) K0::H0=((A*(~C*B))+D) F1:F F0:F 4 MODE K1 e K0 d REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1124 SLICE R22C11B )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~C*A+C*B) K0::H0=(~A*C+A*D) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( BMODE:LOGIC K1::H1=((~D*B)*C)*A K0::H0=((A*C)*D)+(~A*~D) F1:F F0:F 4 MODE K1 g K0 f REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/regs/SLICE_1125 SLICE R10C23A )
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, K0
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~A*~D)*B K0::H0=((~A*B)+((~A+~D)*~B))*C F1:F F0:F 4 MODE K1 i K0 h REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 NGID3 cpu0/alu/SLICE_1126 SLICE R19C30B mMODE:LOGIC K1::H1=((((A*B)*C)+(~B*~C))*D)+((~B*~C)*~D) K0::H0=((((A*B)*C)+(~B*~C))*D)+((~B*~C)*~D) F1:F F0:F 4 MODE K1 k K0 j REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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+ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 & NGID1 cpu0/alu/alu16/SLICE_1209 SLICE R7C15D )
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NGID2 NGID3
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! " # $ % & ' ( 4MODE:LOGIC K1::H1=(B*D) K0::H0=(~A*D+A*C) F1:F F0:F 4 MODE K1
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cpu0/alu/SLICE_1127 SLICE R18C30D mMODE:LOGIC K1::H1=((((A*B)*C)+(~B*~C))*D)+((~B*~C)*~D) K0::H0=((((A*B)*C)+(~B*~C))*D)+((~B*~C)*~D) F1:F F0:F 4 MODE K1 m K0 l REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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. K0
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NGID2 NGID3
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- REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ' NGID1 cpu0/alu/alu16/a16/SLICE_1210 SLICE R8C17D )
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textctrl/SLICE_1128 SLICE R24C10C )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*D+B*C) K0::H0=(~B*C+B*D) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( /MODE:LOGIC K1::H1=(A*D) K0::H0=(D+A) F1:F F0:F 4 MODE K1 o K0 n REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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0 K0
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NGID1
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/ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ( NGID1 )cpu0/alu/SLICE_1211 SLICE R11C17D )
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cpu0/SLICE_1129 SLICE R17C11A )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~B*C+B*~D) K0::H0=(~B*D+B*~C) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(B+C) K0::H0=(~D*(B*A)+D*(~B*C+B*(A+C))) F1:F F0:F 4 MODE K1 q K0 p REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1130 SLICE R16C13B )
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2 K0
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~A*(~C*(B*D))) K0::H0=(~C*(~A*B)) F1:F F0:F 4 MODE K1 s K0 r REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1131 SLICE R18C17B )
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1 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 : NGID1 =cpu0/alu/SLICE_1212 SLICE R11C15B )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~C*(~A+~B)+C*~A) K0::H0=(C*A) F1:F F0:F 4 MODE K1 u K0 t REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1132 SLICE R12C20D )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~A*D+A*~C) K0::H0=(~D*C+D*~A) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( 4MODE:LOGIC K1::H1=(B@(~D+C)) K0::H0=(B@D) F1:F F0:F 4 MODE K1 w K0 v REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 P NGID1 cpu0/SLICE_1133 SLICE R11C19A )
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4 K0
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! " # $ % & ' ( 7MODE:LOGIC K1::H1=(B*(D*(A*C))) K0::H0=(C*D) F1:F F0:F 4 MODE K1 y K0 x REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 U NGID1 cpu0/dec_alu/SLICE_1134 SLICE R11C20C )
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3 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ; NGID1
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! " # $ % & ' ( 1MODE:LOGIC K1::H1=(~D*~B) K0::H0=(B+D) F1:F F0:F 4 MODE K1 { K0 z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 V NGID1 Wcpu0/SLICE_1135 SLICE R15C16B )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~C*D+C*~A) K0::H0=(~D*A+D*~C) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(D*(~C*(A*~B))) K0::H0=(~A+~B) F1:F F0:F 4 MODE K1 } K0 | REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 X NGID1 cpu0/SLICE_1136 SLICE R22C15C )
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6 K0
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=(A*~C) K0::H0=(~A*~C) F1:F F0:F 4 MODE K1 K0 ~ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1137 SLICE R15C12D )
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5 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 < NGID1 ;cpu0/alu/SLICE_1214 SLICE R12C14B )
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! " # $ % & ' ( 4MODE:LOGIC K1::H1=(A*(~D*B)) K0::H0=(A*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 !cpu0/SLICE_1138 SLICE R15C18A )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~B*D+B*~C) K0::H0=(~B*D+B*~A) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~C*(~A*(B*D))) K0::H0=(~A*~B+A*(~C*(~D*~B)+C*~B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1139 SLICE R10C17B )
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8 K0
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! " # $ % & ' ( 5MODE:LOGIC K1::H1=(C*~A) K0::H0=(~D*(C@A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_1140 SLICE R12C19B )
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7 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 = NGID1 9cpu0/alu/SLICE_1215 SLICE R10C16C )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(D*A) K0::H0=(~C*D+C*(~A*(B+D)+A*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 r NGID1 cpu0/SLICE_1141 SLICE R11C16B )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~A*C+A*~D) K0::H0=(~A*C+A*~B) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( PMODE:LOGIC K1::H1=(~B*~D) K0::H0=(~C*(~D*B+D*(A+B))+C*(~D*(A+B)+D*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 cpu0/dec_regs/SLICE_1142 SLICE R10C19D )
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: K0
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! " # $ % & ' ( 4MODE:LOGIC K1::H1=(~A*C) K0::H0=(D*(A*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_1143 SLICE R12C15C )
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9 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 8cpu0/alu/SLICE_1216 SLICE R11C15C )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(~A*~C*~B)*D K0::H0=(~D*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/SLICE_1144 SLICE R17C9D )
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~A*C+A*~D) K0::H0=(~A*D+A*~B) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(D*(A*(B*~C))) K0::H0=(A*B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Fcpu0/SLICE_1145 SLICE R19C12B )
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< K0
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(A*(B*(C*~D))) K0::H0=(B*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_1146 SLICE R22C11D 1MODE:LOGIC K1::H1=(B*A) K0::H0=(~B*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1147 SLICE R18C13C )
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; REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ? NGID1 7cpu0/alu/alu16/a16/SLICE_1217 SLICE R9C15C )
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=((C*A)*B)*~D K0::H0=(~D*~A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 I NGID2 hcpu0/regs/ea/SLICE_1148 SLICE R22C14B )
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=~D K0::H0=(~C*A+C*~D) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( BMODE:LOGIC K1::H1=((~D*A)*~C)*B K0::H0=(~C*(~A*(~D*B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 + NGID2 cpu0/SLICE_1149 SLICE R22C29A )
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> K0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*A+C*(~B*A+B*D)) K0::H0=(~A*D+A*(~B*D+B*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 $ NGID1 cpu0/SLICE_1150 SLICE R17C28A )
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= REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @ NGID1 cpu0/alu/alu16/a16/SLICE_1218 SLICE R10C16D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*A+C*(~B*A+B*D)) K0::H0=(~C*A+C*(~B*A+B*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 % NGID1 cpu0/SLICE_1151 SLICE R17C28C )
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=~A K0::H0=(~C*D+C*~A) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*A+B*(~D*A+D*C)) K0::H0=(~A*B+A*(~D*B+D*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 & NGID1 cpu0/SLICE_1152 SLICE R24C22C )
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@ K0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*D+B*(~C*D+C*A)) K0::H0=(~B*A+B*(~C*A+C*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ( NGID1 cpu0/SLICE_1153 SLICE R24C23B )
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? REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 A NGID1 cpu0/alu/SLICE_1219 SLICE R11C12C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*D+B*(~A*D+A*C)) K0::H0=(~B*C+B*(~A*C+A*D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ) NGID1 cpu0/SLICE_1154 SLICE R15C28A )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=~D K0::H0=(~B*(C@A)+B*(D@(C@A))) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~A*(~D*(B*C)+D*(~B+C))+A*C) K0::H0=(~C*(~A*(B*D)+A*(~B+D))+C*D) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 / NGID1 cpu0/SLICE_1155 SLICE R16C27A )
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B K0
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~D*(~B*(C*A)+B*(~C+A))+D*A) K0::H0=(~D*(~A*(B*C)+A*(~B+C))+D*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 0 NGID1 cpu0/SLICE_1156 SLICE R16C21C )
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A REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1220 SLICE R10C12B )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*(A*C)+D*(B*C)) K0::H0=(~D*(A*C)+D*(B*C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 3 NGID1 cpu0/SLICE_1157 SLICE R16C21A )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=~D K0::H0=(~D*(A@C)+D*(B@(A@C))) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*(C*B)+D*(A*B)) K0::H0=(~D*(C*B)+D*(A*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 4 NGID1 cpu0/SLICE_1158 SLICE R16C20A )
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D K0
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*(B*C)+D*(A*C)) K0::H0=(~B*(D*A)+B*(C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 5 NGID1 gcpu0/SLICE_1159 SLICE R16C20C )
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C REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1221 SLICE R11C12D )
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*(C*D)+B*(A*D)) K0::H0=(~B*(D*A)+B*(C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 7 NGID1 |cpu0/regs/ea/SLICE_1160 SLICE R16C20B )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=~D K0::H0=(~D*(C@B)+D*(A@(C@B))) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~C*(D*B)+C*(A*B)) K0::H0=(~C*(B*A)+C*(D*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 8 NGID1
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F K0
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*(A*B)+D*(C*B)) K0::H0=(~D*(B*A)+D*(C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 9 NGID1 ;cpu0/SLICE_1162 SLICE R17C12C )
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E REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1222 SLICE R12C12D )
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! " # $ % & ' ( [MODE:LOGIC K1::H1=(~A*(B*D)+A*(~B*C+B*(D+C))) K0::H0=(~A*(B*D)+A*(~B*C+B*(D+C))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1163 SLICE R21C15A )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=~C K0::H0=(~C*(B@D)+C*(A@(B@D))) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~D*(~C*(~B*~A))) K0::H0=(~D*(~B*(C*A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1164 SLICE R22C19D )
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H K0
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(~A*(~C*D)+A*~C) K0::H0=(~A*(~C*D)+A*~C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1165 SLICE R23C21D )
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G REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1223 SLICE R11C13A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(~C*D)+A*(D+C)) K0::H0=(~C*(A*~D)+C*(D+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 $cpu0/regs/ea/SLICE_1166 SLICE R24C21D )
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! " # $ % & ' ( 5MODE:LOGIC K1::H1=~D K0::H0=(~D*B+D*(C@B)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~C*D)+B*(D+C)) K0::H0=(~D*(B*~C)+D*(C+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 "cpu0/regs/ea/SLICE_1167 SLICE R22C21B )
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J K0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~D*C)+B*(C+D)) K0::H0=(~C*(B*~D)+C*(D+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 %cpu0/regs/ea/SLICE_1168 SLICE R24C21C )
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I REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1224 SLICE R9C13D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(~D*B)+A*(B+D)) K0::H0=(~A*(C*~D)+A*(D+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 &cpu0/regs/ea/SLICE_1169 SLICE R22C22D )
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! " # $ % & ' ( ,MODE:LOGIC K1::H1=~C K0::H0=(B*C) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~B*(~D*C)+B*(C+D)) K0::H0=(~C*(B*~D)+C*(D+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 #cpu0/regs/ea/SLICE_1170 SLICE R24C22A )
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L K0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*~A)+C*(A+D)) K0::H0=(~C*(B*~A)+C*(A+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1171 SLICE R22C20C )
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K REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1225 SLICE R9C13B )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(~D*~B)+C*(~B+D)) K0::H0=(~C*(~D+~B)+C*~B) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 /cpu0/regs/ea/SLICE_1172 SLICE R24C20C KMODE:LOGIC K1::H1=(~C*(B*A)+C*(~A+B)) K0::H0=(~C*(B*A)+C*(~A+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ' NGID1 .cpu0/regs/ea/SLICE_1173 SLICE R24C20B )
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! " # $ % & ' ( ,MODE:LOGIC K1::H1=~B K0::H0=(B*D) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(A*B)+D*(~B+A)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ( NGID1 -cpu0/regs/ea/SLICE_1174 SLICE R24C19D )
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N K0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~A*(D*C)+A*(~C+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ) NGID1 ,cpu0/regs/ea/SLICE_1175 SLICE R23C20D )
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M REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1226 SLICE R11C13D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(A*D)+C*(~D+A)) K0::H0=(~C*(A*D)+C*(~D+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1 +cpu0/SLICE_1176 SLICE R22C19A )
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! " # $ % & ' ( ,MODE:LOGIC K1::H1=~D K0::H0=(D*C) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( eMODE:LOGIC K1::H1=(~C*(~B+~D)+C*(~B*~A+B*(~D*~A))) K0::H0=(~C*(~B+~A)+C*(~B*~D+B*(~A*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 6 NGID1 cpu0/SLICE_1177 SLICE R22C17B )
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P K0
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! " # $ % & ' ( eMODE:LOGIC K1::H1=(~D*(~A+~C)+D*(~A*~B+A*(~C*~B))) K0::H0=(~D*(~C+~A)+D*(~C*~B+C*(~A*~B))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 8 NGID1 cpu0/SLICE_1178 SLICE R22C19C )
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O REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1227 SLICE R11C13B )
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! " # $ % & ' ( eMODE:LOGIC K1::H1=(~D*(~C+~B)+D*(~C*~A+C*(~B*~A))) K0::H0=(~D*(~B+~C)+D*(~B*~A+B*(~C*~A))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 : NGID1 cpu0/SLICE_1179 SLICE R23C19C )
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! " # $ % & ' ( ,MODE:LOGIC K1::H1=~C K0::H0=(C*A) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( eMODE:LOGIC K1::H1=(~C*(~B+~A)+C*(~B*~D+B*(~A*~D))) K0::H0=(~C*(~B+~A)+C*(~B*~D+B*(~A*~D))) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 < NGID1 cpu0/regs/SLICE_1180 SLICE R16C33D )
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R K0
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! " # $ % & ' ( ]MODE:LOGIC K1::H1=(~B*(~C*(~D*A)+C*(A+D))+B*A) K0::H0=(~B*(~D*(~C*A)+D*(A+C))+B*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 A NGID1 cpu0/SLICE_1181 SLICE R22C29D )
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Q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1228 SLICE R10C11A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*A+D*(~C*A+C*B)) K0::H0=(~B*D+B*(~C*D+C*A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1182 SLICE R23C28D )
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! " # $ % & ' ( /MODE:LOGIC K1::H1=(D*C) K0::H0=(D*A) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*D+A*(~B*D+B*C)) K0::H0=(~A*C+A*(~D*C+D*B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 xcpu0/regs/SLICE_1183 SLICE R12C27A )
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T K0
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(D*B)+C*(~B+D)) K0::H0=(~C*(A*D)+C*(~D+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [ NGID1 \ NGID2 NGID3 cpu0/regs/SLICE_1184 SLICE R12C27B )
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S REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1229 SLICE R15C25A )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*B)+A*(~B+D)) K0::H0=(~D*(A*C)+D*(~C+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ] NGID1 ^ NGID2 NGID3 cpu0/regs/SLICE_1185 SLICE R12C21C )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~D*A+D*(A+B)) K0::H0=(~C*D+C*(D+B)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*B)+D*(~B+C)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 _ NGID1 `cpu0/regs/SLICE_1186 SLICE R9C23B )
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V K0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*B)+C*(~B+D)) K0::H0=(~C*(D*B)+C*(~B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 a NGID1 bcpu0/regs/SLICE_1187 SLICE R11C25C )
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U REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 " NGID1 cpu0/alu/alu8/SLICE_1230 SLICE R7C21A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(B*A)+D*(~A+B)) K0::H0=(~D*(B*A)+D*(~A+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 c NGID1 dcpu0/regs/SLICE_1188 SLICE R12C24D )
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(~B*A+B*(~D*A+D*C)) K0::H0=(~D*(B*A)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(B*C)+D*(~C+B)) K0::H0=(~D*(B*A)+D*(~A+B)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 fcpu0/regs/SLICE_1189 SLICE R12C25B )
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X K0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~C*(D*A)+C*(~A+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 g NGID1 hcpu0/regs/SLICE_1190 SLICE R12C24B )
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W REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Bcpu0/alu/SLICE_1231 SLICE R12C24A )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*B)+C*(~B+D)) K0::H0=(~C*(D*A)+C*(~A+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 i NGID1 jcpu0/regs/SLICE_1191 SLICE R11C24B )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~C*D+C*(D+B)) K0::H0=(~C*D+C*(D+A)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 k NGID1 lcpu0/regs/SLICE_1192 SLICE R12C26C )
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Z K0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~D*(C*B)+D*(~B+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 m NGID1 ncpu0/regs/SLICE_1193 SLICE R10C22D )
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Y REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1232 SLICE R15C23D )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~D*(C*A)+D*(~A+C)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 o NGID1 pcpu0/regs/SLICE_1194 SLICE R10C22C )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~D*C+D*(C+A)) K0::H0=(~D*C+D*(C+B)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~C*(D*B)+C*(~B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 q NGID1 rcpu0/regs/SLICE_1195 SLICE R9C25D )
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\ K0
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(A*C)+D*(~C+A)) K0::H0=(~D*(A*B)+D*(~B+A)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 s NGID1 tcpu0/regs/SLICE_1196 SLICE R9C24B )
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[ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1233 SLICE R15C25C )
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~C*(D*B)+C*(~B+D)) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 u NGID1 vcpu0/regs/SLICE_1197 SLICE R23C25D )
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~A*C+A*(C+D)) K0::H0=(~A*D+A*(D+C)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~D*B+D*C) K0::H0=(~D*B+D*C) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1198 SLICE R24C26B )
|
^ K0
|
! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~D*B+D*A) K0::H0=(~D*B+D*A) F1:F F0:F 4 MODE K1 K0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1199 SLICE R24C26D )
|
] REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1234 SLICE R16C23A )
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*A+B*D) K0::H0=(~B*A+B*C) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(~C*D+C*(D+B)) K0::H0=(~C*D+C*(D+B)) F1:F F0:F 4 MODE K1
|
K0
|
` K0
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1200 SLICE R19C28C )
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_ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/SLICE_1235 SLICE R14C17A )
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! " # $ % & ' ( gMODE:LOGIC K1::H1=(~C*(~B*(~A*D)+B*~A)+C*((D+A)+B)) K0::H0=(~A*(~D*(~B*C)+D*~B)+A*((C+B)+D)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( 4MODE:LOGIC K1::H1=(C*B) K0::H0=(~B*D+B*C) F1:F F0:F 4 MODE K1
|
K0
|
b K0
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1201 SLICE R18C27A )
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a REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 Acpu0/alu/SLICE_1236 SLICE R12C22D )
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! " # $ % & ' ( aMODE:LOGIC K1::H1=(~D*(~A*(~C*B)+A*~C)+D*((B+C)+A)) K0::H0=(~D*(~A*(B+C))+D*((B+C)+A)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~D*(~C*A)+D*(~C*A+C*B)) K0::H0=(~B*(~D*~A)) F1:F F0:F 4 MODE K1
|
K0
|
d K0
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1202 SLICE R19C29D )
|
c REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 j NGID1 cpu0/alu/alu16/mulu/SLICE_1237 SLICE R22C32B )
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! " # $ % & ' ( gMODE:LOGIC K1::H1=(~A*(~D*(~C*B)+D*~C)+A*((B+C)+D)) K0::H0=(~A*(~D*(~C*B)+D*~C)+A*((B+C)+D)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( UMODE:LOGIC K1::H1=(~B*(~A+~D)+B*(~A*~C+A*(~D*~C))) K0::H0=(~C*(~D*(~A*B))) F1:F F0:F 4 MODE K1
|
K0
|
f K0
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1203 SLICE R17C27B MODE:LOGIC K1::H1=(~D+(~C*A+C*B)) K0::H0=(~D+(~C*A+C*B)) REG0::::SD=0 Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M0MUX:M0 REGMODE:FF 4 MODE K1
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e REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_regs/SLICE_1238 SLICE R12C26D )
|
K0
|
! " # $ % & ' ( 7MODE:LOGIC K1::H1=(A*(D*(B*C))) K0::H0=(C+D) F1:F F0:F 4 MODE K1
|
REG1 REG0
|
h K0
|
|
g REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 q NGID1 cpu0/SLICE_1239 SLICE R21C34D )
|
Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_1204 SLICE R16C26C )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=((A*(B*~D))+C) K0::H0=(~B*(~A*(~D+~C))) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( CMODE:LOGIC K1::H1=(~C+(~D*A+D*B)) K0::H0=(~A+(~B*D+B*C)) F1:F F0:F 4 MODE K1
|
j K0
|
K0
|
i REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 textctrl/SLICE_1240 SLICE R23C30B )
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1205 SLICE R22C27B )
|
! " # $ % & ' (
|
! " # $ % & ' ( CMODE:LOGIC K1::H1=(~C+(~A*B+A*D)) K0::H0=(~B+(~A*D+A*C)) F1:F F0:F 4 MODE K1
|
l K0
|
K0
|
k REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1206 SLICE R19C22A )
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NGID1
|
! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(D*B)+A*(~D*C+D*(C+B))) K0::H0=(~D*(C*B)+D*(~C*A+C*(A+B))) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
|
cpu0/regs/SLICE_1241 SLICE R8C21D )
|
K0
|
! " # $ % & ' ( =MODE:LOGIC K1::H1=(~D*(B*A)+D*(~A+B)) K0::H0=(D+C) F1:F F0:F 4 MODE K1
|
REG1
|
n K0
|
REG0
|
m REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1242 SLICE R18C24C )
|
Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 S NGID3 Tcpu0/regs/SLICE_1207 SLICE R11C21B )
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~B*D+B*C) K0::H0=(A*(~B*(~C*~D))) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=(A*~D)*C K0::H0=(D*A) F1:F F0:F 4 MODE K1
|
p K0
|
K0
|
o REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1243 SLICE R21C35A )
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2 cpu0/regs/SLICE_1208 SLICE R10C21B )
|
! " # $ % & ' ( CMODE:LOGIC K1::H1=(A*(~C*(~B*D))) K0::H0=(C*(~D*(~A*B))) F1:F F0:F 4 MODE K1
|
! " # $ % & ' ( 0MODE:LOGIC K1::H1=(A*~D) K0::H0=(A*D) F1:F F0:F 4 MODE K1
|
r K0
|
K0
|
q REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1244 SLICE R21C19D )
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1209 SLICE R19C10D )
|
! " # $ % & ' ( LMODE:LOGIC K1::H1=(~A*(~B+~C)+A*~C) K0::H0=(~C*(A+B)+C*((A+B)+D)) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( EMODE:LOGIC K1::H1=(C@D) K0::H0=(~C*(D*(B*A))+C*(~D*(B*A))) F1:F F0:F 4 MODE K1
|
t K0
|
K0
|
s REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 -cpu0/SLICE_1245 SLICE R16C14B )
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1210 SLICE R18C9C )
|
! " # $ % & ' ( MMODE:LOGIC K1::H1=(~D*(B*C)+D*(~C+B)) K0::H0=(~C*(~B*~D)+C*(~D+B)) F1:F F0:F 4 MODE K1
|
! " # $ % & ' ( 6MODE:LOGIC K1::H1=(~A*~D) K0::H0=(A*(C*~D)) F1:F F0:F 4 MODE K1
|
v K0
|
K0
|
u REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ~ NGID1 cpu0/SLICE_1246 SLICE R12C28A )
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 E NGID1 cpu0/SLICE_1211 SLICE R16C24C )
|
! " # $ % & ' ( FMODE:LOGIC K1::H1=((D*(A*B))+C) K0::H0=(~B*(D*(~A+~C))+B*D) F1:F F0:F 4 MODE K1
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*A)) K0::H0=(~B+C) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
|
x K0
|
K0
|
w REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1247 SLICE R17C30C )
|
REG1
|
! " # $ % & ' ( QMODE:LOGIC K1::H1=(~A*(~B*(~C+D))+A*(~B*~C)) K0::H0=(~D*B+D*(A*(C*B))) F1:F F0:F 4 MODE K1
|
REG0
|
z K0
|
Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1
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y REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 +cpu0/SLICE_1248 SLICE R16C24D )
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NGID2 NGID3 cpu0/SLICE_1212 SLICE R23C18D )
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(C*D)+A*(~D+C)) K0::H0=(~A*(D*C)+A*(~C+D)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
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! " # $ % & ' ( eMODE:LOGIC K1::H1=(~C*(~B+~A)+C*(~B*~D+B*(~A*~D))) K0::H0=(~C*(~B+~D)+C*(~B*~A+B*(~D*~A))) F1:F F0:F 4 MODE K1
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| K0
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K0
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{ REG1
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1213 SLICE R23C17B )
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~ REG0
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! " # $ % & ' ( eMODE:LOGIC K1::H1=(~C*(~B+~D)+C*(~B*~A+B*(~D*~A))) K0::H0=(~C*(~B+~D)+C*(~B*~A+B*(~D*~A))) F1:F F0:F 4 MODE K1
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} Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 v NGID1 p NGID2 NGID3 data_io[0] PIO PT9A {TRIMUX:PADDT IOBUF:::PULLMODE=NONE,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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" K0
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PAD
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! REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/SLICE_1214 SLICE R15C29D )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 cpuclk_o PIO PB29B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~C*(~B*A+B*(A*D))+C*(~B*(D+A)+B*(A@D))) K0::H0=(~C*B+C*~A) F1:F F0:F 4 MODE K1
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PAD
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% K0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 clk40_i PIO PL22A NPADDI:PADDI IOBUF:::PULLMODE=DOWN,CLAMP=ON VREF:OFF PGMUX:INBUF INRDMUX:PGMUX
PADDI TRIMUX IOBUF
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# REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 : NGID1 cpu0/alu/SLICE_1215 SLICE R15C32B )
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PAD
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~D*(~A*B+A*(B*C))+D*(~A*(C+B)+A*(B@C))) K0::H0=(~C*B+C*~D) F1:F F0:F 4 MODE K1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 blue_o PIO PR24A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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' K0
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PAD
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& REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ; NGID1 cpu0/alu/SLICE_1216 SLICE R15C29A )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID 0 NGID0 green_o PIO PR23A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~D*(~A*B+A*(B*C))+D*(~A*(C+B)+A*(B@C))) K0::H0=(~D*A+D*~B) F1:F F0:F 4 MODE K1
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PAD
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) K0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID / NGID0 red_o PIO PR21A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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( REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 < NGID1 cpu0/alu/SLICE_1217 SLICE R14C30C )
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PAD
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~A*(~C*B+C*(B*D))+A*(~C*(D+B)+C*(B@D))) K0::H0=(~A*D+A*~B) F1:F F0:F 4 MODE K1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID . NGID0 vsync_o PIO PR23B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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+ K0
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PAD
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* REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 > NGID1 cpu0/alu/SLICE_1218 SLICE R15C29C )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID - NGID0 vsync_o_MGIOL IOLOGIC IOL_R23B GSR:DISABLED SRMODE:LSR_OVER_CE OUTREG:::GSR=DISABLED IOLDO:IOLDO MODE:IREG_OREG CEOMUX:1 LSROMUX:LSRMUX CLKOMUX:CLK OPOSMUX:OPOS LSRMUX:LSR GSR CEIMUX SRMODE OUTREG
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~D*(~A*C+A*(C*B))+D*(~A*(B+C)+A*(C@B))) K0::H0=(~D*B+D*~C) F1:F F0:F 4 MODE K1
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TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX hsync_o PIO PR24B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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- K0
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PAD
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, REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ? NGID1 cpu0/alu/SLICE_1219 SLICE R16C33C )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID , NGID0 hsync_o_MGIOL IOLOGIC IOL_R24B GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:1 LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS GSR CEIMUX SRMODE OUTREG
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! " # $ % & ' ( XMODE:LOGIC K1::H1=(~D*(~C*B+C*(B*A))+D*(~C*(A+B)+C*(B@A))) K0::H0=(~C*D+C*~B) F1:F F0:F 4 MODE K1
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TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[7] PIO PR2A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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/ K0
|
PAD
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. REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 @ NGID1 cpu0/alu/alu16/mulu/SLICE_1220 SLICE R14C10A )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID $ NGID0 leds_o[7]_MGIOL IOLOGIC IOL_R2A GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG
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! " # $ % & ' ( AMODE:LOGIC K1::H1=(B*(A*~D)) K0::H0=((~B*A+B*(A+C))+D) F1:F F0:F 4 MODE K1
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TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[6] PIO PR2B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
|
1 K0
|
PAD
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0 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1221 SLICE R17C35C )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID % NGID0 leds_o[6]_MGIOL IOLOGIC IOL_R2B GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG
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! " # $ % & ' ( BMODE:LOGIC K1::H1=(((C*D)@B)*A)+((C*D)*~A) K0::H0=(D*A) F1:F F0:F 4 MODE K1
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TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[5] PIO PR3A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
|
3 K0
|
PAD
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2 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 q NGID2 cpu0/alu/SLICE_1222 SLICE R10C27B )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID & NGID0 leds_o[5]_MGIOL IOLOGIC IOL_R3A GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG
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! " # $ % & ' ( 6MODE:LOGIC K1::H1=(~C*D) K0::H0=(C*(~A*~D)) F1:F F0:F 4 MODE K1
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TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[4] PIO PR3B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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5 K0
|
PAD
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4 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 }cpu0/alu/alu8/SLICE_1223 SLICE R11C27B )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID ' NGID0 leds_o[4]_MGIOL IOLOGIC IOL_R3B GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(B*D) K0::H0=(~D*C+D*(~B*A+B*C)) F1:F F0:F 4 MODE K1
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TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[3] PIO PR5A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
|
7 K0
|
PAD
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6 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 |cpu0/alu/alu8/SLICE_1224 SLICE R10C27C )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID ( NGID0 leds_o[3]_MGIOL IOLOGIC IOL_R5A GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG
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! " # $ % & ' ( `MODE:LOGIC K1::H1=(~D*(~B*A+B*(A*C))+D*(~B*(C+A)+B*(A@C))) K0::H0=(~D*C+D*(~B*A+B*C)) F1:F F0:F 4 MODE K1
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TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[2] PIO PR5B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
|
9 K0
|
PAD
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8 REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/s8/SLICE_1225 SLICE R8C26B )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID ) NGID0 leds_o[2]_MGIOL IOLOGIC IOL_R5B GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~B*C+B*D) F1:F F0:F 4 MODE K1
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TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[1] PIO PR7A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
|
; K0
|
PAD
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: REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/SLICE_1226 SLICE R23C18A )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID * NGID0 leds_o[1]_MGIOL IOLOGIC IOL_R7A GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG
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! " # $ % & ' ( eMODE:LOGIC K1::H1=(~C*(~B+~A)+C*(~B*~D+B*(~A*~D))) K0::H0=(~C*(~B+~A)+C*(~B*~D+B*(~A*~D))) F1:F F0:F 4 MODE K1
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TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[0] PIO PR7B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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= K0
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PAD
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< REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1227 SLICE R16C11A )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID + NGID0 leds_o[0]_MGIOL IOLOGIC IOL_R7B GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG
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! " # $ % & ' ( NMODE:LOGIC K1::H1=((~D*(B*C)+D*C)+A) K0::H0=(~B*(~D*(A*C)+D*A)+B*A) F1:F F0:F 4 MODE K1
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TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX state_o[5] PIO PB31B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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? K0
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PAD
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> REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 textctrl/SLICE_1228 SLICE R14C13A )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 state_o[4] PIO PB35A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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! " # $ % & ' ( 4MODE:LOGIC K1::H1=(C+B) K0::H0=(~B*A+B*D) F1:F F0:F 4 MODE K1
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PAD
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A K0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 state_o[3] PIO PB31A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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@ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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PAD
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NGID1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 state_o[2] PIO PT22C TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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textctrl/SLICE_1229 SLICE R14C12B )
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PAD
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! " # $ % & ' ( 4MODE:LOGIC K1::H1=(D*A) K0::H0=(~D*C+D*B) F1:F F0:F 4 MODE K1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID ! NGID0 state_o[1] PIO PT18B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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C K0
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PAD
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B REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID " NGID0 state_o[0] PIO PT18A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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NGID1
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PAD
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textctrl/SLICE_1230 SLICE R14C14D )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID # NGID0 data_io[7] PIO PT15B {TRIMUX:PADDT IOBUF:::PULLMODE=NONE,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B+A*C) K0::H0=(~A*D+A*B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
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PAD
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E K0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 data_io[6] PIO PT15A {TRIMUX:PADDT IOBUF:::PULLMODE=NONE,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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D REG1
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PAD
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G REG0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 data_io[5] PIO PT11B {TRIMUX:PADDT IOBUF:::PULLMODE=NONE,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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F Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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PAD
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NGID1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 data_io[4] PIO PT11A {TRIMUX:PADDT IOBUF:::PULLMODE=NONE,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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NGID2
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PAD
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t NGID3
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 data_io[3] PIO PT10B {TRIMUX:PADDT IOBUF:::PULLMODE=NONE,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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utextctrl/SLICE_1231 SLICE R19C14D )
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PAD
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~A*C+A*B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 data_io[2] PIO PT10A {TRIMUX:PADDT IOBUF:::PULLMODE=NONE,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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I K0
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PAD
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H REG1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 data_io[1] PIO PT9B {TRIMUX:PADDT IOBUF:::PULLMODE=NONE,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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K REG0
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PAD
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J Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 cen_o PIO PB26A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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NGID1
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PAD
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NGID2
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 wen_o PIO PB29A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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r NGID3
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PAD
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stextctrl/SLICE_1232 SLICE R19C12D )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 oen_o PIO PB26B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*B+A*D) K0::H0=(~A*B+A*C) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:1 SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
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PAD
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M K0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[15] PIO PB23B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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L REG1
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PAD
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O REG0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[14] PIO PB18B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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N Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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PAD
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NGID1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[13] PIO PB23A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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NGID2
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PAD
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p NGID3
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[12] PIO PB18A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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qSLICE_1233 SLICE R14C13C )
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PAD
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! " # $ % & ' ( ,MODE:LOGIC K1::H1=~D K0::H0=(D*A) F1:F F0:F 4 MODE K1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[11] PIO PB16B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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Q K0
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PAD
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P REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[10] PIO PB13B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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NGID1
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PAD
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SLICE_1234 SLICE R19C15C )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[9] PIO PB16A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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! " # $ % & ' ( ,MODE:LOGIC K1::H1=~B K0::H0=(B*D) F1:F F0:F 4 MODE K1
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PAD
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S K0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[8] PIO PB13A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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R REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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PAD
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NGID1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID
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textctrl/SLICE_1235 SLICE R21C9D )
|
NGID0 addr_o[7] PIO PB12B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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! " # $ % & ' ( 8MODE:LOGIC K1::H1=(A@C) K0::H0=(A*(C*(D*~B))) F1:F F0:F 4 MODE K1
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PAD
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U K0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[6] PIO PB9B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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T REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
|
PAD
|
NGID1
|
DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[5] PIO PB12A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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SLICE_1236 SLICE R21C10C )
|
PAD
|
! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~A*(B*(C*~D))) K0::H0=(~B*~A) F1:F F0:F 4 MODE K1
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID
NGID0 addr_o[4] PIO PB9A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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W K0
|
PAD
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V REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[3] PIO PB6B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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NGID1 ccpu0/SLICE_1237 SLICE R16C10B )
|
PAD
|
! " # $ % & ' (
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[2] PIO PB4B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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Y K0
|
PAD
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X REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1238 SLICE R14C20D )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[1] PIO PB6A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
|
! " # $ % & ' ( DMODE:LOGIC K1::H1=(~A*(~D*~C)) K0::H0=(~C*(~A*D)+C*(D+A)) F1:F F0:F 4 MODE K1
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PAD
|
[ K0
|
DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 addr_o[0] PIO PB4A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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Z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 :cpu0/SLICE_1239 SLICE R10C20A )
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PAD
|
! " # $ % & ' ( CMODE:LOGIC K1::H1=(~D*(A*~C)) K0::H0=(~C*(~D*A)+C*(A+D)) F1:F F0:F 4 MODE K1
|
DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 reset_o PIO PT22D TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
|
] K0
|
PAD
|
\ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1240 SLICE R10C19A )
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 textctrl/chars/textmem4k_0_0_3 EBR EBR_R20C27 MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,GSR=DISABLED,INITVAL_00=0x00000000000000000000000000000109C4E088E41C84E09C441C8E409C4E088E41C84E09C441C8E4,INITVAL_01=0x00000000031000000000000000000000000000000000000000000000000208000000000000000000,INITVAL_02=0x00000000000000000000000000000000000000001800000000000000000000000000000000000000,INITVAL_03=0x00000000000000000002080000000000000000000000000000000000000000000000010000000000,INITVAL_04=0x18000000000000000000000000000000000000000000000003100000000000000000000000000000,INITVAL_05=0x00000000000000000000000000000100000000000000000000000000000000000000000000000000,INITVAL_06=0x000000000101C4E088E41C84E09C441C8E409C4E088E41C84E09C441C8E408000000000000000000,INITVAL_07=0x00000000000000000000000000000000000000020800000000000000000000000000000000000000,INITVAL_08=0x00000000000000000000180000000000000000000000000000000000000000000000031000000000,INITVAL_09=0x08000000000000000000000000000000000000000000000001000000000000000000000000000000,INITVAL_0A=0x00000000000000000000000000000310000000000000000000000000000000000000000000000002,INITVAL_0B=0x00000000010000000000000000000000000000000000000000000000000018000000000000000000,INITVAL_0C=0x1C84E09C441C8E409C4E088E41C84E09C441C8E40800000000000000000000000000000000000000,INITVAL_0D=0x000000000000000000020800000000000000000000000000000000000000000000000101C4E088E4,INITVAL_0E=0x18000000000000000000000000000000000000000000000003100000000000000000000000000000,WID=0b0000000011,MEM_INIT_FILE=textmem2k.mem,MEM_LPC_FILE=textmem4k.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB3=0,DIB4=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/yptr[0] #%DP8KC%SIGNAME:ADA10 textctrl/yptr[9] #%DP8KC%SIGNAME:ADA11 textctrl/yptr[10] #%DP8KC%SIGNAME:ADA12 textctrl/yptr[11] #%DP8KC%SIGNAME:ADA2 textctrl/yptr[1] #%DP8KC%SIGNAME:ADA3 textctrl/yptr[2] #%DP8KC%SIGNAME:ADA4 textctrl/yptr[3] #%DP8KC%SIGNAME:ADA5 textctrl/yptr[4] #%DP8KC%SIGNAME:ADA6 textctrl/yptr[5] #%DP8KC%SIGNAME:ADA7 textctrl/yptr[6] #%DP8KC%SIGNAME:ADA8 textctrl/yptr[7] #%DP8KC%SIGNAME:ADA9 textctrl/yptr[8] #%DP8KC%SIGNAME:ADB1 addr_o_c[0] #%DP8KC%SIGNAME:ADB10 addr_o_c[9] #%DP8KC%SIGNAME:ADB11 addr_o_c[10] #%DP8KC%SIGNAME:ADB12 addr_o_c[11] #%DP8KC%SIGNAME:ADB2 addr_o_c[1] #%DP8KC%SIGNAME:ADB3 addr_o_c[2] #%DP8KC%SIGNAME:ADB4 addr_o_c[3] #%DP8KC%SIGNAME:ADB5 addr_o_c[4] #%DP8KC%SIGNAME:ADB6 addr_o_c[5] #%DP8KC%SIGNAME:ADB7 addr_o_c[6] #%DP8KC%SIGNAME:ADB8 addr_o_c[7] #%DP8KC%SIGNAME:ADB9 addr_o_c[8] #%DP8KC%SIGNAME:CEB textctrl/un1_CPU_OE_EN_0_a2 #%DP8KC%SIGNAME:CLKA
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! " # $ % & ' ( RMODE:LOGIC K1::H1=(~B*(~D*~A)+B*(~D+(~A+C))) K0::H0=(~D*(~A*B)+D*(B+A)) F1:F F0:F 4 MODE K1
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cpu_clkgen #%DP8KC%SIGNAME:CLKB
|
_ K0
|
cpu_clkgen #%DP8KC%SIGNAME:DIB2 cpu0_data_out[0] #%DP8KC%SIGNAME:DIB5 cpu0_data_out[1] #%DP8KC%SIGNAME:DOA0 textctrl/chars_bus[0] #%DP8KC%SIGNAME:DOA1 textctrl/chars_bus[1] #%DP8KC%SIGNAME:DOB0 textctrl/data_from_video[0] #%DP8KC%SIGNAME:DOB1 textctrl/data_from_video[1] #%DP8KC%SIGNAME:OCEB textctrl/un1_CPU_OE_EN_0_a2 #%DP8KC%SIGNAME:WEB wen_o_c NGID0 textctrl/chars/textmem4k_0_1_2 EBR EBR_R20C24 %MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,GSR=DISABLED,INITVAL_00=0x00000000000000000000000000000014A5001455000A50A00A0AA0014A5001455000A50A00A0AA00,INITVAL_02=0x00000000000000000000000000000000000000010000000000000000000000000000000000000000,INITVAL_03=0x00000000000000000001080000000000000000000000000000000000000000000000010800000000,INITVAL_04=0x08000000000000000000000000000000000000000000000001080000000000000000000000000000,INITVAL_05=0x00000000000000000000000000000210000000000000000000000000000000000000000000000002,INITVAL_06=0x000000000004A5001455000A50A00A0AA0014A5001455000A50A00A0AA0010000000000000000000,INITVAL_08=0x00000000000000000001000000000000000000000000000000000000000000000000000000000000,INITVAL_09=0x08000000000000000000000000000000000000000000000001080000000000000000000000000000,INITVAL_0A=0x00000000000000000000000000000108000000000000000000000000000000000000000000000001,INITVAL_0B=0x00000000021000000000000000000000000000000000000000000000000208000000000000000000,INITVAL_0C=0x000A50A00A0AA0014A5001455000A50A00A0AA001000000000000000000000000000000000000000,INITVAL_0D=0x000000000000000000000000000000000000000000000000000000000000000000000004A5001455,INITVAL_0F=0x00000000000000000000000000000008000000000000000000000000000000000000000000000001,WID=0b0000000100,MEM_INIT_FILE=textmem2k.mem,MEM_LPC_FILE=textmem4k.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB3=0,DIB4=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/yptr[0] #%DP8KC%SIGNAME:ADA10 textctrl/yptr[9] #%DP8KC%SIGNAME:ADA11 textctrl/yptr[10] #%DP8KC%SIGNAME:ADA12 textctrl/yptr[11] #%DP8KC%SIGNAME:ADA2 textctrl/yptr[1] #%DP8KC%SIGNAME:ADA3 textctrl/yptr[2] #%DP8KC%SIGNAME:ADA4 textctrl/yptr[3] #%DP8KC%SIGNAME:ADA5 textctrl/yptr[4] #%DP8KC%SIGNAME:ADA6 textctrl/yptr[5] #%DP8KC%SIGNAME:ADA7 textctrl/yptr[6] #%DP8KC%SIGNAME:ADA8 textctrl/yptr[7] #%DP8KC%SIGNAME:ADA9 textctrl/yptr[8] #%DP8KC%SIGNAME:ADB1 addr_o_c[0] #%DP8KC%SIGNAME:ADB10 addr_o_c[9] #%DP8KC%SIGNAME:ADB11 addr_o_c[10] #%DP8KC%SIGNAME:ADB12 addr_o_c[11] #%DP8KC%SIGNAME:ADB2 addr_o_c[1] #%DP8KC%SIGNAME:ADB3 addr_o_c[2] #%DP8KC%SIGNAME:ADB4 addr_o_c[3] #%DP8KC%SIGNAME:ADB5 addr_o_c[4] #%DP8KC%SIGNAME:ADB6 addr_o_c[5] #%DP8KC%SIGNAME:ADB7 addr_o_c[6] #%DP8KC%SIGNAME:ADB8 addr_o_c[7] #%DP8KC%SIGNAME:ADB9 addr_o_c[8] #%DP8KC%SIGNAME:CEB textctrl/un1_CPU_OE_EN_0_a2 #%DP8KC%SIGNAME:CLKA
|
^ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1241 SLICE R9C19A )
|
cpu_clkgen #%DP8KC%SIGNAME:CLKB
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~C*~D) K0::H0=(~C*(~B*D)+C*(D+B)) F1:F F0:F 4 MODE K1
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cpu_clkgen #%DP8KC%SIGNAME:DIB2 cpu0_data_out[2] #%DP8KC%SIGNAME:DIB5 cpu0_data_out[3] #%DP8KC%SIGNAME:DOA0 textctrl/chars_bus[2] #%DP8KC%SIGNAME:DOA1 textctrl/chars_bus[3] #%DP8KC%SIGNAME:DOB0 textctrl/data_from_video[2] #%DP8KC%SIGNAME:DOB1 textctrl/data_from_video[3] #%DP8KC%SIGNAME:OCEB textctrl/un1_CPU_OE_EN_0_a2 #%DP8KC%SIGNAME:WEB wen_o_c NGID0 textctrl/chars/textmem4k_0_2_1 EBR EBR_R13C24 ?MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,GSR=DISABLED,INITVAL_00=0x154AA154AA154AA154AA154AA154AB1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF,INITVAL_01=0x154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA,INITVAL_02=0x154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA,INITVAL_03=0x154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA,INITVAL_04=0x1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA,INITVAL_05=0x154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB,INITVAL_06=0x154AA154AB1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1D4AA154AA154AA154AA,INITVAL_07=0x154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA,INITVAL_08=0x154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA,INITVAL_09=0x1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA,INITVAL_0A=0x154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB,INITVAL_0B=0x154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA,INITVAL_0C=0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1D4AA154AA154AA154AA154AA154AA154AA154AA,INITVAL_0D=0x154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1FEFF1FEFF,INITVAL_0E=0x1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA,INITVAL_0F=0x0000000000000000000000000000001D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB,WID=0b0000000101,MEM_INIT_FILE=textmem2k.mem,MEM_LPC_FILE=textmem4k.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB3=0,DIB4=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/yptr[0] #%DP8KC%SIGNAME:ADA10 textctrl/yptr[9] #%DP8KC%SIGNAME:ADA11 textctrl/yptr[10] #%DP8KC%SIGNAME:ADA12 textctrl/yptr[11] #%DP8KC%SIGNAME:ADA2 textctrl/yptr[1] #%DP8KC%SIGNAME:ADA3 textctrl/yptr[2] #%DP8KC%SIGNAME:ADA4 textctrl/yptr[3] #%DP8KC%SIGNAME:ADA5 textctrl/yptr[4] #%DP8KC%SIGNAME:ADA6 textctrl/yptr[5] #%DP8KC%SIGNAME:ADA7 textctrl/yptr[6] #%DP8KC%SIGNAME:ADA8 textctrl/yptr[7] #%DP8KC%SIGNAME:ADA9 textctrl/yptr[8] #%DP8KC%SIGNAME:ADB1 addr_o_c[0] #%DP8KC%SIGNAME:ADB10 addr_o_c[9] #%DP8KC%SIGNAME:ADB11 addr_o_c[10] #%DP8KC%SIGNAME:ADB12 addr_o_c[11] #%DP8KC%SIGNAME:ADB2 addr_o_c[1] #%DP8KC%SIGNAME:ADB3 addr_o_c[2] #%DP8KC%SIGNAME:ADB4 addr_o_c[3] #%DP8KC%SIGNAME:ADB5 addr_o_c[4] #%DP8KC%SIGNAME:ADB6 addr_o_c[5] #%DP8KC%SIGNAME:ADB7 addr_o_c[6] #%DP8KC%SIGNAME:ADB8 addr_o_c[7] #%DP8KC%SIGNAME:ADB9 addr_o_c[8] #%DP8KC%SIGNAME:CEB textctrl/un1_CPU_OE_EN_0_a2 #%DP8KC%SIGNAME:CLKA
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a K0
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cpu_clkgen #%DP8KC%SIGNAME:CLKB
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` REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1242 SLICE R14C15A )
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cpu_clkgen #%DP8KC%SIGNAME:DIB2 cpu0_data_out[4] #%DP8KC%SIGNAME:DIB5 cpu0_data_out[5] #%DP8KC%SIGNAME:DOA0 textctrl/chars_bus[4] #%DP8KC%SIGNAME:DOA1 textctrl/chars_bus[5] #%DP8KC%SIGNAME:DOB0 textctrl/data_from_video[4] #%DP8KC%SIGNAME:DOB1 textctrl/data_from_video[5] #%DP8KC%SIGNAME:OCEB textctrl/un1_CPU_OE_EN_0_a2 #%DP8KC%SIGNAME:WEB wen_o_c NGID0 textctrl/chars/textmem4k_0_3_0 EBR EBR_R13C27 _MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,GSR=DISABLED,WID=0b0000000001,MEM_INIT_FILE=textmem2k.mem,MEM_LPC_FILE=textmem4k.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB3=0,DIB4=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/yptr[0] #%DP8KC%SIGNAME:ADA10 textctrl/yptr[9] #%DP8KC%SIGNAME:ADA11 textctrl/yptr[10] #%DP8KC%SIGNAME:ADA12 textctrl/yptr[11] #%DP8KC%SIGNAME:ADA2 textctrl/yptr[1] #%DP8KC%SIGNAME:ADA3 textctrl/yptr[2] #%DP8KC%SIGNAME:ADA4 textctrl/yptr[3] #%DP8KC%SIGNAME:ADA5 textctrl/yptr[4] #%DP8KC%SIGNAME:ADA6 textctrl/yptr[5] #%DP8KC%SIGNAME:ADA7 textctrl/yptr[6] #%DP8KC%SIGNAME:ADA8 textctrl/yptr[7] #%DP8KC%SIGNAME:ADA9 textctrl/yptr[8] #%DP8KC%SIGNAME:ADB1 addr_o_c[0] #%DP8KC%SIGNAME:ADB10 addr_o_c[9] #%DP8KC%SIGNAME:ADB11 addr_o_c[10] #%DP8KC%SIGNAME:ADB12 addr_o_c[11] #%DP8KC%SIGNAME:ADB2 addr_o_c[1] #%DP8KC%SIGNAME:ADB3 addr_o_c[2] #%DP8KC%SIGNAME:ADB4 addr_o_c[3] #%DP8KC%SIGNAME:ADB5 addr_o_c[4] #%DP8KC%SIGNAME:ADB6 addr_o_c[5] #%DP8KC%SIGNAME:ADB7 addr_o_c[6] #%DP8KC%SIGNAME:ADB8 addr_o_c[7] #%DP8KC%SIGNAME:ADB9 addr_o_c[8] #%DP8KC%SIGNAME:CEB textctrl/un1_CPU_OE_EN_0_a2 #%DP8KC%SIGNAME:CLKA
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~B*D+B*(~A*D+A*(D*C))) K0::H0=(~B*D+B*C) F1:F F0:F 4 MODE K1
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cpu_clkgen #%DP8KC%SIGNAME:CLKB
|
c K0
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cpu_clkgen #%DP8KC%SIGNAME:DIB2 cpu0_data_out[6] #%DP8KC%SIGNAME:DIB5 cpu0_data_out[7] #%DP8KC%SIGNAME:DOA0 textctrl/chars_bus[6] #%DP8KC%SIGNAME:DOA1 textctrl/chars_bus[7] #%DP8KC%SIGNAME:DOB0 textctrl/data_from_video[6] #%DP8KC%SIGNAME:DOB1 textctrl/data_from_video[7] #%DP8KC%SIGNAME:OCEB textctrl/un1_CPU_OE_EN_0_a2 #%DP8KC%SIGNAME:WEB wen_o_c NGID0 textctrl/font/fontrom_0_0_3 EBR EBR_R20C13
MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,CSDECODE_B=0b111,GSR=DISABLED,INITVAL_00=0x0000000000000021F000000031E00000000100000000215000000BF1FEE0000950AA600000000000,INITVAL_01=0x0000C19800000BF1FEF000000006F0000080548000000014A01FEF50BEFF0000A140001FEFF1FEFF,INITVAL_02=0x0008200400000AA000000008014020000FF1FEF0000A2154A00000200400000AA154A80000004000,INITVAL_03=0x00000014000002800000000021C00000008000000000010000000001000000008000000000000400,INITVAL_04=0x00000000000008004000000A0014000002A10480000080100000000000A800000000000000000000,INITVAL_05=0x00000014000000000000000001000000000000000000010000000081900000000000000000000000,INITVAL_06=0x00000014A00002A100000002A1002000080100000002A11480000A00048000080000000002F1FE80,INITVAL_07=0x0000000480000001000000002010000008000080000000000000000000000000A154800002A11480,INITVAL_08=0x000AA1048000000004A0000A8004A00000A1540000028004800002A11480000AA150000000215400,INITVAL_09=0x0002A15480000AA154A0000FF1FEF0000A800000000A8004A000000000200000000000000AA154A0,INITVAL_0A=0x000AF1FEF00000B1FEF00002A154A000000002F00002A00480000AA014800102A154800000001480,INITVAL_0B=0x018000000000000000800000000000000A8000000000000000000F4004F000000016F0000F8004F0,INITVAL_0C=0x000000100000000000000002014000000800000000020040000002A1000000080000000000000000,INITVAL_0D=0x0002A14000000AA14000000FF1F0000000000000000A001000014AA150A00000000000000AA14000,INITVAL_0E=0x000BF1F8000000B1F800000800000000020000000002004000000001400004000010000002A14000,INITVAL_0F=0x0002A100000000000020000000400000000000000008000020000A001000004AA15000000E005800,INITVAL_10=0x00082010000008000000000800000000080000000008000000000201400000080000000040A00480,INITVAL_11=0x000AA14000000AA14008000000000000000000800000000020000201400000020140200002014000,INITVAL_12=0x000800000000080000000002A140000002A140200002A140000008004020000C21F000000A001400,INITVAL_13=0x0000004038000EA1D0A000003060B000020000000000B006800002A154880002A15408004AA15020,INITVAL_14=0x00000000000000004400000AA15482000AA1402000080000000002A1400000000000000008000000,INITVAL_15=0x000001000000008010000000000000014AA00480018B8004800002A1400000000040000002800000,INITVAL_16=0x154AA10000154AA154AA0000000000000000000000000000001BADD1BADD13299132990221102211,INITVAL_17=0x0000000000000000000000000154AA00000154AA154AA15000154AA154AA154AA154AA0000000000,INITVAL_18=0x154AA1D4AA0000019800000001800000000180000000018000000001800000000180000000018000,INITVAL_19=0x0000019800154AA19CAA0000019800154AA19CAA154AA198000000019CAA154AA198000000019CAA,INITVAL_1A=0x154AA1D4AA154AA1800000000198000000019800000001D4AA154AA180000000019800000001D4AA,INITVAL_1B=0x0000007EFF1FEFF1FEFF00000000001FEFF180001FEFF1FEFF000001800000000000000000019800,INITVAL_1C=0x000000040000002154000000001000000A000480000000040000000004A00002A000000008001000,INITVAL_1D=0x000AA1540000000000000000B1F4C00000B1F0000002A1402000080054000000A150000008214080,INITVAL_1E=0x00002010000000010000000000000000000006E000080000000008004000000C0040000002010400,INITVAL_1F=0x0000000000000000000000000000000000000000000000000C000000000000000000000000000000,WID=0b0000000110,MEM_INIT_FILE=font256x16l.mem,MEM_LPC_FILE=fontrom.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=1,OCEB=1,CLKB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/line_cnt[0] #%DP8KC%SIGNAME:ADA10 textctrl/chars_data[5] #%DP8KC%SIGNAME:ADA11 textctrl/chars_data[6] #%DP8KC%SIGNAME:ADA12 textctrl/chars_data[7] #%DP8KC%SIGNAME:ADA2 textctrl/line_cnt[1] #%DP8KC%SIGNAME:ADA3 textctrl/line_cnt[2] #%DP8KC%SIGNAME:ADA4 textctrl/line_cnt[3] #%DP8KC%SIGNAME:ADA5 textctrl/chars_data[0] #%DP8KC%SIGNAME:ADA6 textctrl/chars_data[1] #%DP8KC%SIGNAME:ADA7 textctrl/chars_data[2] #%DP8KC%SIGNAME:ADA8 textctrl/chars_data[3] #%DP8KC%SIGNAME:ADA9 textctrl/chars_data[4] #%DP8KC%SIGNAME:CLKA
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b REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 - NGID1 scpu0/SLICE_1243 SLICE R14C16B )
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cpu_clkgen #%DP8KC%SIGNAME:DOA0 textctrl/font_bus[0] #%DP8KC%SIGNAME:DOA1 textctrl/font_bus[1] NGID0 textctrl/font/fontrom_0_1_2 EBR EBR_R13C13
MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,CSDECODE_B=0b111,GSR=DISABLED,INITVAL_00=0x0000B1C000000EB1FE80000E90BE800000B1F0000002F1FE00000FD07CF0000C2182300000000000,INITVAL_01=0x000AB0F48000054006300000000630000AE1AA70000BF1C4F01FECB1C6FF00034038001FEF403EFF,INITVAL_02=0x000EF156E0000FF000000067B0BC1C000AA154B0000510AA500002F156E00001F1FED00000017000,INITVAL_03=0x0000A1FE000003F1D000000051A8000000C0000000000180000000B1F000000BE154A0000AA156E0,INITVAL_04=0x00000000000007F1B6E00005016800014D50E07A000FF1FEC00000000254000A215EE00000000000,INITVAL_05=0x0000016800000A0000000000018000000A8000000000A1D000000071E8000002F1FE80000E0000B0,INITVAL_06=0x0000016A70000D50E020000D50E030000FF1FEF0000D50EA70000D005A70000EA154A0000D014070,INITVAL_07=0x000A215A700000B0F0000000301800000780164000028014000002801400000B50EA70000D50EA70,INITVAL_08=0x00095180700000015070000D015070000B50AAE0000D000070000D50EA70000551AE80000CF1EAC0,INITVAL_09=0x000D50AA70000551FA500000005E40000D0000000005715A50000BF1FEF0000EA154B0000550EA50,INITVAL_0A=0x0005E10000000B400000000D50AA50000EA154B0000D51C270000551EA7001EF50AA700000006A70,INITVAL_0B=0x01800000000000000078000FF1FEF00001F10000000C000030000C005A30000EA168000000715A00,INITVAL_0C=0x05EFF1E80000000002E0000D01B8000007F1FEF0000D003800000D50F0000007F1F0000000000020,INITVAL_0D=0x000D50B800000550B800000AA16800000EA154A00005E1680006A550B850000EA150A0000550B800,INITVAL_0E=0x0007A00000000B4000000007F1F800000D001800000DE03800000000B80007EFF1E800000D50B800,INITVAL_0F=0x000350F00000000000D00002A17480000AA114A0000EA114B0000D01780005AD50A8000001E1A000,INITVAL_10=0x0067D00E000007F1F0B80007F1F0800007F1F0300007F1F0E0000D01B82C0007F1F83001AF400070,INITVAL_11=0x000570BC2E000570BC04000EA15080000EA15078000EA15010000D01B880000D01B810000D01B8E0,INITVAL_12=0x0007F1F8800007F1F8E0000D50B880000D50B810000D50B8E0000FF1FEF00007B15800000D018E02,INITVAL_13=0x004AA174AC000151A65C000AB17640000D000078000AC000E8000D50AA44000D50AAC405AD50A810,INITVAL_14=0x00000064F800000066FC000571EA4D000550B8D00007F1F808000D50B808000EA1502C0007F1F008,INITVAL_15=0x0000B0F0000000716800000BF150A000ADD05A0001E6C05A00000150E0000000006000000D400000,INITVAL_16=0x0AA55180000AA550AA55154AA154AA154AA154AA154AA154AA0EE770EE7713299132990884408844,INITVAL_17=0x154AA1000000000154AA000001AA55000001AA550AA550B8000AA550AA550AA550AA55154AA15000,INITVAL_18=0x0AA550AA55154AA1DCAA154AA1D4AA0000018000154AA1D4AA154AA18000000001D4AA000001D4AA,INITVAL_19=0x0000019CAA0AA5508A5500000198000AA5508A550AA55098000000018A550AA55098000000018A55,INITVAL_1A=0x0AA551AA550AA5518000154AA1D800000001DCAA000001AA550AA5518000154AA19800000001AA55,INITVAL_1B=0x0000007EFF1FEFF1FEFF00000000001FEFF180001FEFF1FEFF154AA1800000000154AA154AA1DCAA,INITVAL_1C=0x000AA15A000000D0AA000002A15800000D0102C0000FF1FE000000000270000D51DEE00007A16800,INITVAL_1D=0x000550AAC0000C0060300000C15A000000E15800000D50FC30000FF1AAE0000B51AE80000ED0BCC0,INITVAL_1E=0x0000D0680000028194000002A154AA154AA154B0000CE004C0000C21BC00000C2174000003018600,INITVAL_1F=0x00000000000003F1FE0000000050200000007EF8000FF1FEFC0000200000000021000000000004F8,WID=0b0000000111,MEM_INIT_FILE=font256x16l.mem,MEM_LPC_FILE=fontrom.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=1,OCEB=1,CLKB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/line_cnt[0] #%DP8KC%SIGNAME:ADA10 textctrl/chars_data[5] #%DP8KC%SIGNAME:ADA11 textctrl/chars_data[6] #%DP8KC%SIGNAME:ADA12 textctrl/chars_data[7] #%DP8KC%SIGNAME:ADA2 textctrl/line_cnt[1] #%DP8KC%SIGNAME:ADA3 textctrl/line_cnt[2] #%DP8KC%SIGNAME:ADA4 textctrl/line_cnt[3] #%DP8KC%SIGNAME:ADA5 textctrl/chars_data[0] #%DP8KC%SIGNAME:ADA6 textctrl/chars_data[1] #%DP8KC%SIGNAME:ADA7 textctrl/chars_data[2] #%DP8KC%SIGNAME:ADA8 textctrl/chars_data[3] #%DP8KC%SIGNAME:ADA9 textctrl/chars_data[4] #%DP8KC%SIGNAME:CLKA
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! " # $ % & ' ( 5MODE:LOGIC K1::H1=(A+C) K0::H0=(~D*~C+D*A) F1:F F0:F 4 MODE K1
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cpu_clkgen #%DP8KC%SIGNAME:DOA0 textctrl/font_bus[2] #%DP8KC%SIGNAME:DOA1 textctrl/font_bus[3] NGID0 textctrl/font/fontrom_0_2_1 EBR EBR_R13C16
MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,CSDECODE_B=0b111,GSR=DISABLED,INITVAL_00=0x000071A000000D71FE40000D615E400001F1FA000007F1FC00000FE07AF0000C1184300000000000,INITVAL_01=0x0005716A40000AA156B0000BF1FEF00005D1D4B0000C007A101FEC71A6FF00038058001FEF805EFF,INITVAL_02=0x000DF0AED0000FF000000060E0168C000550EA70000A2154A00001F0AED0000011FA000000B1FE80,INITVAL_03=0x0001F1FE000003F1FA000000A1D0000000C000000000E1D80000004188000007D0AA50000550AED0,INITVAL_04=0x00000004FC000C00FCB00000B0800000AC006035000AE15C8000000004A8000510BED00000000000,INITVAL_05=0x0000B08000000500000000000180000065400000000051A8000000B1F000000D0000700001F1FE40,INITVAL_06=0x000FF08030000C0060B0000C0060300004019640000C006030000C21A030000D50AED0000E00A0B0,INITVAL_07=0x000510A030000B400E8000003018000000716800000D400A000001400A00000C006030000C006030,INITVAL_08=0x000E0080B0000EA174B0000EA174B0000EA154B0000E0000B0000EA174B000000184D0000C50A0C0,INITVAL_09=0x000C0000300000003E800000003E80000EA154B0000AA1F4A0000C000010000D50AA700000006000,INITVAL_0A=0x000AD080000007800000000C000000000D50AA70000C007030000AA174B0000D400030000EA174B0,INITVAL_0B=0x0180000000000000002D000C000030000011F000000FF1FEF0000C21A030000D50F0000000B0BC00,INITVAL_0C=0x060C001800000EA174B0000C019800000C005810000C001800000EA15CA0000C019800000000001F,INITVAL_0D=0x000C001800000AA14800000550F000000D50AA70000AB1D4A00740000000000D50B850000AA174A0,INITVAL_0E=0x000B5000000007800000000C0000000007F1FED0000C311800000EA16800020C001800074EA14800,INITVAL_0F=0x0003005A000000000070000D508A700005508A50000150EA40000CB09800060C0000000002D1C000,INITVAL_10=0x0060E15600000C0198EC000C019878000C019800000C0198B4000C0198D0000C00000001838000B0,INITVAL_11=0x000030163B0000301640000D50B878000D50B8B4000D50B820000C019878000C019800000C0198B4,INITVAL_12=0x000C000078000C00003C000C001878000C001800000C0018B400000060B0000D70F000000EA1D62D,INITVAL_13=0x01A550EA50000EA156AC000570EE80000EA15CAC0005C000D4000C000000000C0000C0060C000000,INITVAL_14=0x00000066AC00000066AC000000FC07000AA14870000C0000B4000C0018B4000D50B8D0000C0198B4,INITVAL_15=0x000061C8000000E0D8000007F0A850000D21A000008121A00000000060000000006000000C0178F0,INITVAL_16=0x1FEFF180001FEFF1FEFF0AA551BA550AA551AA550AA550AA551BADD1BADD13299132990221102211,INITVAL_17=0x0AA5518000000001BA55000001FEFF0000019EFF1FEFF198001FEFF1FEFF1FEFF19EFF0AA551B800,INITVAL_18=0x1FEFF1FEFF0AA550AA550AA551AA5500000180000AA550AA550AA5518000000001AA55000000AA55,INITVAL_19=0x0000019A551FEFF19EFF00000198001FEFF1FEFF1FEFF198000000019EFF1FEFF1F800000001FEFF,INITVAL_1A=0x1FEFF1FEFF1FEFF180000AA550A800000000AA55000001FEFF1FEFF180000AA5519800000001FEFF,INITVAL_1B=0x0000007EFF00000000001FEFF1FEFF1FEFF180001FEFF1FEFF0AA5508000000001AA550AA551BA55,INITVAL_1C=0x000550AE00000AE15400000D50B800000CB0F0C0000AA1560000000000300000002030000D50B800,INITVAL_1D=0x00000000C00007A174D00002F0B8000000D0B800000EA162D0000AA100B0000E0184C0000DE15AC0,INITVAL_1E=0x00007038000001418A00000D50AA550AA550AA40000C11DA00000CD002C0000C10EA000003018600,INITVAL_1F=0x00000000000003F1FE0000000064DC00000054A40007A100000000100000000010800000000006AC,WID=0b0000001000,MEM_INIT_FILE=font256x16l.mem,MEM_LPC_FILE=fontrom.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=1,OCEB=1,CLKB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/line_cnt[0] #%DP8KC%SIGNAME:ADA10 textctrl/chars_data[5] #%DP8KC%SIGNAME:ADA11 textctrl/chars_data[6] #%DP8KC%SIGNAME:ADA12 textctrl/chars_data[7] #%DP8KC%SIGNAME:ADA2 textctrl/line_cnt[1] #%DP8KC%SIGNAME:ADA3 textctrl/line_cnt[2] #%DP8KC%SIGNAME:ADA4 textctrl/line_cnt[3] #%DP8KC%SIGNAME:ADA5 textctrl/chars_data[0] #%DP8KC%SIGNAME:ADA6 textctrl/chars_data[1] #%DP8KC%SIGNAME:ADA7 textctrl/chars_data[2] #%DP8KC%SIGNAME:ADA8 textctrl/chars_data[3] #%DP8KC%SIGNAME:ADA9 textctrl/chars_data[4] #%DP8KC%SIGNAME:CLKA
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e K0
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cpu_clkgen #%DP8KC%SIGNAME:DOA0 textctrl/font_bus[4] #%DP8KC%SIGNAME:DOA1 textctrl/font_bus[5] NGID0 textctrl/font/fontrom_0_3_0 EBR EBR_R20C16
MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,CSDECODE_B=0b111,GSR=DISABLED,INITVAL_00=0x0000000000000011E800000031E000000011A000000071FA000007F1FED00006A154900000000000,INITVAL_01=0x0000C19800006F50AA50000F4000000000402A400007F1A0001FEFA15EFF000050A0001FEFF1FEFF,INITVAL_02=0x0004100200000FF00000002C11E8740000003ED0000510AA5000001002000000006000000BF1FEF8,INITVAL_03=0x000000BE000003D08000000011A0000000F1E000000011A000000001800000004000000000000200,INITVAL_04=0x00000002000007F1A240000B401E000007803ED00005D0BA40000000005400000000000000000000,INITVAL_05=0x000B4000000000000000000001800000000000000000008000000041880000000000000000000000,INITVAL_06=0x00000000F00007F1FE400007007EF0000001E80000070000D0000FD000D000040002000001F1FE40,INITVAL_07=0x00000006D0000400004000001008000000008000000000000000000000000004003ED00007F1BED0,INITVAL_08=0x0001F1FE40000D50AA70000D50AA70000D50AA700001F1FE40000D50AA70000FF1FA000007F1FE40,INITVAL_09=0x0007F1FED0000FF1FEF0000FF1FEF0000D50AA70000D50AA700007F000000000000000000FF1FEF0,INITVAL_0A=0x0005F1FEF0000071FEF00007F1FEF000000004F00007C00ED0000D50AA700007F1FED0000D50AA70,INITVAL_0B=0x018000000000000000D000000000000000003E800000000000000FD004F00000000EF0000F4002F0,INITVAL_0C=0x0387F1E800000D50EA400007F1E8000007F1A0000007F1E800000550AA700007F088000000000000,INITVAL_0D=0x0007F1E800000550B800000FF1F8000000000000000D50AA7000A00000000000000000000D50AA70,INITVAL_0E=0x0007F1F800000071F8000007F1F8000000001800000700E800000D50B8000007F1E80006A550B800,INITVAL_0F=0x0003F1A00000000000D0000400001000000000000000002000000F4078000607F1F800000D003800,INITVAL_10=0x000010A8000007F088100007F088040007F088300007F088400007F1E8000007F1F830008071FE40,INITVAL_11=0x000FF1E804000FF1E80C0000000004000000004000000000100007F1E8040007F1E8300007F1E840,INITVAL_12=0x0007F1F8040007F1F8D00007F1E8040007F1E8300007F1E840000FF1FE400007D00800000D50AE10,INITVAL_13=0x00E0002000000D50AA5C0000306070000F50BA50000071FE400007F1FECC0007F1FE4C0207F1F830,INITVAL_14=0x00000020500000002050000FF1FECD000550B8D00007F1F8400007F1E84000000000000007F08840,INITVAL_15=0x0000D03800000011A00000000000000002D01EFC0002D01EFC00000060000003F1E0000007F08000,INITVAL_16=0x000001800000000180000000019800000001800000000000000EE770EE7713299132990884408844,INITVAL_17=0x00000180000000019800000001800000000198000000019800000000000000000198000000019800,INITVAL_18=0x00000000000000000000000001800000000180000000000000000001800000000180000000000000,INITVAL_19=0x00000198000000019800000001980000000000000000019800000001980000000000000000000000,INITVAL_1A=0x00000180000000000000000000000000000000000000000000000001800000000198000000018000,INITVAL_1B=0x0000007EFF00000000001FEFF1FEFF1FEFF180001FEFF1FEFF000000000000000180000000019800,INITVAL_1C=0x0000001A00006550AA000007F1E800000F400EC0000550AE00000FF1FEF0000FF1FED00007F1E800,INITVAL_1D=0x000FF1FE40000050AA00000D71E800000071E8000001508000000D50FE400001F1FA00000410A040,INITVAL_1E=0x0000D0680000000080000007F00000000000000000040020000004000000000C0020000003018600,INITVAL_1F=0x0000000000000150AA000000007A340000002A5C0000518000000000000000000000000000000050,WID=0b0000001001,MEM_INIT_FILE=font256x16l.mem,MEM_LPC_FILE=fontrom.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=1,OCEB=1,CLKB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/line_cnt[0] #%DP8KC%SIGNAME:ADA10 textctrl/chars_data[5] #%DP8KC%SIGNAME:ADA11 textctrl/chars_data[6] #%DP8KC%SIGNAME:ADA12 textctrl/chars_data[7] #%DP8KC%SIGNAME:ADA2 textctrl/line_cnt[1] #%DP8KC%SIGNAME:ADA3 textctrl/line_cnt[2] #%DP8KC%SIGNAME:ADA4 textctrl/line_cnt[3] #%DP8KC%SIGNAME:ADA5 textctrl/chars_data[0] #%DP8KC%SIGNAME:ADA6 textctrl/chars_data[1] #%DP8KC%SIGNAME:ADA7 textctrl/chars_data[2] #%DP8KC%SIGNAME:ADA8 textctrl/chars_data[3] #%DP8KC%SIGNAME:ADA9 textctrl/chars_data[4] #%DP8KC%SIGNAME:CLKA
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d REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1 cpu0/SLICE_1244 SLICE R12C14B )
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cpu_clkgen #%DP8KC%SIGNAME:DOA0 textctrl/font_bus[6] #%DP8KC%SIGNAME:DOA1 textctrl/font_bus[7] NGID0 bios/bios2k_0_1_0 EBR EBR_R13C30 dMODE:DP8KC DP8KC:::DATA_WIDTH_A=4,DATA_WIDTH_B=4,RESETMODE=ASYNC,GSR=DISABLED,INITVAL_00=0x0000000000000000000000000000000000000000000000000001C2F0508F04A4F042C51140418C08,INITVAL_1F=0x01E00000000000000000000000000000000000000000000000000000000000000000000000000000,WID=0b0000001010,MEM_INIT_FILE=test1.mem,MEM_LPC_FILE=bios2k.lpc:CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=0,OCEB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,ADA1=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA10 addr_o_c[8] #%DP8KC%SIGNAME:ADA11 addr_o_c[9] #%DP8KC%SIGNAME:ADA12 addr_o_c[10] #%DP8KC%SIGNAME:ADA2 addr_o_c[0] #%DP8KC%SIGNAME:ADA3 addr_o_c[1] #%DP8KC%SIGNAME:ADA4 addr_o_c[2] #%DP8KC%SIGNAME:ADA5 addr_o_c[3] #%DP8KC%SIGNAME:ADA6 addr_o_c[4] #%DP8KC%SIGNAME:ADA7 addr_o_c[5] #%DP8KC%SIGNAME:ADA8 addr_o_c[6] #%DP8KC%SIGNAME:ADA9 addr_o_c[7] #%DP8KC%SIGNAME:CEA un1_bios_en_0_a2 #%DP8KC%SIGNAME:CLKA
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! " # $ % & ' ( 0MODE:LOGIC K1::H1=(C*D) K0::H0=(D*~C) F1:F F0:F 4 MODE K1
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cpu_clkgen #%DP8KC%SIGNAME:CLKB
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g K0
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cpu_clkgen #%DP8KC%SIGNAME:DIA0 cpu0_data_out[4] #%DP8KC%SIGNAME:DIA1 cpu0_data_out[5] #%DP8KC%SIGNAME:DIA2 cpu0_data_out[6] #%DP8KC%SIGNAME:DIA3 cpu0_data_out[7] #%DP8KC%SIGNAME:DOA0 data_from_bios[4] #%DP8KC%SIGNAME:DOA1 data_from_bios[5] #%DP8KC%SIGNAME:DOA2 data_from_bios[6] #%DP8KC%SIGNAME:DOA3 data_from_bios[7] #%DP8KC%SIGNAME:OCEA un1_bios_en_0_a2 #%DP8KC%SIGNAME:WEA un1_cpu0_we_0_a2 NGID0 bios/bios2k_0_0_1 EBR EBR_R20C30 MODE:DP8KC DP8KC:::DATA_WIDTH_A=4,DATA_WIDTH_B=4,RESETMODE=ASYNC,GSR=DISABLED,INITVAL_00=0x00000000000000000000000000000000000000000000000000018010E01D0D8C90C01C0AE011880E,WID=0b0000001011,MEM_INIT_FILE=test1.mem,MEM_LPC_FILE=bios2k.lpc:CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=0,OCEB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,ADA1=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA10 addr_o_c[8] #%DP8KC%SIGNAME:ADA11 addr_o_c[9] #%DP8KC%SIGNAME:ADA12 addr_o_c[10] #%DP8KC%SIGNAME:ADA2 addr_o_c[0] #%DP8KC%SIGNAME:ADA3 addr_o_c[1] #%DP8KC%SIGNAME:ADA4 addr_o_c[2] #%DP8KC%SIGNAME:ADA5 addr_o_c[3] #%DP8KC%SIGNAME:ADA6 addr_o_c[4] #%DP8KC%SIGNAME:ADA7 addr_o_c[5] #%DP8KC%SIGNAME:ADA8 addr_o_c[6] #%DP8KC%SIGNAME:ADA9 addr_o_c[7] #%DP8KC%SIGNAME:CEA un1_bios_en_0_a2 #%DP8KC%SIGNAME:CLKA
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f REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 R NGID1 cpu0/SLICE_1245 SLICE R14C21D )
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cpu_clkgen #%DP8KC%SIGNAME:CLKB
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! " # $ % & ' ( 5MODE:LOGIC K1::H1=(C*~D) K0::H0=(~C*D+C*B) F1:F F0:F 4 MODE K1
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cpu_clkgen #%DP8KC%SIGNAME:DIA0 cpu0_data_out[0] #%DP8KC%SIGNAME:DIA1 cpu0_data_out[1] #%DP8KC%SIGNAME:DIA2 cpu0_data_out[2] #%DP8KC%SIGNAME:DIA3 cpu0_data_out[3] #%DP8KC%SIGNAME:DOA0 data_from_bios[0] #%DP8KC%SIGNAME:DOA1 data_from_bios[1] #%DP8KC%SIGNAME:DOA2 data_from_bios[2] #%DP8KC%SIGNAME:DOA3 data_from_bios[3] #%DP8KC%SIGNAME:OCEA un1_bios_en_0_a2 #%DP8KC%SIGNAME:WEA un1_cpu0_we_0_a2 NGID0
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i K0
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GSR_INST GSR GSR "GSRMODE:ACTIVE_HIGH SYNCMODE:ASYNC GSRMODE SYNCMODE NGID0 N_69 s F0 c PADDO n c c l c n cP cP '~U '~U& && &e
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h REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/dec_op/SLICE_1246 SLICE R11C17A )
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e
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(D*~C) K0::H0=(~D*(~B*~C+B*A)+D*(~B+A)) F1:F F0:F 4 MODE K1
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e 5 e 5e - e -c 4 c 4` ` l & l &f f l N_18_i f ufvF0 c PADDT PADDT E PADDT G PADDT
PADDT t PADDT r PADDT f+ PADDT ( ufv u c c R E T G
t t r r f8 f+ l f8 {G r {G t T
R
l c u Fw Fw
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k K0
|
M
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j REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1247 SLICE R16C12D )
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Mw we~ e~e~ W e~ We~ i e~ ic c c c a! # a! #l a! #l a! #f f l l g g
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~D*A+D*C) K0::H0=(~C*(~B*(~D*A))) F1:F F0:F 4 MODE K1
|
|
m K0
|
c c
c
a! #v$ 2 v$ 2 v$ 2 v$ 2{G v$ 2{G cpu_clk f a XJ (Q0 @ B 4CE A\ 6TCE B\ 5CE C\ 5XCE D\ 4CE E 6TCE F 5CE G 5XCE I B 'CE J\ ):CE K\ (CE L\ (>CE M\ 'CE N ):CE O (CE P (>CE z OCE PCE P
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l REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1248 SLICE R16C21B )
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CE OCE OCE {^ PCE {^ P
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(C*~D) K0::H0=(~B*(C*A)+B*(D*A)) F1:F F0:F 4 MODE K1
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CE {^ OCE zCE zCE CE CE CE u$CE X CE CE X ):CE f ):CE f 'CE f (CE u$ CE z P
|
o K0
|
CE 5CE @C1 $ CE @ 4CE : OCE : OCE : CnCE : P
|
n REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 : NGID1 cpu0/regs/SLICE_1249 SLICE R19C17D )
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CE Iz (CE :CE CE mCE ,^CE X5CE $CE CE 4CE ҲCE $CE $CE $CE $CE CE ҲCE $OCE u$ (>CE (CE (>CE @ BrCE @ \CE @ BCE BrCE CE @ $CE @ 'CE $CE 6TCE CE 4CE ! CE a X ^A0 a X D1 b \nCE c \mCE 2ZC1 {C0 XC1 x_C1 (B1 1 'B0 B0 XB0 IzC0 XB0 :MD0 Iz[B0 D1 D0 u$C0 u$C1 f : 4CE n @A1 %TPADDO J 0B . 4 . 4 B 4 0BH 6T H 6T\ 6T 0BH 5 H 5\ 5 0BH 5X H 5X\ 5X 0BH 4 H 4\ 4 a 0B 6T 6T 6T a 0B 5 5 5 a 0B 5X 5X 5X #( . ' . ' B ' #(H ): H ):\ ): #(H ( H (\ ( #(H (> H (>\ (> #(H ' H '\ ' a #( ): ): ): a #( ( ( ( a #( (> (> (> ) Jvf O f Oz O ) Jv P P P ) Jv P
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! " # $ % & ' ( GMODE:LOGIC K1::H1=(A*(~C*(D*~B))) K0::H0=(~D*(B*~C)+D*(C+B)) F1:F F0:F 4 MODE K1
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P
|
q K0
|
P
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p REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 | NGID1 cpu0/regs/ea/SLICE_1250 SLICE R23C13B )
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) Jv O O O ) Jv O O O a Jv{J P {J P{^ P a Jv{J P
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=(~B+~A) K0::H0=(~A+C) F1:F F0:F 4 MODE K1
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{J P
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s K0
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{^ P
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r REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1251 SLICE R18C19A )
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a Jv{J O {J O{^ O )f fz )f fz ) ) ) a u u u$ M) W W X a M) #( W ): W ): X ): M) #( f ): f ): f ): M) #( f ' f ' f ' M) #( f ( f ( f ( a u u u$ ) Jvf P
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! " # $ % & ' ( SMODE:LOGIC K1::H1=(~B*(A*C)+B*(~A*D+A*(D+C))) K0::H0=(~D*(~B*C)+D*(C+B)) F1:F F0:F 4 MODE K1
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f P
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u K0
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z P
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t REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1252 SLICE R19C24D )
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) 0B 5 5 5 a $ a 0B, 4 , 4@ 4 M) Jv : O : O : O M) Jv : O : O : O M) =\ : Cn : Cn : Cn M) Jv : P
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(~D*B)+C*(B+D)) K0::H0=(~C*(~D*A)+C*(A+D)) F1:F F0:F 4 MODE K1
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: P
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w K0
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: P
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v REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1253 SLICE R19C21C )
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M) #( If ( If ( Iz ( M) : : : m m m ,J ,J ,^ M)ѡ W5 W5 X5 ) $ $ $ ) ) 0B 4 4 4 aҞ ҞҲ a $ a $ a $ a $ ) aҞ ҞҲ aO O$O a #( u (> u (> u$ (> a #( ( ( ( a #( (> (> (> a =\ , Br , Br @ Br a W , \ , \ @ \ a =\ , B , B @ B a =\ Br Br Br a a , $ , $ @ $ a #( , ' , ' @ ' a $ $ $ a 0B 6T 6T 6T a a 0B 4 4 4 ) h Hn Hn \n h Hm Hm \m M) 0B : 4 : 4 : 4 X y 1< y 1< 0B = X 1< 1V E >V M) =\ > E E M) Y y y Y y y > Eқ Eқ M)ѡ X ) a ) ߵ ߵa {= X $" $" a #( {= X >V >V a =\ {= X X X a W {= X 1< 1< a 0B x a u !iz !iz h A X E 1< E 1< M) 0B ^ X | ^= X | ^ X | ^U X | x ^ A X ^ {= X > Y | Z u ^ | ^ | Z 5 E 5 E ) X ) XJ ( X T %T )`F T x M M aS aS ) ) L L ;g ;g , X W ^ X W " W " W ; ; , , ( ( -D -D 2F L b% aS } } X {= X a a p p } o } o z} & z} & ( ; ~ ~ ' ~ ~ bj bj N? N? W b% aU aU W > EM EM M)S M)S : : 4 4 :M , ~ l% l% u l% u ;g , L 5_V 5_V )`F l% ~σ ~σ Ҙ Ҙ { h dm dm #j #j bg bg d_ } } 2+ 2+ 4 1ȉ 1ȉ Di Di Hf~ Hf~ If Di If[ , @ W ^ X ^ W X 2F 2Z { { X X d_ x_ ( ( ' ' W X If Iz W X :M :M If[ Iz[ u u$ u u$ , @ PAR_CLOCKSIGNAL 2 sclk_id cpu_clkgen # 8aPADDI {CLK
{"CLK zCLK z&CLK CLK VCLK CLK ZCLK zCLK z&CLK \{CLK \{"CLK \zCLK \z&CLK CLK
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(~A*C)+D*(C+A)) K0::H0=(~C*(~D*A)+C*(A+D)) F1:F F0:F 4 MODE K1
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CLK sCLK CLK
xtCLK xCLK \CLK CLK CLK pCLK CLK CLK CLK GCLK 5LCLK CLK ɑCLK 5CLK wCLK CLK ֫CLK \CLK ɑCLK CLK ! CLK " tCLK # sCLK $ wCLK % pCLK & BCLK '\CLK (ZCLK )\pCLK * B-CLK +\CLK ,\CLK -\GCLK . CLK / IzCLK 0 :aCLK 1 IzקCLK 2 BקCLK 3CCLK 4aCLK 5קCLK 6 GCLK 7 IzaCLK 8 BCLK 9 Iz֫CLK : B{CLK ; ,^ɑCLK <\CLK = CLK > CLK ? ,^קCLK @ IzsCLK A :wCLK B ,^ 6HCLK C@ BfCLK D ,^ BCLK E\ CLK F@CLK G BwCLK H CLK I B)CLK J BwCLK KCLK L IzCLK M VCLK N ,^CLK O ZCLK P ,^CLK Q CLK R ,^CLK S :sCLK T :CLK U :pCLK V IztCLK W wCLK X CLK Y X CbCLK Z ,^wCLK [ CLK \ CLK ] ,^ OCLK ^ X BfCLK _ \CLK ` u$CLK a X CLK b \nCLK c \mCLK d xקCLK e x-CLK f x)CLK g @CLK hҲ BCLK i ,^ CLK j IzwCLK k$ CLK l$ CLK m$ CLK n@CLK o CLK p
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y K0
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IzCLK קCLK L XCLK M f{CLK N fCLK O Iz{CLK P IzCLK Q f-CLK f : 4CLK IzCLK C@CLK Cw&CLK C CLK C CLK C CLK C CLK C uQCLK C sPCLK C [ CLK C Y CLK u%CLKA u%CLKB I%CLKA JF%CLKB I CLKA JF CLKB u CLKA u CLKB z%CLKA z CLKA $ CLKA $%CLKA @ CLKA CLKB @%CLKA %CLKB u^ { { { u^ z z {" u^ z z z u^ z& z& z& V Z Z Z Tu^ z z z Tu^ z& z& z& Tu^ H{ H{ \{ Tu^ Dz Dz \{" Tu^ Hz Hz \z Tu^ Hz& Hz& \z& Tx Tx < Tx Tx @ @ @ hD m m m hD m m m hD ,n ,n @n hD (m (m @n hD ,m ,m @m hD ,m ,m @m 0 . 4 . 4 B 4 0H 6H H 6H\ 6H 0D 5V D 5V\ 5 0H 5L H 5L\ 5L 0H 4 H 4\ 4 0 6H 6H 6H 0 5V 5V 5 0 5L 5L 5L " . ' . ' B ' "H ). H ).\ ). "D (< D (<\ ( "H (2 H (2\ (2 "H ' H '\ ' " ). ). ). " (< (< ( " (2 (2 (2 J:f O f Oz O J: P| P| P| J: O O O J: O O O J: O O O d J:{J P| {J P|{^ P| d J:{F O {F O{^ O d J:{J O {J O{^ O f fz f{ f{z{ w u u u$ O W W X O " W ). W ). X ). O " f ). f ). f ). O " f ' f ' f ' O " f~ (< f~ (< f ( u u u$ 1 ( ( @ u u u$ 1 w w w T Z Z Z T H H \ T H H \ J:b O b Oz O 0 5V 5V 5 t t t K ,ɑ ,ɑ @ɑ $ 0, 4 , 4@ 4 O J: : O : O : O O J: : O : O : O O = : Cb : Cb : Cb O J: : O : O : O O " Ib (< Ib (< Iz ( O :{ :{ :{ a a a ,J{ ,J{ ,^{ Oe Wֵ Wֵ X) 0 4 4 4 Қ ҚҲw $ { {${ $ $w Ҟ ҞҲ $C " u (2 u (2 u$ (2 " (< (< ( " (2 (2 (2 = , Bf , Bf @ Bf WT , \ , \ @ \ = ( Bp ( Bp @ B = Bf Bf Bf " " , , @ " , ' , ' @ ' 0 6H 6H 6H { { { 0 4 4 4 e ֵ ֵ ) u{ u{ u${ K uɑ uɑ u$ɑ Oe f֫ f֫ f֫ e u ֵ u ֵ u$) K u u u$ K uʍ uʍ u$ʍ 1 u u u$ K ɛ ɛ 1 uw uw u$w Te H֫ H֫ \֫ K T H H \ O f f f O f f f T 1 s s s 1 T dt dt xt T d d x T H H \ p T T T G G G 0 5L 5L 5L K ɛ ɛ K ɑ ɑ ɑ 0 5V 5V 5 T1 w w w TK Te ֫ ֫ ֫ TK H H \ TK ɑ ɑ ɑ TK ɛ ɛ t t t 1 s s s 1 w w w p . . B H H\ Z ZZ D D\p e .- .- B- H H\ H H\ HG HG\G O If If Iz O :a :a :a Oe Ifק Ifק Izק e .ק .ק Bק C a aa eק קק G G G O Ifa Ifa Iza . . B Oe If֫ If֫ Iz֫ .{ .{ B{ K ,Jɑ ,Jɑ ,^ɑ H H\ e ,Jק ,Jק ,^ק O1 Ifs Ifs Izs O1 :w :w :w 0 ,J 6H ,J 6H ,^ 6H = , Bf , Bf@ Bf = ,F Bp ,F Bp ,^ B D " D "\ , ,@ * * Bw e *ֵ *ֵ B) 1 .w .w Bw O If If Iz V K ,J ,J ,^ Z Z Z ,J ,J ,^ ,J ,J ,^ O1 :s :s :s O1 : : : O : : :p O Ift Ift Izt w " " O = W Cb W Cb X Cb ,F ,F ,^w J: ,J O ,J O ,^ O O = W Bf W Bf X Bf T H H \ u u u$ O W W X ThD Hn Hn \n ThD Hm Hm \m Te dק dק xק Te d- d- x- Te `ֵ `ֵ x) x , , @ = Қ Bp Қ BpҲ B ,J ,J ,^ O Ib Ib Izw $ $ " "$ 1, ,@ x x < , , @ , , @ ( ( @V ,Z ,Z @Z , , @ , , @ ( ( @p x , , @ OK Wɛ Wɛ X 1 u^ ,z& ,z& @z& OK Wʍ Wʍ Xʍ C K ,Jʍ ,Jʍ ,^ʍ ,F ,F ,^p 1 ,J ,J ,^ 1 ,F ,F ,^ 1 1 ,Jw ,Jw ,^w 1 ,Js ,Js ,^s OK Ifʍ Ifʍ Izʍ O1 : : : OK If If Iz O f f f 1 s s s O1 If If Iz e ק ק ק O W W X O f{ f{ f{ O f f f O If{ If{ Iz{ O If If Iz Oe f- f- f- O 0 : 4 : 4 : 4 O If If Iz 1| @ @ C@ 1|u @z @z Cw& 1| s @ @ C 1| s @ @ C 1| Y @ @ C 1| Y @ @ C 1| r% @ vP @ vP C uQ 1| r% @ v @ v C sP 1| W @ \ @ \ C [ 1| W @ \ @ \ C Y u% G G u% O W W I% O WG WG JF% O W
W
I O W W JF
u u z%
z )
)
$ ) )$% T E
E
@ T E E T E E @% T EG EG % y u^ y Tu^ Tx y hD U T 0 T 0 U T " T " T J: TU Td J: ΐ yΐ ? T O y T ? T O " yΐ 1 y T T 0 yΐ K T ? T O J: ? T O = ?ΐ O Uΐ Uΐ ?ΐ Oe T ΐ ΐ ΐ y T " y T = y T WT y T 0 yΐ yΐ e ΐ Te ΐ T ?ΐ O ΐ T T ΐ T1 ΐ TK U Uΐ 1 U Uΐ e Uΐ ΐ ΐ e Uΐ K ?ΐ O1 T = U T = U T yΐ ? O U T J: ? T O ThD y x ΐ 1 ?ΐ OK ?ΐ O ? T O 0 (m 1| (m 1|u (m T 1| s (m T 1| Y (m T 1| r% (m T 1| W yΐ ?ΐ O ? T O y T ΐ T T ΐ T T ΐ T yS y yS yS , yS S S S , S L U T F L , F ȼ T ȶ ȼ x, ȶ T ~ x, ~ TL TU T TF TL x, TF nΐ ~nn x,~n yn yΐ yn yn , yn ? ? T ?~ ? , ?~ y y T y y , y ?n ?ΐ ?~n ?n , ?~n Ln Uΐ Fn Ln , Fn ȼnΐ ȶnȼn x,ȶn n ΐ n n , n LS U FS LS , FS ȼS ȶSȼS x,ȶS ?S ? ?~S ?S , ?~S (dS (m (^S (dS , (^S (d (m T (^ (d , (^ T , O , O , Ox, Ox, q W O k W q W ] W k W ) > > Hp) 8aHp ] W PAR_CLOCKSIGNAL 1 pclk_id cpu_clk_i a XJ "F0 a X RDI0 XJ " X W R X R X W R textctrl.vsyncrc_i & BF0 C^OPOS B @ C^ 2[ 2[ ! ! 7 7 <> <> @ textctrl.vsync_cnt[10] ,zQ1 zA1 g @LSR y @LSR @zB0 D0 CFLSR ,z zN , @ , @ @ CF zN z zN puS puS S S ; ; , ; , zN sv sv sv sv ,z S ! ! 7 7 ; ; ?0} ?0} ? ? @ z z ,z @z vsync_o_c C|IOLDO CIOLDO C| C cpu0_data_out[7] ^ XJ BrQ0 v f B0B0 C OPOS v
wDIB5 %
kDIA3 XJ Br X B @ C ) v
w L %
k X B \A ? \A ? f B0 \A ? _ i _ i r u r u )1 )1 7 7 @ r u j j ) 4 ) 4 ) ) ) ) ) ) H H L f B0 f B0 k_cpu_we_RNIKJPB n ʟF1 C CE C CE C CE C CE C u]CE C s\CE C [)CE C Y(CE ʟ ɛ @ C @ " C @ C @ C @ v\ C u] @ v C s\ @ \( C [) @ \ C Y( ɛ F F BP BP d d 9 (w 9 (w 9 w 9 w ?6 ?6 ; ; @ ; @ " 9 w 8 T 8 T @ 8 T @ 9 w ?6 l ?6 l ; o ; o @ v\ ; o @ v 9 (w 7 [ 7 [ @ \( 7 [ @ \ leds_r[7] C IOLDO C IOLDO C C reset_cnt_1[3] c mF1 c \mDI1 m m4 Hm \m m4 Hm reset_cnt[3] c mQ1 b \nC0 c \mC1 i \nhB1 m m4 m4 Ej Ej Hn m4 Ej Ej Hm Ej Hnh Hn \n Hm \m Hnh \nh textctrl/bluerc_i g F0 g @DI0 h , @ h , textctrl/bluer[0] g Q0 w @>C1 h h G G ,> ,> @> N_67
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x REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1254 SLICE R21C20C )
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x vF0 @CC0 @[C1 u$4A0 u$LA1 u$D0 f!A0 f9A1 f A0 f5A1 v a a f5 a f a f9 /1 /1 ,C /1 ,[ u4 uL b? b? u a f! ,C @C ,[ @[ u4 u$4 uL u$L u u$ f! f! f9 f9 f f f5 f5 textctrl/data_from_video[2] Ja(DOB0 u$@C0 t u$D1 Ja( Ic Ic s8K s8K l1 l1 u@ s8K lC lC u u@ u$@ u u$ data_from_bios[2] %4DOA2 u$:B0 t u$A1 %4 y y M M ~ ~ u: ~ l+y l+y u u: u$: u u$ addr_o_c[12] f (Q0 X 6$A1 @ID0 @aD1 u$FD0 u$RB1 f'B0 f?B1 f#B0 f;B1 f u$D1 r u$ZD1 s @YB1 t u$C1 u f CC1 v f BTD1 w f D1 x f CPD1 y faD1 z @A1 TPADDO > f ( gP ( TT `.T gP ( _\( _\( _\ _\ ]md ]md p p uZ p u gP ( ` - ` - S - S - W 19 W 19 W 6$ _\ l l ,I ,a p uF p s s uR _\( ] ] f f f? ] f# ] f; ,Y p k k u ` - ]a @ ]a @ f C ]a @ ` ?< ` ?< f BT gP ( ` ` f ]a @ f CP k bF% bF% fa , _\ ]n ]n 8(Z 8(ZY* Y*`. f f' W 6$ X 6$ ,I @I ,a @a uF u$F uR u$R f' f' f? f? f# f# f; f; u u$ uZ u$Z ,Y @Y u u$ f C f C f BT f BT f f f CP f CP fa fa , @ cpu0_data_in_1[2] y ufF0 u$(DI0 fB0 X9M0 e M0 ,^ M0 M0 Iz=M0 M fM0 v =B0 v UB1 IzM0 ) uf u u( u$( W9 X9 ,J ,^ If= Iz= f f If Iz u u( u m m a{ a{ ] ] f a{ Vo Vo W9 u ~ ~ z z a{ )|j )|j #k a{ EK EK H0o H0o If= ] ] ] ` ` f ~ zy zy = zy U ] Sܯ Sܯ H6 H6 If #k U U d d #k &YY &YY ,J f f = = U U textctrl/data_from_video[7] v DOB1 fAC1 v f BHB1 v u
Y u
Y j F j F ]s ]s fA j F _ 5 _ 5 ]g M ]g M f BH fA fA f BH f BH data_from_bios[7] % DOA3 fGD1 v f BBA1
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! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(~B*D)+C*(D+B)) K0::H0=(~C*(~B*D)+C*(D+B)) F1:F F0:F 4 MODE K1
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% E
k E
k a\ a\ ]o ]o fG a\ ] | ] | ] 4 ] 4 f BB fG fG f BB f BB cpu0_data_in_1[7] ~
fF1 u$sB1 u$B1 fDI1 A1 K XʽM1 ,^ʽM1 ,^M1 ,^)M1 fM1 @D0 @D1 O IzM1 1 f gt f f Wʽ Xʽ ,Jʽ ,^ʽ ,J ,^ ,J) ,^) f f If Iz gt f gt ]g? ]g? ]ț ]ț pVO pVO , ]ț pVi pVi us pVO u ]ț SLc , SLc @uգ @uգ @u @u Cu Cu If SLc @{ @{ 60/ 60/ #Yo #Yo &Ya &Ya ,Jʽ 60/ #_ #_ ,G ,G ,J #Yo &YM &YM ,J) 60/ :G :G ?% ?% S S N' N' Ra Ra Wʽ ]g? f f f us u$s u u$ , @ , @ textctrl/data_from_video[6] v DOB0 f)C0 w f C1 v u
e u
e lIo lIo an an f) an ]] ]] ] ] f f) f) f f data_from_bios[6] % DOA2 f/D0 w f A1 %
M
M rT rT R R ]K ]K f/ R ] X ] X f f/ f/ f f cpu0_data_in_1[6] }
fF0 u$aC0 u$C0 fDI0 ZD1 K XʷM0 ,^ʷM0 ,^M0 ,^#M0 fM0 @A0 @A1 O IzM0 1 f gh f f Wʷ Xʷ ,Jʷ ,^ʷ ,J ,^ ,J# ,^# f f If Iz gh f gh rR rR ? ? Aț Aț , Aț ~c ~c so so ua ~c l% l% u rR ʺ ʺ Z ~c bj3 bj3 Vo Vo Wʷ ~c F@ F@ 'i 'i +\~ +\~ ,Jʷ F@ Bj' Bj' 60 60 + + ,J bj3 ]a ]a ` ` f Aț , F@ @ @ @ @ Cu Cu If Bj' @ @ B| B| 5m 5m ,J# ua u$a u u$ Z Z , @ , @ textctrl/data_from_video[5] Ja DOB1 fEC1 x f CDB1
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{ K0
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Ja Ic
Y Ic
Y @K @K R R fE R ]9 ]9 _ 5 _ 5 ] N ] N f CD fE fE f CD f CD data_from_bios[5] % DOA1 fKD1 x f CJC1 %
_
_ < < p p ] ] fK p l l b" b" ]y 3 ]y 3 f CJ fK fK f CJ f CJ cpu0_data_in_1[5] |
fF1 u$׃A1 iA1 fDI1 ^D1 Q sM1 ,^M1 ,^M1 IzʽM1 :)M1 @C0 @C1 N f%M1 2 f g8 f f s s ,J ,^ ,J ,^ Ifʽ Izʽ :) :) f% f% g8 f g8 jc jc lI; lI; u׃ lI; lw lw ] ] i ] $] $] ] ] ^ $] s lw C C U U , U , g8 ] ] ` ` f% lI; anܻ anܻ D܋ D܋ '܋ '܋ #SՑ #SՑ #S] #S] &YG &YG ,J &YG ,J C ze ze pW pW SpW SpW Hx~ Hx~ Ifʽ pW 8" 8" 1 1 4M 4M :) u׃ u$׃ i i ^ ^ , @ , @ textctrl/data_from_video[4] Ja DOB0 f-C0 u f CD1 Ja Ic
e Ic
e R R O-o O-o a\ a\ f- Ic
e B| 5 B| 5 R .H R .H ] A ] A f C f- f- f C f C data_from_bios[4] % DOA0 f3D0 u f CA1 %
k
k p p l l l 4 l 4 a ;, a ;, f C p ] ] f3 f3 f3 f C f C cpu0_data_in_1[4] { fF0 u$wC0 ]C0 fDI0 C1 [C1 \ZD1 Q mM0 ,^M0 ,^M0 IzʷM0 :#M0 N f M0 u u$GC0 / f g, f f m m ,J ,^ ,J ,^ Ifʷ Izʷ :# :# f f g, f g, j] j] l l uw l lI lI ~x ~x ] lI ~xs ~xs s s [ s HZ l ܑ ܑ $ܑ $ܑ m lI n; n; F F 'l[ 'l[ ,J 'l[ +&U +&U ,J 'l[ 1ȭ 1ȭ Du Du HBo HBo Ifʷ 'l[ 9U 9U :# g, ] ] f f f lI uG s uw u$w ] ] [ [ HZ \Z uG u$G textctrl/data_from_video[3] Ja.DOB1 u$^D1 y f[C1 Ja. Ic Ic M M b b l
l
u^ b ]y' ]y' f[ u^ u$^ f[ f[ data_from_bios[3] %:DOA3 u$XC1 y fUB1
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z REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1255 SLICE R21C20B )
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%: E E rT rT l% l% uX rT S:5 S:5 ]o ]o fU uX u$X fU fU cpu0_data_in_1[3] z
ufF1 u$.DI1 f B1 X?M1 e M1 ,^%M1 %M1 IzCM1 @B0 M fM1 u u$MD0 u u$eD1 IzM1 - uf u u. u$. W? X? ,J% ,^% % % IfC IzC f f If Iz u u. u o* o* n& n& aω aω f o* l o l o ac ac Vo Vo W? u ofI ofI P P z~ z~ aω )Z )Z #_ț #_ț ,G ,G ,J% o* F6 F6 % F6 @ @ IfC l o ~O ~O , n& an an f l o uM l o ue @ @i @i Ic Ic If f f , @ uM u$M ue u$e textctrl/data_from_video[1] v .DOB1 @OA1 z @B1 v . u
u
~M ~M S S ,O S , ,O @O , @ data_from_bios[1] %.DOA1 @UB1 z @D1 %. `U `U ,U `U >d >d , ,U @U , @ cpu0_data_in_1[1] x
F1 @1DI1 u$B1 u$B1 Z )M1 M1 M1 @B1
|
! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(~B*C)+A*(C+B)) K0::H0=(~C*(~B*D)+C*(D+B)) F1:F F0:F 4 MODE K1
|
Iz)M1 M1 L X)M1 P IzM1 v ID0 , Q ,1 @1 ) ) If) Iz) W) X) If Iz Q ,1 Q F F ~o ~o u ~o u Q | | c6 c6 '6S '6S ) '6S h h Q >1 >1 zU zU Q , '$s '$s D@s D@s If) ~o z z ӱ ӱ c6 3 3 D@ D@ V V W) 3 1
1
Dܩ Dܩ If zU I u u$ u u$ , @ I I cpu0_data_out[0] W Q0 s @;A0 C Y:OPOS v DIB2 %DIA0 @ \p C Y: v - % G G l l m m P+ P+ U U ,; P+ j j 9 9 9 5 9 5 ?l RA ?l RA Q1 zA1 q u$A0 u{jADA1 IjADA1 I
ADA1 u{
ADA1 z> y u{j W Ij W : I
: u{
y z y } } pl pl t t u } z z z z z p G p G S S V; V; W z |` |` z z p p S( S( W : z : z z u u$ textctrl/yptr[1] ! zQ0 zA0 q u$B0 u{pADA2 IpADA2 I
ADA2 u{
ADA2 z NzN u{p W Ip W L I
L u{
NzN z NzN {h< {h< {mm {mm ph ph u {mm z z zU zU }? }? ph SL SL W W R/ R/ NZ NZ W NZ P P N f N f W L {mm | | |P |P z F z F }
|
} K0
|
}
|
| REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/ea/SLICE_1256 SLICE R19C20D )
|
L z z u u$ textctrl/yptr[2] v F0 u{vADA3 IvADA3 I
ADA3 u{
ADA3 d u
u{v Ic Iv Ic ^ I
u
^ u{
d rT rT l72 l72 o - o - u
rT @2 @2 Cu- Cu- Ic @2 @ @ B|6 B|6 @
t @
t Cu
|
! " # $ % & ' ( 0MODE:LOGIC K1::H1=(D*~A) K0::H0=(D*C) F1:F F0:F 4 MODE K1
|
Cu
|
K0
|
Ic ^ Cu
|
~ REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1257 SLICE R22C15A )
|
Ic Ic M | M | b b t" t" u
^ textctrl/yptr[3] ufF0 u{|ADA4 I|ADA4 I
ADA4 u{
ADA4 uf u ) u{| f I| f @ I
) @ u{
u y]\ y]\ r r ; ; ) u a a ] ] f y]\ | | | C | C p p f @ | C r r , , ) @ textctrl/yptr[4] ufF1 u{ADA5 IADA5 I
#ADA5 u{
#ADA5 uf u ) u{ f I f : I
# ) : u{
# u l l ~5 ~5 ) l a a ft ft ` ` f u m m n& U n& U an an e e f : n& U ~x ~x ) : textctrl/yptr[5] q ufRF1 u{ADA6 IADA6 I
)ADA6 u{
)ADA6 ufR uX 5 u{ W5 I W I
) u{
) uX y]B y]B z z z z 5 y]B U8m U8m O O N N W5 N N N O O Na Na W z zȭ zȭ |> |> z " z " textctrl/yptr[6]
|
! " # $ % & ' ( 1MODE:LOGIC K1::H1=(~A*~B) K0::H0=(A*C) F1:F F0:F 4 MODE K1
|
fF0 u{ADA7 IADA7 I
/ADA7 u{
/ADA7 f g, u{ W I W I
/ u{
/ g, `/ `/ _D _D pz) pz) _D Sp# Sp# W g, \A& \A& P P O O O
> O
> W O
> a a , , textctrl/yptr[7]
|
K0
|
fF1 u{ADA8 IADA8 I
5ADA8 u{
5ADA8 f g8 / u{ W/ I W I
5 u{
5 g8 ] ] pV5 pV5 J J / ] SL/ SL/ V; V; W/ g8 _n _n _n C _n C S S W _n C p p textctrl/yptr[8] f\F0 u{ADA9 IADA9 I
;ADA9 u{
;ADA9 f\ gJ u
u{ Ic I Ic I
; u
u{
; gJ j\ j\ l+ l+ u
j\ F F @u @u Ic @u BR BR @u @u Ic @u Ic
Ic
M M a a u
textctrl/yptr[9]
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1258 SLICE R21C18C )
|
fhF1 u{ADA10 IADA10 I
AADA10 u{
AADA10 fh gV u
u{ Ic I Ic I
A u
u{
A gV p p l l u
l b" b" E E H0; H0; Ic E @]' @]' B( B( @o @o Ic B( sP sP l l u
textctrl/yptr[10] fF0 u{ADA11 IADA11 I
GADA11 u{
GADA11 f gh u{ W I W R I
G R u{
G gh ]m~ ]m~ p p n; n; ]m~ S S VJ VJ W S N N P P N x N x W W W R N x bX bX t t R textctrl/yptr[11] fF1 u{ADA12 IADA12 I
MADA12 u{
MADA12 f gt u{ W I W F I
M F u{
M gt ]aZ ]aZ p p ]aZ S S W gt _ _ _D = _D = S S W F _D = p p F addr_o_c[0] ufQ0 $ Iz 5.B1 2 Iz rA1 @ Iz )pA0 TPADDO v jADB1 JajADB1 Ja
ADB1 v
ADB1 %
ADA2 %pADA2 2 uf uo TT v j W Jaj W 4 Ja
4 v
E L %
E %p #`.T uo l1 l1 l1 l1 ~A ~A t; t; l1 a; a; W J W J W ~A A A ; ; E uo m C m C a . a . D . D . If 5. D . 1 '< 1 '< D D Hr Hr If r m C F F @u @u If )p a; ) ) x|6 x|6H H;Yf ;Yf rY6 rY6#`. m C a a V V W 4 m C ~ ~ 4 ~ T T E L If 5. Iz 5. If r Iz r If )p Iz )p addr_o_c[1] ufQ1 Iz 5B0 9
TPADDO v pADB2 JapADB2 Ja
ADB2 v
ADB2 %
ADA3 %vADA3 ) uf uo 9T9
T )' v p f' Jap f
Ja
)
v
^ %
%v A`.9T uo n n ~ ~ S2 S2 )' S2 ~G ~G aG aG f' aG )|6 )|66 6x x H H
|
! " # $ % & ' ( PMODE:LOGIC K1::H1=(~C*(~D*(B*A)+D*B)+C*B) K0::H0=(~D*A+D*(~B*(~C*A))) F1:F F0:F 4 MODE K1
|
`
|
K0
|
f ^ `
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1259 SLICE R24C19A )
|
f
f
j j ~ ~ > > ) ^ ~ @ ) Y Y Y Y If 5 Iz 5 addr_o_c[3] XJ Q1 Iz 6 A0 ; TPADDO v |ADB4 Ja|ADB4 Ja
ADB4 v
ADB4 %
#ADA5 %ADA5 ) XJ X? s ; T; T )! v | f! Ja| f
Ja
)
v
: %
# % A`F; T X? s RJ o RJ o P 5 P 5 E* - E* - Hr 19 Hr 19 If 6 X? s )| )| x| x| H& H&H9 H9Z U>ZZ Z>Z >Zh8Y6 h8Y6l`F RJ N N W
If 6 Iz 6 addr_o_c[7] XJ )FQ1 X 5A0 _TPADDO v ADB8 JaADB8 Ja
5ADB8 v
5ADB8 %
;ADA9 %ADA9 ) XJ )F X (< TT_T ? v W? Ja W
Ja
5
v
5 %
; % c`FTT X (< M % M % " "T " T "j. j. z zo_V o_Vc`F X (< \A % \A % f " f " 0. 0. W W ~S ~S ? ~S anS anS W? \A % ] ] R R O-
t O-
t W
f " Y j Y j ~ ~
f " A " A " 0. 0 0 5 5 X (< R - R - W 5 W 5 X 5 addr_o_c[8] f ):Q0 X 5(A1 TPADDO v ADB9 JaADB9 Ja
;ADB9 v
;ADB9 %
AADA10 %ADA10 + f ): gn (< TT ' v W' Ja W
Ja
;
v
; %
A % `.T gn (< p p z z }
|
! " # $ % & ' ( CMODE:LOGIC K1::H1=(~D*A+D*(~B*A+B*C)) K0::H0=(~C+(B*~D)) F1:F F0:F 4 MODE K1
|
}
|
K0
|
z z |N |N z z o o ' o W W c c DdM DdM W' M M }
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1260 SLICE R21C27D )
|
c c Dd Dd W
gn (< \A %z \A %z N 4 N 4 W 5( z p p 8"w 8"w { { Z ZvZ vZpY6 pY6`. W 5( X 5( addr_o_c[9] f )FQ1 X 5A0 ʙTPADDO v ADB10 JaADB10 Ja
AADB10 v
AADB10 %
GADA11 %ADA11 * f )F gz (< ʎTʙT - v W- Ja W
Ja
A
v
A E R %
G E % қ`.ʎT gz (< ]a 3 ]a 3 S - S - V 7* V 7* W 5 S - / / . .ɛ & ɛ &x xx! x!ɧlp ɧlpқ`. gz (< r " r " " " - bj bj W- gz (< S S N N W
|
! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(D*B)+A*(~B+D)) K0::H0=(~C*(D*B)+C*(~B+D)) F1:F F0:F 4 MODE K1
|
W
|
K0
|
W
r "
r " 0 0 E R H H NJ NJ E W 5 X 5 addr_o_c[10] f 'Q0 X 5A1 TPADDO v ADB11 JaADB11 Ja
GADB11 v
GADB11 %
MADA12 %ADA12 / f ' f ' TT ! v W! Ja W
Ja
G
v
G E F %
M E % `FT f ' j % j % l+ 4h l+ 4h a ;D a ;D O 4z O 4z R 2. R 2. W 5 a ;D ) = ) = = = M M !* !*yf yf_2 _2`F j % n. n. r r / / ! / ph/ ph/ fG fG \A \A W! / )G )G y y E O 4z N N W
f ' j % j % t t z z
t !
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1261 SLICE R21C26A )
|
!
|
! " # $ % & ' ( KMODE:LOGIC K1::H1=(~A*(B*C)+A*(~C+B)) K0::H0=(~D*(C*A)+D*(~A+C)) F1:F F0:F 4 MODE K1
|
] " ] " E E E F W 5 X 5 addr_o_c[11] f 'Q1 X 6 A0 ̗TPADDO v ADB12 JaADB12 Ja
MADB12 v
MADB12 f ' f ' ̌T̗T v W Ja W X Ja
M X v
M қ`F̌T f ' _@ _@ _ _ pM pM _ SG SG W f ' p !" p !" z j z j
|
K0
|
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1262 SLICE R19C25C )
|
X f ' \A % \A % O' 4 O' 4 W 6 SG 6 6 `YN `YNѪ\] Ѫ\]қ`F \A % O F O F W X W 6 X 6 wen_o_c n ʓF0 'TPADDO v%WEB J^%WEB J^ WEB v WEB ʓ ɛ T 'T )M v% fM J^% f J^ ) v )`. T ɛ )lL )lL )`. ɛ ;9 ;9 )M cM cM ]a ]a fM ]a `S `S fs fs j j m m bj bj f ɛ ) ) ) ) ) textctrl/un1_CPU_OE_EN_0_a2 r ufF0 v%CEB u%OCEB JX%CEB JR%OCEB JX CEB JR OCEB v CEB u OCEB & uf u )c v% u% fc JX% W JR% f JX W
JR ) v
u u P P )i )i )c u o`I o`I ~ ~ z z i i z pD; pD; eJ eJ fc pD; S(; S(; VJ VJ W > > b" b" eL eL f b" V V W
> h h
> s s u
u
y] y] * * ) textctrl/chars_bus[0] u{(DOA0 # @m6M0 u{( u
,m6 @m6 u
o0 o0 m m Pf> Pf> oh oh ,m6 textctrl/chars_bus[1] u{.DOA1 } @zPM0 u{. u
,zP @zP u
l=D l=D mSu\ mSu\ ~xf ~xf _z _z ,zP textctrl/data_from_video[0] v (DOB0 @=B0 s @eD1 v ( u
u
y] y] r5 r5 ;o ;o ,= ;o ,e ,= @= ,e @e cpu0_data_out[2] Y XJ CnQ0 t u$B0 C snOPOS JaDIB2 %DIA2 XJ Cn X Bp @ v C sn W Ja E# % X Bp < < |N A |N A |x |x p p l1 l1 u < i i 8 d' 8 d' ! b ! b 7 b 7 b <> b <> b 7 u 7 u @ v p Sp Sp N1 N1 Wu Wu W N1 a) a) R# R# E# u u$ cpu0_data_out[3] Z ,Q0 y fID0 C uoOPOS JaDIB5 %DIA3 , - @ v C uo f Ja % - V4 V4 P P b4 b4 ]m ]m fI V4 l l + (q + (q + w
+ w
<> o <> o @ v b4 f l d d fI fI textctrl/chars_bus[2] I(DOA0 hҲ CM0 I( Ic Ҟ CҲ C Ic C C B( B( B( 5 B( 5 6T U` 6T U` W W ɧ Nf ɧ NfҞ C textctrl/chars_bus[3] I.DOA1 hҲ CM1
|
! " # $ % & ' ( \MODE:LOGIC K1::H1=((((C*B)*A)+(~B*~A))*D)+((~B*~A)*~D) K0::H0=(~D*(B*C)+D*(~C+B)) F1:F F0:F 4 MODE K1
|
I. Ic Ҟ CҲ C Ic B| B| ф фP P O O< Hj < Hj A Aқ ?r қ ?rҞ C cpu0_data_out[4] [ Q0 u f CA0 C OPOS Ja
eDIB2 %
YDIA0 l @ C W Ja
e
%
Y l G G n& 5 n& 5 a .* a .* ] A ] A f C n& 5 n& ? n& ? ~ ~ H ~ H ~ - | - | @ Z @ Z : Y : Y @ l " w " w 6 6 1 f 1 f E< E< W E< q q
f C f C cpu0_data_out[5] \ Q0 x f C&A0 C OPOS Ja
wDIB5 %
_DIA1 " @ C f Ja
w E %
_ " T B T B G d' G d' B C B C S ;& S ;& f C& G d' dQ dQ N N - - @ B C S S ] ] f f f ] p p ( ( | | E f C& f C& textctrl/chars_bus[4] I DOA0 i ,^ BM0 I Ic
k ,J B ,^ B Ic
k C o C o 6 6 +P +P ,J B textctrl/chars_bus[5] I DOA1 i ,^ HM1 I Ic
_ ,J H ,^ H Ic
_ C o C o 6 6 ,J H cpu0_data_out[6] ] , OQ0 w f C0 C OPOS v
eDIB2 %
eDIA2 , O , N @ C v
e E %
e , N V Jn V Jn o Hv o Hv ] A ] A ] ' ] ' f V Jn JG JG Jn Jn +\ w% +\ w% ; ; ?0 ?0 ? ? @ ] A _ E _ E p2 p2 z z p2 t t E f f textctrl/chars_bus[6] u{ DOA0 j IzM0 u{ u
k If Iz u
k o` o` F F '$ '$ D D If textctrl/chars_bus[7] u{ DOA1 j IzM1 u{ u
_ If Iz u
_ o0 o o0 o m m Fd Fd @i @i If textctrl/line_cnt[0] d o Q0 o B0 o B1 p B0 k C1 _jADA1 _
ADA1
ADA1 jADA1 " Nh _j :_
) :
) j Nh Nh Nh }/ }/ U>] U>]] ] m~ m~o o oW W
>
> : =1 =1͜ ͜S9 S9) : 5 5) textctrl/line_cnt[1] f o Q1 o *D1 p C0 k A1 q B1 _pADA2 _
ADA2
ADA2 pADA2 Zh _p L_
) L
) p Zh * Zh | | U8 U8 h/ h/X; X; h/ D Dm m L m N N ) L r5 r58J 8J) * * textctrl/line_cnt[2] h p HQ0 p D0 k D1 q &D1 _vADA3 _
ADA3
ADA3 vADA3 H l _v ^_
қ ^
қ v l z z z z & l U>C U>C D D
^ x x z z қ ^ . .ɧ] ɧ]қ & & textctrl/line_cnt[3] j p TQ1 p C1 k C0 q C1 _|ADA4 _
ADA4
ADA4 |ADA4 T x
_|
@_
@
| x h h h h x y] y] F F
|
K0
|
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 NGID2
|
@ @ U U
U
` `& &+ +
@ + @
|
cpu0/regs/SLICE_1263 SLICE R18C26A )
|
@ @U U textctrl/chars_data[0] # mQ0 _ADA5 _
#ADA5
#ADA5 ADA5 m ql
_
:_
# :
# ql B/ B/ c c ` `͊ ͊CV CV
CVC C&6 &6I
t I
t
: ` V V V
b
b : textctrl/chars_data[1] } z2Q0 _ADA6 _
)ADA6
)ADA6 ADA6 z2 qz 5_ _
) )
) )5 qz BI BI c c ` ` y yu u5 2 2 ) y2A 2A )5 textctrl/chars_data[2] h BQ0 _ADA7 _
/ADA7
/ADA7 ADA7 Bl B@ _ _
/ )
/ ) l B@ɧ 42 ɧ 42x( x(N N Nܺ ܺ ) ɧ 42ɧ ɧ ɧ ܖ ܖ ) textctrl/chars_data[3] h BQ1 _ADA8 _
5ADA8
5ADA8 ADA8 Bx B@ /_ _
5 )
5 )/ x B@x G x Gx x 1 1/ x B@ ; ; 4 4 * * ) 1 1) ); ;)/ textctrl/chars_data[4] i , $Q0 _ADA9 _
;ADA9
;ADA9 ADA9 , $ , _ _
; қ
; қ , 8 8 & & -
t -
t
|
! " # $ % & ' ( KMODE:LOGIC K1::H1=(~D*(C*A)+D*(~A+C)) K0::H0=(~C*(D*A)+C*(~A+D)) F1:F F0:F 4 MODE K1
|
|
K0
|
-
t\ \ n n қ W WA AV5 V5қ textctrl/chars_data[5] i , 0Q1 _ADA10 _
AADA10
AADA10 ADA10 , 0 - _ _
A қ
A қ - #_
#_
%N %N / /p p G G #_
p p L L p V V ў ў қ p M Mқ textctrl/chars_data[6] j IQ0 _ADA11 _
GADA11
GADA11 ADA11 I J4 _ R_
G ) R
G ) J4 6T 6T~ ~x x# #J J #K KD D s s
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/regs/SLICE_1264 SLICE R12C23C )
|
|
! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(A*C)+B*(~C+A)) K0::H0=(~D*(B*C)+D*(~C+B)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
|
R
|
K0
|
͜ ͜ 2 2 ) R s 2 2 *M *M2J 2J) textctrl/chars_data[7] j IQ1 _ADA12 _
MADA12
MADA12 ADA12 I J@ _ F_
M ) F
M ) J@ B@ B@ 6 6 a a F ) 6 6} f } f ) F textctrl/font_bus[0] { _(DOA0 k$ M0 _( $ A A f f textctrl/font_bus[1] | _.DOA1 k$ M1 _. $
|
REG1
|
6
|
REG0
|
6 textctrl/font_bus[2] } _ DOA0 l$ BM0 _
k B$ B
kA A 7 X 7 X B textctrl/font_bus[3] ~ _ DOA1 l$ HM1 _
_ H$ H
_ o o H textctrl/font_bus[4] DOA0 m$ M0 қ
k $ қ
k] F ] F textctrl/font_bus[5] DOA1 m$ M1 қ
_ $ қ
_̸ o ̸ oD D textctrl/font_bus[6] (DOA0 n@#M0 (қ ,#@# қY Y m m,# textctrl/font_bus[7] .DOA1 n@)M1 .қ ,)@) қ ) ),) textctrl/tshift[0] u Q0 q @FD0 ) ) ,F ,F @F textctrl/hsync_cnt[2] " mQ1 " @mA1 q @@C0 x @B1 g @D0 } @zzD0 m m4 m4 ,m m4 ;y ;y ; ; ,@ ; , ;y ; ; , ;y ,zz ,m @m ,@ @@ , @ , @ ,zz @zz textctrl/hsync_cnt[1] " mQ0 " @mA0 q @4A0 x @D1 g @B0 } @zD1
m m4 m4 ,m m4 Gy Gy d d ,4 d , Gy , Gy ,z ,m @m ,4 @4 , @ , @ ,z @z textctrl/hsync_cnt[0] # m$Q1 # @mfA1 q @:B0 x @A1 g @~A0 } @ztC0
m$ wl wl ,mf wl Sy Sy S S ,: S , Sy ,~ Sy ,zt ,mf @mf ,: @: , @ ,~ @~ ,zt @zt textctrl/shift_7[0] q F0 q @(DI0 ,( @( ,( data_from_bios[0] %(DOA0 @7A0 s @SA1 %( % % 8d 8d ,7 8d ,S ,7 @7 ,S @S cpu0_data_in_1[0] w
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Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 H NGID1 i NGID2 NGID3 cpu0/regs/SLICE_1265 SLICE R10C21A )
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F0 @+DI0 u$A0 Z #M0 M0 M0
|
! " # $ % & ' ( KMODE:LOGIC K1::H1=(~C*(D*A)+C*(~A+D)) K0::H0=(~D*(C*A)+D*(~A+C)) F1:F F0:F 4 MODE K1
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Iz#M0 M0 L X#M0 P IzM0 + Q ,+ @+ # # If# Iz# W# X# If Iz Q ,+ Q phI phI l ȉ l ȉ u phI l%g l%g u
u
o` o` F F #
|
K0
|
S
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 J NGID1 |cpu0/SLICE_1266 SLICE R14C22B )
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S gh gh F @ @ If# V V Q
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~D*A+D*C) K0::H0=(~D*A+D*B) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
|
Q
|
K0
|
O O W# o` n& n& Fj Fj @ @ If z z ӽ ӽ @ Rs Rs os os nU nU u u$ cpu0_we u ` ufQ0 f u$D0 r u$0A0 s @MD0 t u$D0 u f CC0 v f B6C0 w f B0 x f C2C0 y f=B0 z @D0 n @B0 n @B1 p @
|
REG1
|
uf u u , , , u u , , , ,0 , @ u u$ , @ ,0 @0 textctrl/N_139 r uf F1 x @D0 f u$B0 r u$
|
REG0
|
)
|
Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 W NGID1 j NGID2 ? NGID3 @cpu0/SLICE_1267 SLICE R21C22C )
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,| / ) ) , textctrl/hsync_cnt[9] mQ0 mB0 % zA0 % {B1 h {B0 l {|A1 n zA1 { @{B0 m jm4 jm4 j j m jm4 _ Zn _ Zn l l z l w w { w {| jm4 r r z jm4 r r { r `s `s ,{ m m z z { { { { {| {| z z ,{ @{ textctrl/hsync_cnt[6] nQ1 @nA1 % {D1 h {D0 l {vD0 n zB1 { @{D0 n $m $m ,n $m y y sL sL { sL { sL {v sL v v z y ;w ;w ,{ ,n @n { { { { {v {v z z ,{ @{ textctrl/hsync_cnt[5] nQ0 @nA0 % {
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! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*D+C*B) K0::H0=(~C*A+C*D) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
|
C1 h {A0 l {jB0 n zD1
n m m ,n m yk yk y y {
|
K0
|
y { y {j y z ,n @n {
|
REG1
|
{
|
REG0
|
{ { {j {j z z textctrl/N_11 h {F1 h {C0 n zC1 { @{A0 { z z { z v v z z yw yw ,{ { { z z ,{ @{ textctrl/N_155_i h {F0 {B0 | B1
{jB0
{B1 zB0 {B1 znB0 zB1 { z z sR sR v v { v | v {j v { v z v { v zn v z { { | | {j {j { { z z { { zn zn z z reset_o_c i nF1 @A1 $ \A0 $ \A1 \ fA0 \ fA1 i \nVC0 n zhA0 2ZA1 D0 fC0 u$ C0 :[C1 ցD0 xD1 B1 4A0 xeD1 u$C1 _C1 1 !A0 < fB1 =B0 fwC0 u$D0 u$A1 ) PADDO $ GSR c n md ) ) A $ ,G ) md
|
Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 Y NGID1 a NGID2 M NGID3 Ncpu0/regs/SLICE_1268 SLICE R12C23D )
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|
! " # $ % & ' ( MODE:LOGIC K1::H1=(~C*(A*B)+C*(~B+A)) K0::H0=(~C*(A*B)+C*(~B+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
|
~% ~% , md ?yT ?yT H ?yT H 2 2 cT cT ] ] f ] f md HnV ?yT Zs^ Zs^ zh 2 H H 2 2 ! ! )C )C 2F bY bY cT ]gY ]gY f f f 2 > > l
l
u 2 c " c " 1 1 1s 1s :[ bY ց
|
K0
|
+ + d + Q Q + de ] p܅ p܅ t߲ t߲ u bY zQ zQ z z _ zQ ! ]gY f f f + [ [ = ] ]m ]m fw bY u bY t Ҙ t Ҙ u c " 1 3 1 3 3 i 3 i ( ( #5 #5 ,G #5 | | ( ( K@ K@ ? ? A ]m _\! _\! pz pz 4 , @ H \ H \ f f f f HnV \nV zh zh 2F 2Z f f u u$ :[ :[ ց ց d x 4 4 de xe u u$ _ _ ! ! f f = = fw fw u u$ u u$ textctrl/N_4_i
i nF0 mA0 mA1 mTB0 mlB1 @nB0 @nB1 ! @nPB0 ! @nhB1 " @mB0 " @mB1 # @mTB0 # @mlB1 n md md j j m j m md j j mT j ml j f\ f\ ,n f\ ,n f\ ,nP f\ ,nh f\ ,m f\ ,m f\ ,mT f\ ,ml m m m m mT mT ml ml ,n @n ,n @n ,nP @nP ,nh @nh ,m @m ,m @m ,mT @mT ,ml @ml textctrl/visible_2_i_o3_2 zF0 g @A1 j B0 z zN zN L L , zN yx( yx( , @ textctrl/N_126
|
REG1
|
p FF0 y @ C1 g @B1 j D0
|
REG0
|
F + + , 2 2 , + , @ , @ textctrl/N_124 % zF0 y @B1 g @C1 j ~A0
|
Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 c NGID1 h NGID2 NGID3 cpu0/regs/SLICE_1269 SLICE R14C24A )
|
z dzN dzN yw yw / / , / , / $ $ ~ , @ , @ ~ ~ textctrl/N_103_i j BF0 q @CE r @CE s @bCE t @fCE
B , @ , @ ,b @b ,f @f y y _< _< ) ) , _< ) ) , ) ,b ) ,f textctrl/y_cnt_s[0]
lF1 DI1 l 9 9 textctrl/y_cnte k FF0 CE bCE CE fCE F + b b f f + z< z< b f textctrl/yptr_5 rQ1 fA1 u$B1
|
! " # $ % & ' ( MODE:LOGIC K1::H1=(~B*(C*D)+B*(~D+C)) K0::H0=(~A*(C*D)+A*(~D+C)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
|
f&C0 fB1 A1 v B0 q u$C0 q u$C1 r 3 f& f& 3 z z p p eX eX f 3 y] y] u 3 p p f& p eR eR f 3 3 * * p u p u f f u u$ f f u u$ u u$ textctrl/y_cnt_s[1] F0 DI0 H H textctrl/y_cnt[1] Q0 fB0 fB1 u$A0
|
K0
|
f B0 A0 q A1 N N z z pD pD f pD f N y]& y]& u y]& a a f N z f f f f u u$ f f textctrl/y_cnt_s[2] F1 DI1 T T textctrl/y_cnt[2] Q1 f A0 fA1 u$8B1 2A1 q u$D0 Z Z ph ph ] ] f f f f f ph u8 Z 2 ph l% l% u f f f f u8 u$8 2 2 u u$ textctrl/y_cnt_s[3] \F0 DI0 \ f f textctrl/y_cnt[3] bQ0 f~A0 f B1 u$A0 A0 q B0 b l l z z p p f~ p e e f l p p u l z f~ f~ f f u u$ textctrl/y_cnt_s[4] hF1 DI1 h r r textctrl/y_cnt[4] nQ1 fB0 fA1 u$A1 A1 q C0 n x x z z px px eR eR f px f px l l o o u x z f f f f u u$ textctrl/y_cnt_s[5] F0
|
REG1
|
DI0
|
REG0
|
|
Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 d NGID1 g NGID2 NGID3 cpu0/regs/SLICE_1270 SLICE R14C23A )
|
|
! " # $ % & ' ( MODE:LOGIC K1::H1=(~A*(B*D)+A*(~D+B)) K0::H0=(~C*(A*D)+C*(~D+A)) REG1::::SD=0 REG0::::SD=0 Q1:Q Q0:Q F1:F F0:F GSR:DISABLED CLKMUX:CLK CEMUX:CE SRMODE:ASYNC LSRONMUX:0 M1MUX:M1 M0MUX:M0 REGMODE:FF 4 MODE K1
|
textctrl/y_cnt[5] Q0 fB0 fB1 u$ B0 A0 | u$ B1 zu\ zu\ pfD pfD ]yyT ]yyT f pfD eRoh eRoh fm fm `r `r ] ] f ] pV pV u ] pV pV u f f f f u u$ u u$ textctrl/y_cnt_s[6] F1 DI1 textctrl/y_cnt[6] Q1 .A1 w @,D0 . V V ,, . . ,, @, textctrl/x_cnt_s[0] z8F1 zbDI1 z8 z zb zb z zb textctrl/x_cnte } z8F1 {CE
{.CE zCE z2CE
|
K0
|
z8 tz { { {. {. z z z2 z2 tz ~s ~s { ~s {. ~s z ~s z2 textctrl/x_cnt_s[1] zF0 zDI0 z HzN z z HzN z textctrl/x_cnt_s[2] " zF1 zDI1 z TzN z z TzN z textctrl/x_cnt[2] # zQ1 u$A1 zA1 v &C0 | u$*D1
z ZzN ZzN y]w y]w l l u ZzN z l & l u* u u$ z z & & u* u$* textctrl/x_cnt_s[3] $
{(F0
{XDI0 {( fz~ {X {X fz~ {X textctrl/x_cnt[3] %
{.Q0 u$ B0
{dA0 | u$B0 {. lz~ lz~ y]w y]w lC" lC" u lz~ {d lC" u u u$ {d {d u u$ textctrl/x_cnt_s[4] &
{4F1
{^DI1 {4 rz~ {^ {^ rz~ {^ textctrl/x_cnt[4] '
{:Q1 u$2A1
{|A1 | u$D0
|
REG1
|
{: xz~ xz~ zn zn p p u2 xz~ {| p l
l
u u2 u$2 {| {| u u$ textctrl/x_cnt_s[5] ( {F0 {DI0 { z { { z { textctrl/x_cnt[5] ) {Q0 u$B0 {A0 w @ B0 { z z zJ zJ p p t t u z { zJ , u u$ { { , @ textctrl/x_cnt_s[6] * {F1 {DI1 { z { { z { textctrl/x_cnt[6] + {Q1 u$B1 {A1 w @&C0 { z z z}& z}& pz pz s s u z { z}& , , ,& u u$ { { ,& @& textctrl/vsync_cnt_s[0] , z8F1 \zbDI1 z8 z Hzb \zb z Hzb textctrl/N_4 - n z,F0 zCE z2CE \{CE \{.CE \zCE \z2CE z, z z z z2 z2 H{ \{ H{. \{. Hz \z Hz2 \z2 z "s "s | | z | z2 "s | | H{ | H{. | Hz | Hz2 textctrl/vsync_cnt[0] . z>Q1 \zA1 # C1 $ \B1 B1 z> y y Hz y o o y x( x( h< h< m m H Hz \z H \ textctrl/vsync_cnt_s[1] / zF0 \zDI0 z zN Hz \z zN Hz textctrl/vsync_cnt[1] 0 zQ0 \zA0 # A1 $ \D1 $C1 z zN zN Hz zN 1h< 1h< m m $ zN c c H Hz \z H \ $ $ textctrl/vsync_cnt_s[2] 1 zF1 \zDI1 z zN Hz \z zN Hz textctrl/vsync_cnt[2] 2 zQ1 \zA1 o \$C1 z zN zN Hz zN h h H$ Hz \z H$ \$ textctrl/vsync_cnt_s[3] 3 {(F0 \{XDI0 {( z~ H{X \{X z~ H{X textctrl/vsync_cnt[3] 4 {.Q0 \{dA0 o \ B1 p B1 {. z~ z~ H{d z~ b b H b H{d \{d H \ textctrl/vsync_cnt_s[4] 5 {4F1 \{^DI1 {4 z~ H{^ \{^ z~ H{^ textctrl/vsync_cnt[4] 6 {:Q1 \{|A1 & \A1 j C1 {: "z~ "z~ H{| "z~ ?n ?n W W H ?n Z Z H{| \{| H \ textctrl/vsync_cnt_s[5] 7 {F0 \{DI0 { .z H{ \{ .z H{ textctrl/vsync_cnt[5] 8 {Q0 \{A0 v DD1 & \D1 p A1 { 4z 4z H{ 4z w w D 4z 3J 3J H H{ \{ D D H \ textctrl/vsync_cnt_s[6] 9 {F1 \{DI1 { :z H{ \{ :z H{ textctrl/vsync_cnt[6] : {Q1 \{A1 & \C1 j A1 p C1 { @z @z H{ @z r r a a tl tl Q Q H @z w w " " " H{ \{ H \ textctrl/vsync_cnt_s[7] ; ,z,F0 z\DI0 ,z, z z\ z\ z z\ textctrl/vsync_cnt[7] < ,z2Q0 zhA0 & \~A0 p C0 C0 ,z2 z z zh z w w {" {" H~ {" zh zh H~ \~ textctrl/vsync_cnt_s[8] = ,z8F1 zbDI1 ,z8 z zb zb z zb textctrl/vsync_cnt[8] > ,z>Q1 zA1 & \C0 p A0 A0 ,z> !y !y z !y w w K K H K 6 6 6 z z H \ textctrl/vsync_cnt_s[9] ? ,zF0 zDI0 ,z zN z z zN z textctrl/vsync_cnt[9] @ ,zQ0 zA0 v 8B1 & \B0 & \B1 p D0 ,z zN zN z zN | | 8 | i i H i H | z z 8 8 H \ H \ textctrl/vsync_cnt_s[10] A ,zF1 zDI1 ,z zN z z zN z textctrl/visiblec_i B y F0 y @DI0 , @ , textctrl/visible D y Q0 w @8B1 F/ F/ ,8 ,8 @8 textctrl/font_data[0] E kf Q0 u @ M0
|
REG0
|
f U , @ U ] ] 6 6 S: S: f f A
A
) ) , textctrl/font_data[1] F kf Q1 u @%M1 f [ s ,% @% [ sf o f oP P
t q
t q d d ,% textctrl/tshift[1] G u
Q1 q @LA1
$ $ Y Y Z Z ,L ,L @L textctrl/font_data[2] H lf $Q0 v M0
|
Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 f NGID2 NGID3 cpu0/alu/SLICE_1271 SLICE R9C27D )
|
f $ ' ' * * 'H 'H d d textctrl/tshift[2] I v Q0 r @(D0 j j y y ,( ,( @( textctrl/font_data[3] J lf 0Q1 v M1
|
! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~B*D+B*C) K0::H0=(~C*B+C*D) F1:F F0:F 4 MODE K1
|
f 0 9 9 s8 s8 N N textctrl/tshift[3] K v Q1 r @.A1 v v y& y& ,. ,. @. textctrl/font_data[4] L mf Q0 w @M0
|
K0
|
f , @ ! ! Ge Ge kR kR t t 2 2 , textctrl/tshift[4] M w Q0 s @D0 / / n n gL gL J J , , @ textctrl/font_data[5] N mf Q1 w @M1
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 ) NGID1 cpu0/alu/SLICE_1272 SLICE R12C29B )
|
f , @ G G m m m! m! 5 5 ; ; , textctrl/tshift[5] O w Q1 s @B1 |/ |/ mn mn QgL QgL G G , , @ textctrl/font_data[6] P nQ0 x @M0 q , @ q
Ve
Ve de de M M ; ; , textctrl/tshift[6] Q x |Q0 t @B0 | @ @ z z N N , , @ textctrl/font_data[7] R nQ1 x @M1 w , @ wF F
V
V d d e e 5 5 , textctrl/tshift[7] S x Q1 t @D1 |I |I , , @ textctrl/shift[0] T q Q0 q @RB1 ) ) ,R ,R @R textctrl/N_96 U q F1 q @.DI1 ,. @. ,. textctrl/shift[1] V q
|
! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*C+A*D) K0::H0=(~A*C+A*D) F1:F F0:F 4 MODE K1
|
Q1 r @A0
|
K0
|
A A , , @ textctrl/N_97 W r F0 r @
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 * NGID1
|
DI0 ,
|
cpu0/alu/SLICE_1273 SLICE R12C28D )
|
@
|
! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~C*A+C*D) K0::H0=(~D*B+D*C) F1:F F0:F 4 MODE K1
|
,
|
K0
|
textctrl/shift[2] X r Q0 r @@D1 > > ,@ ,@ @@ textctrl/N_98 Y r F1 r @DI1 , @ , textctrl/shift[3] Z r Q1 s @A0 $ $ 8 8 , , @ textctrl/N_99 [ s \F0 s @DI0 \ , @ , textctrl/shift[4] \ s bQ0 s @A1 b , , @ textctrl/N_100 ] s hF1 s @DI1 h , @ , textctrl/shift[5] ^ s nQ1 t @D0 n , , @ textctrl/N_101 _ t `F0 t @DI0 ` nE , @ nE , textctrl/shift[6] ` t fQ0 t @C1 f q? q? ; ; , , @ textctrl/N_102 a t lF1 t @DI1 l t9 , @ t9 , textctrl/shift[7] b t rQ1 g @$C1 r w3 w3 Y Y ) ) ,$ ,$ @$ textctrl/N_114 c o F0 o DI0 Hh Hh textctrl/N_50_i e o F1 o DI1 Th Th textctrl/N_51_i g p BF0 p rDI0 B f r r f r textctrl/N_52_i i p NF1 p xDI1 N r x x r x textctrl/hsync_cnt_s[0] k # m F1 # @mHDI1 m tl ,mH @mH tl ,mH textctrl/hsync_cnt_s[1] l " mF0 " @mDI0 m m4 ,m @m m4 ,m textctrl/hsync_cnt_s[2] m " mF1 " @mDI1 m m4 ,m @m m4 ,m textctrl/hsync_cnt_s[3] n ! nF0 ! @n>DI0 n md ,n> @n> md ,n> textctrl/hsync_cnt[3] o ! nQ0 ! @nJA0 m @B1 { @|C1 @{
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 + NGID1 cpu0/alu/SLICE_1274 SLICE R15C28B )
|
C1 n md md ,nJ md Lr Lr & & , Lr ,| Lr ,{
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~C*B+C*D) K0::H0=(~C*D+C*B) F1:F F0:F 4 MODE K1
|
,nJ @nJ , @ ,| @| ,{
|
K0
|
@{
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 , NGID1 cpu0/alu/SLICE_1275 SLICE R12C29C )
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textctrl/hsync_cnt_s[4] p ! nF1 ! @nDDI1 n md ,nD @nD md ,nD textctrl/hsync_cnt[4] q ! n Q1 ! @nbA1 m @A1 { @| B1 @{D1
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~C*A+C*D) K0::H0=(~A*C+A*D) F1:F F0:F 4 MODE K1
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n md md ,nb md #yT #yT , #yT ,| #yT ,{ ,nb @nb , @ ,| @| ,{ @{ textctrl/hsync_cnt_s[5] r nF0 @nDI0 n m ,n @n m ,n textctrl/hsync_cnt_s[6] s nF1 @nDI1 n m ,n @n m ,n textctrl/hsync_cnt_s[7] t mF0 mBDI0 m l mB mB l mB textctrl/hsync_cnt[7] u mQ0 mNA0 % zD0 h | D1 l {C1 m l l mN l z z w w z z | w { mN mN z z | | { { textctrl/hsync_cnt_s[8] v m F1 mHDI1 m l mH mH l mH textctrl/hsync_cnt[8] w m$Q1 mfA1 % zB0 h {A1 l {B1
m$ l l mf l a a tl tl 4 4 z 4 wz wz { wz { mf mf z z { { { { textctrl/hsync_cnt_s[9] x mF0 mDI0 m dm4 m m dm4 m textctrl/hsync_cnt_s[10] y mF1 mDI1 m pm4 m m pm4 m textctrl/hsync_cnt[10] z mQ1 mB1 g @B0 y @B0 l {dA0 m @D1 @zC0 @{B1 m vm4 vm4
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K0
|
e
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 - NGID1 cpu0/alu/alu16/SLICE_1276 SLICE R14C31A )
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e Z _ Z _ m
|
! " # $ % & ' ( 5MODE:LOGIC K1::H1=(~B*D) K0::H0=(~D*A+D*B) F1:F F0:F 4 MODE K1
|
e ` ` , ` , _ y y {d ` > > , ` My My ,z y
|
K0
|
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 . NGID1 cpu0/alu/alu16/a16/SLICE_1277 SLICE R14C33D )
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eT eTeT (k eT (keT w eT wv v o% ] o% ]{G textctrl/N_81 u f CtF1 u f CB0 f Ct gt Bp gt Bp e >S e >S f C f C f C N_73 u f ChF0
PADDO f Ch gh Bp
gh Bp 8( < 8(
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! " # $ % & ' ( 9MODE:LOGIC K1::H1=(~A*D+A*C) K0::H0=(~A*D+A*C) F1:F F0:F 4 MODE K1
|
8
|
K0
|
p p 7 \ 7 \ o o
textctrl/N_83 w f F1 w f A0 f gV gV eX eX f f f N_75 w f F0 E PADDO f gJ R E
R gJ _D B _D B 8" d9 8" d9 bz bzZ d9 Z d9
textctrl/N_82 x f BF1 x f C8D0 f B gV B@ gV B@ e^ DD e^ DD f C8 f C8 f C8 N_74 x f BF0 G PADDO f B gJ B@ T G T gJ B@ 8" < 8" < i iv d9 v d9" d9 " d9I I } } textctrl/N_80 y fF1 y fCC0 f gVQ gVQ fC fC fC N_72 y fF0 t PADDO f gJQ t t {G t gJQ _D _D _D 5 _D 5 _D ' _D ' 8" 8" v v " " h& h& {G textctrl/N_78 z F1 z @C0 ! ! , , @ N_70 z }F0 f+ PADDO } ! f8 f+ l f8 !
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 / NGID1 0cpu0/alu/alu16/SLICE_1278 SLICE R15C32D )
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! " # $ % & ' ( FMODE:LOGIC K1::H1=(~B*(D@A)+B*(C@(D@A))) K0::H0=(~D*A+D*~B) F1:F F0:F 4 MODE K1
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B 5 B 5 c Ws c Ws 3 ? 3 ? ` ` v v k k l textctrl/un6_visiblelto10_0_o2_1 v F1 j B1 p p textctrl/N_88 { {F1 % zA1 { @{C0 { z z yx^ yx^ z z ,{ z z ,{ @{ textctrl/redr9_3 | ufF1 | u$ C0 uf uh uh u u u$ textctrl/redr9_11 q ufFF0 | u$ A0 ufF uR+ uR+ o o u u u$ cen_o_c p F1 ^}TPADDO ^rT ^}T f`. ^rT { { ct ct ]lL ]lL f`. addr_o_c[13] f (Q1 X 6B0 f u$C1 r u$TC1 2TPADDO f ( g\ ( 2T 2T :`. 2T g\ ( ] ] _\ _\ p+ p+ l l uT g\ ( ` - ` - S( .* S( .* W 6 _\ pzC pzC lC lC u _\ 8" 8" 3 3 1_V 1_V :`. W 6 X 6 u u$ uT u$T addr_o_c[14] uf Q0 X 6B1 f u$A1 r u$NB1 TPADDO uf uU TT `FT uU an an O' ' O' ' W 2R W 2R W 6 uU n;& n;& lI lI lIh lIh u lI n; n; F[I F[I
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K0
|
Yf
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 = NGID1 cpu0/alu/alu16/a16/SLICE_1279 SLICE R16C32B )
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Yf6Y6 6Y6`F lI l l uN W 6 X 6 u u$ uN u$N addr_o_c[15] uf Q1 f 5A0 f u$B1 r u$HA1 f 60C1 4TPADDO uf u[ s 4T 4T :`F 4T u[ s j f j f ] ' ] ' f 2R f 2R f 5 u[ s o` o o` o n; n; l1 l1 u l1 uH f 2R f 60 l1 n{ n{ lZ lZ aYZ aYZ EY* EY* :`F f 5 f 5 u u$ uH u$H f 60 f 60 red_o_c w F1 CyuPADDO CPADDO CPADDO Cyj Cyu C C C C @ C @| C @zb Cyj d d 8 8 @w @w @zb 8 @ @ @| @ @0 @0 :/ :/ 7 7 @ N_81_i b nF1 b \nDI1 n :m Hn \n :m Hn textctrl/N_21 } z,F0 } @zB1 z, nz nz ;w ;w ,z ,z @z textctrl/yptr uf\F0 fA1 q u$A1 uf\ u u a a f u l l u f f u u$ textctrl/x_cnte_0_1 zF1 } @zC1 z zN zN ,z ,z @z textctrl/y_cnt F1 B0 4B1 B0 B1 B0 8B1 B0 B1 ph ph / / ` ` ` 4 ` ` ` ` 8 ` ` 4 4 8 8 textctrl/yptr_5_cry_5 fFCO fFCI f f textctrl/yptr_5[11] fF0 f4B1 f gh gh `/ `/ f4 f4 f4 textctrl/yptr_5_cry_3 f-FCO f9FCI f- f9 textctrl/yptr_5[9] fBF0 fA1 fB gJ gJ ] ] f f f f f textctrl/yptr_5[10] fNF1 f B0 fN gV gV ]y ]y f f f textctrl/yptr_5_cry_1 fFCO fFCI f f textctrl/yptr_5[7] fF0
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=~C K0::H0=(~C*D+C*~A) F1:F F0:F 4 MODE K1
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f2A1 f g,h g,h ] ] f f f2 f2 f2 textctrl/yptr_5[8] fF1 fA0 f g8h g8h `/ `/ f f f textctrl/yptr_4_cry_6 u'FCO u'FCI u' u' textctrl/yptr_4[7] ufF0
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K0
|
f8B1 uf u u bF bF e e f8 f8 f8 textctrl/yptr_4[8] ufF1 fB0 uf v v j j f f f textctrl/yptr_4_cry_4 u'GFCO u'SFCI u'G u'S textctrl/yptr_4[6] ufhF1
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 A NGID1 #cpu0/alu/alu16/a16/SLICE_1280 SLICE R16C31D )
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fA0 ufh u u j& j& f f f textctrl/yptr_4_cry_2 u'FCO u'FCI u' u' textctrl/yptr_cry_9 fFCO fFCI f f textctrl/yptr_cry_7
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=~C K0::H0=(~C*A+C*~B) F1:F F0:F 4 MODE K1
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fGFCO fSFCI fG fS textctrl/yptr_cry_5 fFCO
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K0
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fFCI f f textctrl/x_cnt_cry[4]
{FCO {FCI { { textctrl/x_cnt_cry[2] {FCO
{ FCI { { textctrl/x_cnt_cry[0] zFCO zFCI z z textctrl/y_cnt_cry[4] FCO FCI textctrl/y_cnt_cry[2] GFCO SFCI G S textctrl/y_cnt_cry[0] FCO FCI textctrl/vsync_cnt_cry[8] zFCO zFCI z z textctrl/vsync_cnt_cry[6] _|FCO z#FCI _| H| z z# wP z H| wP textctrl/vsync_cnt_cry[4] _{FCO _{FCI _{ _{ textctrl/vsync_cnt_cry[2] _{FCO _{ FCI _{ _{ textctrl/vsync_cnt_cry[0] _zFCO _zFCI _z _z textctrl/blink_cnt_cry[4] ! FCO FCI textctrl/blink_cnt_cry[2] $ -FCO 9FCI - 9 textctrl/blink_cnt_cry[0] % FCO FCI textctrl/hsync_cnt_cry[8] ' m{FCO mFCI m{ m textctrl/hsync_cnt_cry[6] ) CnFCO m FCI Cn ,n m m xj6 m ,n xj6 textctrl/hsync_cnt_cry[4] * ! CnwFCO CnFCI Cnw Cn textctrl/hsync_cnt_cry[2] + " CmFCO ! CnFCI Cm Cn textctrl/hsync_cnt_cry[0] , # Cm{FCO " CmFCI Cm{ Cm cpu0/un1_state_122 " 2 I F0 $ Iz 5(A1 f 5 C0 X 6A0 X 6A1 X 6B0 X 6*B1 X 5B0 X 5B1 X 5B0 X 5.B1 Iz 6A0 Iz 6A1 Iz 6B0 Iz 6*B1 Iz 5A0 Iz 5A1 2 Iz ~C1 u$ B1 B0 B1 u$ 5"D0 u$ 5:D1 X (B0 X )C1 f 5B0 f 5B1 X 'A0 X ( D1 f (zB0 f (B1 f 6B0 f 6B1 B0 P I J f 5 f 5 J C C @] 3 @] 3 If 5( C @E 3 @E 3 If 5 @E 3 If 5 J @ 'N @ 'N If 6 @ 'N If 6* @ 'N If 6 @ 'N If 6 J M M O 'N O 'N W 6 O 'N W 6* O 'N W 6 O 'N W 6 J If ~ @ 'N S .0 S .0 W 5. S .0 W 5 S .0 W 5 S .0 W 5 O 'N W ( O 'N W %8 W %8 W ' W %8 W ) O 'N W ( O 'N a ! a ! f ( a ! f (z M a a u a ~ ~ S .0 f 6 S .0 f 6 S .0 f 5 S .0 f 5 ~ ~ S .0 eL 7* eL 7* f 5 S .0 p . p . u 5: p . u 5" If 5( Iz 5( W 6 X 6 W 6 X 6 W 6 X 6 W 6* X 6* W 5 X 5 W 5 X 5 W 5 X 5 W 5. X 5. If 6 Iz 6 If 6 Iz 6 If 6 Iz 6 If 6* Iz 6* If 5 Iz 5 If 5 Iz 5 If ~ Iz ~ u u$ u 5" u$ 5" u 5: u$ 5: W ( X ( W ) X ) f 5 f 5 f 5 f 5 W ' X ' W ( X ( f (z f (z f ( f ( f 6 f 6 f 6 f 6 cpu0/un1_cpu_reset_11 ;.F0 $ Iz 54C1 2 Iz lD0 2 Iz D1 ;. ; If 54 Iz 54 ; 1 1 E E If l ; ?%} ?%} BR (w BR (w @ A @ A If 54 E If If l Iz l If Iz cpu0/un1_regs_o_su_iv_0[0] @ I )4F0 $ Iz 5:D1 2 Iz xB1 I )4 JL (< If 5: Iz 5: JL (< C C If x JL (< C - C - If 5: If x Iz x cpu0/un1_k_cpu_addr_1_cry_0 $ I} 5=FCO I} 5IFCI I} 5= I} 5I cpu0/state_32_iv_i[5] f ̺;F1 f xeDI1 ̺; 8օ de xe 8օ de cpu0/k_mul_cnt_RNI6QASC ̺F1 d x׳CE e x9CE f x5CE ̺ o d׳ x׳ d9 x9 d5 x5 o yյ yյ a a d׳ a d9 a d5 state_o_c[5] N f ̺AQ1 A0 A1 A0 ׃A1 u$B1 u$kA0 u$B0 u$C1 QA0 {D1 u$D0 u$D1 A1 CM1 A1 _ \FD0 "uB0 "֍B1 . "C1 / C0 / B1 9 "iA1 ; [C1 C xD0 H UA0 H mA1 I !A0 I KD1 M A0 ] xCC0 C0 "/D0 u$ցD0 ZD1 A1 ׃A1 \׃A1 LA1 SA1 @mA1 "B0 "D0 )C0 gD0 D1 D0 x;B1 uC1 OA1 SA1
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 B NGID1 "cpu0/alu/alu16/a16/SLICE_1281 SLICE R16C31A )
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B1 "A1 "A0 C1 u$B0 MD0 N 4A0 O \A0 aD1 C1 \
C1 C0 C1 ;A0 eD1 "aC0 "yC1 xGC0 xeD1 "
C1 @ ;A0 @ SA1 v [C1 w u${D1 } "׃A1 ׃A1 ATPADDO ̺A >օ C C 6T AT E`F 6T >օ aS aS v1 v1 Z1 Z1 Z1 Z1 ) ) > > Z1 #A #A >e >e ׃ #A 8 8 b >e uk >e l
S l
S u l
S u
Ʃ u
Ʃ u #A >K >K Q >K zo zo { l
S u l
S u >օ րk րk u u րk S S Ʃ Ʃ C >օ ve ve v1 E E HF րk ϛ ϛ Ҙ Ҙ u Ҙ ֍ ϛ 5 5 5 ܯ ܯ ܯ P P ϛ ; ; i u 9 9 t t [ aS d րk }S }S U }S m u ! K aS dC ܯ 5 / >e s؉ s؉ uց }S Z Ʃ րk ׃ ve H׃ > L S S #A ,m Ҙ ; Ɨ Ɨ u ) zo g v1 U U u 4 4 d; }S u 9 O v1 S ϛ Ҙ Ҙ 9 >օ ƴ ƴ j j l+ l+ u b M E E E H }S } } a } ve ؉ ؉ H
ܯ Z1 ~a ~a t e ; a ; y t dG t @ @ de ve ؉ ؉
Z1 ; Z1 S ~a [ u
Ʃ u{ Ҙ ׃ j ׃ E "{ "{ Z Z GZV K_D GZV K_D E`F l+ kk kk u S
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=~A K0::H0=(~A*D+A*~B) F1:F F0:F 4 MODE K1
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|
K0
|
4 ; ׃ ׃ u u$ uk u$k u u$ u u$ Q Q { { u u$ u u$ HF \F u "u ֍ "֍ " i "i [ [ d x U U m m ! ! K K dC xC / "/ uց u$ց Z Z ׃ ׃ H׃ \׃ L L S S ,m @m " " ) ) g g d; x; u u O O S S " " u u$ M M 4 4 H \ a a H
\
; ; e e a "a y "y dG xG de xe
; ; S S [ [ u{ u${ ׃ "׃ ׃ ׃ state_o_c[0] A d ̺׳Q0 D1 kA0 mA1 \!B1 A1 D0 D1 _ \^D1 ` u$!B1 . "B0 . "B1 / D1 0 \C1 < xCC0 < x[C1 H D1 I 9A1 M AC1 B1 D0 /D0 \B0 A1 TC1
C1 1D1 eD1 xB0 D0 CC0 /D0 mA1 D1 xGD1 {D1 ID0 eD1
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 C NGID1 !cpu0/alu/alu16/a16/SLICE_1282 SLICE R16C31B )
|
D1 "
C1 "'C1 x'C1 "B1 ֍B1 D0 1 9A1 N FD0 D0 \D1 \B0 \aD1 MD0 C0 C1 "UA0 "mA1 A0 A1 " B0 " B1 % D0 % D1 u u$SA1 ~ A0 PADDO ̺׳ Pֵ Pֵ
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! " # $ % & ' ( 2MODE:LOGIC K1::H1=~D K0::H0=(~A*D+A*~B) F1:F F0:F 4 MODE K1
|
|
K0
|
S S
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 D NGID1 cpu0/alu/alu16/a16/SLICE_1283 SLICE R16C31C )
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,k ,k k S m S Q Q ?[ ?[ H! ?[ Z Z Pֵ U/ U/ ֤+ ֤+ U/ ֤E ֤E Q E9 E9 E E H^
|
! " # $ % & ' ( 2MODE:LOGIC K1::H1=~C K0::H0=(~D*C+D*~A) F1:F F0:F 4 MODE K1
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lu lu u! ֤E E E 7 7 7 7 Ds Ds Pֵ Ƅ Ƅ CG CG dC CG d[ ֤E Ds kk kk 9 kk A Ds CG / 'a 'a H ,k ֤+ q q T Ds I I
Ds 1 ֤+ e CG d S kk C kk ֤E { kk ֶ ֶ I U/ % % e ֶ 7
7 ' Ƅ d' 7 k k ֤E k7 k7 ֍ ֶ lu , , 9 q ֶ ֶ F ֤+ % H ?[ H % Ha ,k zu zu zu E o o U o m ,k ,k Q [ [ [ Ds Ds k7 lu b" b" )d )d
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K0
|
W
|
REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 E NGID1 cpu0/alu/alu16/a16/SLICE_1284 SLICE R15C32C )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 G NGID1 cpu0/alu/alu16/a16/SLICE_1286 SLICE R15C35B )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 H NGID1 cpu0/alu/alu16/SLICE_1287 SLICE R16C30A )
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b _ B _ B p2 ;J p2 ;J N ;J N ;J , C, o o , V p2 ;J z 4z z 4z 5 z 4z 5 p2 ;J l1 4z l1 4z u 5 o l1 4z o 2 o 2 u 60 N ;J M 4z M 4z , 5 M 4z , )p o z z a , z o n n , C, @ C, , V @ V 5 5 5 5 u 5 u$ 5 u 60 u$ 60 u u$ , 5 @ 5 f f u b u$ b , )p @ )p a a , @ W X W X f f cpu0/k_opcode[3] C IQ1 ~ PB1 \ 5(A1 \ B*A0 CB0 CB1 PLC0 PdC1 A0 A1 f ]fC0 - Iz;A0 8 \A0 8 \A1 : B1 = u$A0 ? u$C0 A @ ]D0 B PLC0 B PXA1 L OC1 N \ 6C0 N \ 6$A1 SA1 \ C&A0 5A0 OA1 A0 C1 KD1 @C1 D1 A0 \ zC1 u$ PjD1 A1 OhC1 \D0 xA0 xA0 xA0 C>A1 [C1 u$ PB0 @KD1 u$ OA0 \ 6A0 \ 6A1 @ 5A0 @ 5(A1 \ 'A0 \ (A1 X B0B0 X BHB1 \ B0 \ A1 \ )vB0 \ )B1 \ ODA0 \ O\A1 B*A0 BHB1 f OVD0 @ 6 A0 @ 6$A1 BD1 t @A1 I J^ J^ sV8 sV8 G G [ J^ @EG @EG A (k sV8 m 7 m 7 k @ k @ u O A (k S H@ S H@ ]y [J ]y [J f ]f m 7 m \ m \ P UN P UN , ] G ,K J^ C C s8љ s8љ sV8 ܅ ܅ H ܅ H ܅ ܅ K G m 7 , . , . , 6$ ' f ' f H m 7 l A l A u P l A , ;& , ;& C> S H@ p Hp p Hp Oh p Hp O p Hp PL sV8 R 7 R 7 A R 7 @ @ BH R 7 . . H 6 P UN \ A H@ H@ H O\ A (k S H( k @ u Pj A P . H 5( H@ E A( E A( H B* A C A C A PL A Pd @EG If; R 7 & & sV8 l l u l u l A , H@ , H@ PX E A( H 6 . H 6$ G S A ;& ;& H C& , . H . H . 5 s8љ ϡ ϡ , ' f H z sV8 d d . H 6 , . , 5 , . , 5( . E & E & H ' E & H ( S H( N @ N @ W B0 N @ W BH E & H E & H )v E & H ) H@ H OD A B* , . , 6 , A B @ O s8љ "ϧ "ϧ a a d S H( f OV P P H 5( \ 5( H B* \ B* C C C C PL PL Pd Pd f ]f f ]f If; Iz; H \ H \ u u$ u u$ , ] @ ] PL PL PX PX O O H 6 \ 6 H 6$ \ 6$ S S H C& \ C& 5 5 O O K K , @ H z \ z u Pj u$ Pj Oh Oh \ \ d x d x d x C> C> [ [ u P u$ P ,K @K u O u$ O H 6 \ 6 H 6 \ 6 , 5 @ 5 , 5( @ 5( H ' \ ' H ( \ ( W B0 X B0 W BH X BH H \ H \ H )v \ )v H ) \ ) H OD \ OD H O\ \ O\ B* B* BH BH f OV f OV , 6 @ 6 , 6$ @ 6$ B B , @ cpu0/k_postbyte[3] M fQ1 BC0 5 C0 F @ bC0 F @ zC1 J 5B1 O u$ 5B0 O u$ 5B1 _C1 u$ 6$A1 @D0 u$C1 @ 5B0 u$ hD0 @ )D0 [C1 @ C1 C0 C1 XD0 XC1 f;A0 f tB1 > f fT fT p p l7
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t p uM p z} z} N} W z} p N} W S W N} O O Wo O W O W V W= b b W X W X Wo Xo ` ` f f u r u$ r uM u$M I I W X W X W X W= X= WU XU W X f z f z cpu0/k_opcode[5] , Q [Q1 @ ( D1 5C1 6*B1 \ BA0 \ 5A0 CM0 u$KD1 'B0 \ PC0 f ]`B0 f ]rA1 ' ?B1 , u$ B*A0 7 u$ID0 7 u$[C1 : A1 ? u$D0 ? u$C1 E @ BHB1 5:D1 OA0 CB0 C0 f \A0 \C1 %B1 \ D1 \A0 C0 OVD0 D0 \aD1 @?B1 @C0 \ lD0 \ rA1 \ C0 \ C1 \ OVD0 B0B0 @ 6C0 @ 60C1 | ]D1 [ C C | = | = @ @ C @ H. H. OV | = R \ R \ U< I I H I ܝ ܝ % H. A A , BH | = . . z A: z A: C U< ] R \ UT UT p UT p UT f ]r U< ph Ul ph Ul f ]` A M '` M '` , ( A l . l . 7* 7* 5 l . 7* 7* 6* l . 3 @ 3 @ H B | = . . H 5 | = rZ rZ l l uK | = & & ' @ H4 H4 Q^ Q^ H P 6 6 ? z A: p ;, p ;, u B* l o o uI l o o u[ l o o u l u l . 5: @ O 6 " " p UT f \ I H & H y y ~ܯ ~ܯ " " {] {] Ha 6 ` ` ,? y , H l H r H H H4 H OV @ B0 . , 19 , 19 , 6 , 19 , 60 | = ' ' , ( @ ( 5 5 6* 6* H B \ B H 5 \ 5 uK u$K ' ' H P \ P f ]` f ]` f ]r f ]r ? ? u B* u$ B* uI u$I u[ u$[ u u$ u u$ , BH @ BH 5: 5: O O C C f \ f \ H \ % % H \ H \ OV OV Ha \a ,? @? , @ H l \ l H r \ r H \ H \ H OV \ OV B0 B0 , 6 @ 6 , 60 @ 60 ] ] cpu0/k_postbyte[5] N f
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B0 u$ PXA1 \A0 OPC0 u$ \B1 @ OC1 aD1 (D1 u$ OB0 @B1 @!B1 \ `B0 \ D1 \ OnD1 B6C0 BBA1 f OJB0 f OhC1 & B6C0 & BNC1 f gz H 5v \ 5v 6r 6r H B \ B P. P. ' ' gz jI jI ތ ތ a gz ]aG ]aG _ (k _ (k p H( gz `6 `6 _ o _ o ] N ] N f ]Z _ o T =T T =T G N G N , ] jI ~ܝ ~ܝ m m - ތ .ܗ .ܗ H
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 acpu0/alu/alu16/SLICE_1290 SLICE R17C32C )
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6NF0 ) u$ )D0 * u$ (C1 + @ )
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! " # $ % & ' ( ,MODE:LOGIC K1::H1=(D*C) K0::H0=~D F1:F F0:F 4 MODE K1
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A1 @ 6C1 u$ \B0 )D0 )D1 @ (C0 @ (C1 6N 5V 5V c / c / ]g & ]g & p p u ) 5V - - , )
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K0
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5V , 6 5V \ \ U< U< s ^x s ^x u \ p ) p ) - , ( - , ( p t $ t $ u ( u ) u$ ) u ( u$ ( , )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_1291 SLICE R17C30B )
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! " # $ % & ' ( ,MODE:LOGIC K1::H1=(D*A) K0::H0=~D F1:F F0:F 4 MODE K1
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, 6 @ 6 u \ u$ \ ) ) ) ) , ( @ ( , ( @ ( cpu0/N_156 M F0 - IzMD0 - IzeD1 DҲ[C1
` ` r` s r` s @c @c IfM @c Ife r` s s s Ƀ x Ƀ xҞ[ IfM IzM Ife Ize Ҟ[Ҳ[ cpu0/mode79_1 n f F0 @C0 f A1 f f f f f _& _& o o , , @ f f cpu0/optype31[0] l cF0 (C0 * u$ (A1 + @ (C0 @A1 @qB0 @B0 )B1 c , 6 6 )m )m , 6 = = . . z ' z ' ( . l ' l ' u ( = 5 ' 5 ' , ( z ' ) |6 |6 Aյ Aյ ,q ( ( u ( u$ ( , ( @ ( , @ ,q @q , @ ) ) cpu0/dec_alu/N_51 4F0 } 6A0 5(A1 4 4 4 5( 4 2" 2" 6 6 6 5( 5( cpu0/mode76_2 j uf F0 ( u$ (A0 > ZA0 u$ zC1 f D1 uf u " u " bF bF f u " y] y] Z u " o0 o0 u ( u " u z u ( u$ ( Z Z u z u$ z f f cpu0/dec_alu/alu_opcode103[0] ( uf (F0 u$ (C1 ( u$ )B1 * u$ (D0 + @ )C1 u$A0 )|C0 )C1 uf ( u ( u ( s * s * u ) u ( o` o` l=
P l=
P u u ( h * h * )| h * ) u ( u ( u ( s * s * u ( u ( l l / / , ) u ( u$ ( u ) u$ ) u ( u$ ( , ) @ ) u u$ )| )| ) ) cpu0/k_p3_valid Q0 u$ (A1 (B0 (tA0 7A0 ) u$ )|C0 ) u$ )B1 @ 6D1 u$D0 u$)C0 u$ \A0 @ P^B1 )pA0 $ 6 D0 $ 60C1 1 Q Q | | p p u ( $ $ ( (t Q 7 o !( o !( u )| p t $ t $ u ) | R 5 R 5 - - , 6 $ ). ). y] %z y] %z l l l l u y] %z m" m" k- k- u) y] %z m O m O k h. k h. u \ k h. l% N l% N ~ HX ~ HX , P^ )p - 6 - h 7* h 7* 60 u ( u$ ( ( ( (t (t 7 7 u )| u$ )| u ) u$ ) , 6 @ 6 u u$ u) u$) u \ u$ \ , P^ @ P^ )p )p 6 6 60 60 cpu0/mode79_5 s ufF1 ( u$ ) D1 ) u$ )D1 u$C0 fA1
uf u u b" b" f u o0 o0 k k u ) k o % o % u ) u u u ) u$ ) u ) u$ ) u u$ f f cpu0/dec_alu/alu_opcode_1[3] uf}F0 u$ (C0 )C1 uf} u u o* o* l l u ( o* l7 X l7 X ~ !" ~ !" ) u ( u$ ( ) ) cpu0/un1_postbyte0_2_3 A s XJ F0 Iz hD0 Iz D1 ) u$ )pA0
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K0
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XJ X " X " M ` M ` If M ` If h X " R R a a u )p If h Iz h If Iz u )p u$ )p cpu0/dec_alu/alu_opcode_0_sqmuxa ) uf )4F0 u$ (tA0 ) D1 ) u$ )A1 uf )4 u (< u (< t $ t $ u (t u (< P P ) t $ u ) u (t u$ (t ) ) u ) u$ ) cpu0/dec_alu/alu_opcode_4_1[3] ( uf (F1 u$ (D0 )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_1292 SLICE R17C31C )
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A1 uf ( u ( u ( , , )
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! " # $ % & ' ( ,MODE:LOGIC K1::H1=(C*A) K0::H0=~C F1:F F0:F 4 MODE K1
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, z 3 z 3 p ; p ; l
4 l
4 u ( u ( u$ ( )
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K0
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)
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1293 SLICE R11C33D )
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cpu0/dec_alu/alu_opcode_1_f0_0[1] ) uf )@F1 u$ (D1 uf )@ v (< v (< t" $ t" $ u ( u ( u$ ( cpu0/dec_alu/alu_opcode_1_f0_0[2] )4F0 )D0 )4 (< (< ) ) ) cpu0/dec_o_alu_opcode[0] \ uf (8F0 u$ (hDI0 (A1 uf (8 u ' u (h u$ (h u ' u (h u ' y] % y] % ( ( ( cpu0/dec_o_alu_opcode[3] _ (F1 (DI1 (D1 ( r ( ( ( r ( ( r ( ( ( ( cpu0/dec_o_alu_opcode[4] ` (8F0 (C1 (hDI0 (8 H ' (h (h H ' (h H ' ( ( ( cpu0/un3_dest_flags_2 W (DF1 (D0 (D T ' T ' ( ( ( cpu0/dec_alu/alu_opcode_4_1_f1[0] (8F0 u$ (zB0 (8 ' ' ~ ! ~ ! u (z u (z u$ (z cpu0/dec_alu/alu_opcode_4_1_f1[3] (DF1 )B1 (D ' ' %z %z ) ) ) cpu0/dec_alu/alu_opcode_4[1] * uf 'F0 u$ (B1 uf ' uR ' uR ' u ( u ( u$ ( cpu0/dec_o_alu_opcode[1] ] uf (DF1 u$ (nDI1 'A0 uf (D u ' u (n u$ (n u ' u (n u ' ~ !
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! " # $ % & ' ( @MODE:LOGIC K1::H1=(D*B) K0::H0=(~A*(C@D)+A*(B@(C@D))) F1:F F0:F 4 MODE K1
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~ !
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K0
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$ $ ' ' ' cpu0/dec_alu/alu_opcode_4[2] + (F0 (A0 ( ( ( ( ( ( cpu0/dec_o_alu_opcode[2] ^ (F0 (DI0 'B0 ( f ( ( ( f ( ( f ( n * n * ' ' ' cpu0/dec_alu/N_35 P OFX1 * u$ (C0 P OE OE rZ J rZ J l AL l AL lI ' lI ' u ( u ( u$ ( cpu0/dec_alu/alu_opcode_4_1_f0_0[1] * uf 'F1 * u$ 'B0 uf ' uX ' uX ' u ' u ' u$ ' cpu0/dec_alu/alu_opcode_2[2] BOFX1 + @ (B0 B Aa Aa u 4 u 4 ! ! * * , ( , ( @ ( cpu0/dec_alu/alu_opcode_4_1_f0_0[2] + (F1 + @ (A0 ( ( ( * * , ( , ( @ ( cpu0/dec_alu/alu_opcode_2[0] | 5LOFX0 @ (zB0 5L 4 4 i '` i '` ! ! , (z , (z @ (z cpu0/dec_alu/alu_opcode_2[3] } 6HOFX0 @ (A1 6H 5V 5V y 2 y 2 & & , ( , ( @ ( cpu0/dec_alu/N_6 'F0 | \ 5B0 \ 5"D0 ' ' ' b - b - H 5 b - H 5" H 5 \ 5 H 5" \ 5" cpu0/dec_alu/N_10 4OFX0 | \ 5A0 4 4 4 W 2. W 2. H 5 H 5 \ 5 cpu0/dec_alu/N_19 4F0 | \ 5D1 4 n 4 n 4 .H .H $ 7* $ 7* H 5 H 5 \ 5 cpu0/dec_alu/N_56 4F1 } 6B0 4 4 4 2 2 6 6 6 cpu0/dec_alu/i6_mux )4F0 } 6D1 )4 . (< . (< h - h - ~ - ~ - 6 6 6 cpu0/dec_alu/N_31 ~ P|OFX0 P FXA P| O P P O P cpu0/dec_alu/N_34 OOFX0 P"FXB O | OZ P" P" | OZ P" cpu0/dec_alu/N_42 BfOFX0 \ BFXA Bf A H B \ B A H B cpu0/dec_alu/N_48 AOFX0 \ B FXB A A H B \ B A H B cpu0/dec_alu/N_26 OF0 ~ PB0 O d O* d O* L L P P P cpu0/dec_alu/i4_mux OF0 ~ PA0 O N N L L P P P cpu0/N_350_1 e OF0 ~ PC1 P@A0 B PFB0
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1294 SLICE R16C34A )
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O N N Hv Hv Km Km PF N Lb Lb P N P@ P P P@ P@ PF PF cpu0/dest_reg48_3 ? OF0 ~ PA1 CD0 @ ObB1
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(~B*D+B*(A@D)) K0::H0=(~D*(C@B)+D*(A@(C@B))) F1:F F0:F 4 MODE K1
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O n N n N ; Lb ; Lb , Ob n N y M y M A A C y M P P P C C , Ob @ Ob cpu0/dec_alu/i5_mux BF1 \ BB0 B B@ B@ H B H B \ B cpu0/N_429 = N 5F1 \ BB1 N \ 6 A0 \ C>A1
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K0
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5 5& 5& b : b : H B 5& h : h : H C> 5& 7* 7* H 6 H B \ B H 6 \ 6 H C> \ C> cpu0/dec_alu/N_55 CbOFX0 , u$ B6C0 5.B1 Cb Bp Bp 3 3 5. Bp y ? y ? ~ ;P ~ ;P u B6 u B6 u$ B6 5. 5. cpu0/dec_alu/i2_mux_0 XJ AF0 , u$ B0B0 , u$ BTD1 XJ A X6 A X6 A a\ ;b a\ ;b s DD s DD u B0 a\ ;b s DD s DD u BT u B0 u$ B0 u BT u$ BT cpu0/dec_alu/N_66 , uf AF0 , u$ BHB1 uf A uR A uR A o ?H o ?H u BH u BH u$ BH cpu0/dest_reg47_3 R ,F1 \ BNC1 A @ ]A1 -C0 \UB1 , p p ] ] ; Nx ; Nx , ] ] ;V ;V H BN - P P | | HU H BN \ BN , ] @ ] - - HU \U cpu0/dec_alu/N_25 OF1 OC0 O p O* p O* O O O cpu0/dec_alu/N_154_i BlF0 CC0 PXA1 - IzAB0 Bl d B d B C d B G G PX G )a )a rZ " rZ " @o @o @o @o IfA C C PX PX IfA IzA cpu0/dec_alu/un1_alu_opcode103 )@F1 (C0 )@ (< (< $ $ ( ( ( cpu0/N_225_0 : f \F1 P^B1 f ]xB1 = u$D0 ? u$B1 f \C0 f \ g8 \D g8 \D _ 6 _ 6 pV pV l% l% u g8 \D f Y f Y f ]x _ 6 f 0 f 0 ; A^ ; A^ HX HX P^ l% u g8 \D f \ P^ P^ f ]x f ]x u u$ u u$ f \ f \ cpu0/N_150 O - IF0 - Iz_C1 DҲID0 DҲaD1 I J J If_ J CP CP 5 5z z] ]ҞI ]Ҟa If_ Iz_ ҞIҲI ҞaҲa cpu0/dec_alu_right_path_mod_i_1[1] 0 XJ AF1 - IzYB1 DҲOA1 XJ A X< A X< A Q _ Q _ DR DR @] @] IfY Q _ )| )| ɭ ɭҞO IfY IzY ҞOҲO cpu0/mode76_1 ` uf F0 u$ ~C1 uf u u u ~ u ~ u$ ~ cpu0/N_153 F ChF0 K ]A0 L OB0 CA1
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/mulu/SLICE_1295 SLICE R12C32C )
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Ch Bp Bp } G } G O } G z [ z [ ] Bp >S >S C ] ] O O C C cpu0/dec_alu/alu_opcode_4_m_1[4] , uf AF1 (zB0 uf A uX A uX A y] ? y] ? z 4 z 4 (z (z (z cpu0/dec_ea/next_state_cnv_0[0] 2gF0 \B0 2g 2L 2L u u u u H H \ cpu0/un1_state_36 ɣF1 B1 NB1 B0 WB0 5 A0 6 4A0 X x4B1 \C0 \WB0 xC1 O \B1 W D0 Y D0 x>C1 B1 T 2A1 2A1 1 ɣ ; ; L' L' W W N 4 d4 ; H ; EƝ EƝ HW d d d H Z Z d d> 2 2 ; i i W N N W W 4 4 d4 x4 H \ HW \W d x H \ d> x> 2 2 2 2 cpu0/un1_state_74_1 b ,yF0 B1 \D0 ,y ? ? H H \ cpu0/un1_state_74_2 r 0 ʓF0 \yC1 \A0 ʓ .ɛ .ɛ T~ T~ H .ɛ H~ H~ Hy Hy \y H \ cpu0/next_state_cnv_1[0] m ɗF0 3 \3D0 ɗ ; ; h h ?u ?u H3 H3 \3 cpu0/dec_o_ea_ofs8 vF0 2ZB0 AB0 D1 C1
A1 \BD0 v f f U>w U>w HB f e e * * < < < < - - 2F 2 2 k k A f z1 z1 f e 4 4 2F 2Z A A HB\B cpu0/dec_o_ea_ofs16 p }F0 2ZD0 GC0 C1
} H! H! |
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! " # $ % & ' ( /MODE:LOGIC K1::H1=(A*D) K0::H0=(A*C) F1:F F0:F 4 MODE K1
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K0
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ތ ތ )a )a 2F m m G H! 2F 2Z G G cpu0/k_ealo_cnv_0[0] 2sF1 5CE u$CE \ַCE CE \CE
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1296 SLICE R21C14C )
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CE CE CE CE SCE 5XCE CE ɝCE 5CE _ \CE ` u$CE 2ZC0 ;A0 A0 xC0 @oA0 T ևA1 B0 ^ ѧ 5 5 5 [ u u u$ ѧ Hַ Hַ \ַ č H H \ - s s - S S S 0H 5X 5X 5X č č ɝ ɝ ɝ 0H 5 5 5 H H \ [ u u u$ W wқ wқ ѧ M T? T? [ W wŁ wŁ č W wߵ wߵ ȯ ȯ - W wg wg s ȯߵ ȯߵ - X w 1< w 1< 0H w w M T?ߵ T?ߵ [ 8 W 8 M 8 8 d X 8Z 8 8 d 8Z ] k @ ] k 7 @ 6c 7 2@ 6c 2s 2@ 2@ ,U ,U 2F ȯM ȯM -Y -Y } } ; č ʍ ʍ y y / / $w $w -Y a a Ƅ Ƅ d / ,o $w և Ƅ \C \C C C 2F 2Z ; ; d x ,o @o և և PAR_CLOCKSIGNAL 2 sclk_id cpu0/un1_state_32 Z H%F1 [B0 C1 2ZA0 MD0 B1 \QA0 H% : : [ : t{ t{ : )y )y )I )I 2F : ? ? M M M : zj zj z z t{ K K HQ [ [ 2F 2Z M M HQ \Q cpu0/next_mem_state_cnv_0[0] k F0 _C1 S S _ _ _ cpu0/N_266 F0 A0 ҲHA1 +@0A0 CҲA0 DҲD0 ӄ ӄѪ ѪҞH ӄɏv ɏvҞ ɏv̭ ̭Ҟ ӄv v,0 ӄe e V:e V:e z} z} ҞHҲH ,0@0 ҞҲ ҞҲ cpu0/dec_ea/ofs16_0_a2_0 XJF0 B0 XJ X X N N b4+ b4+ ~[ ~[ cpu0/k_ind_ea[3] ( e Q1 P@C0 C0 D0 \C0 " BD0 +@
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! " # $ % & ' ( IMODE:LOGIC K1::H1=(A*(D*(C*B))) K0::H0=(~A*C+A*(~D*C+D*(C+B))) F1:F F0:F 4 MODE K1
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K0
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HH
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 a NGID1 cpu0/alu/alu8/SLICE_1297 SLICE R8C30C )
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(~B*A+B*(~D*A+D*C)) K0::H0=(D*C) F1:F F0:F 4 MODE K1
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E EH @ FMw wv v
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K0
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Z Z, w 4 ,< Y* Y*, wv vP PҞ w P+ P+ҞM P+Ҟa } } z} z} }M }M wP Pɉ ɉҞ Z 6 v
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [ NGID1 _cpu0/alu/alu8/SLICE_1298 SLICE R8C30A )
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H4
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! " # $ % & ' ( =MODE:LOGIC K1::H1=(D*(~C*~A)) K0::H0=(((C+A)+B)+D) F1:F F0:F 4 MODE K1
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K0
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 y NGID1 {cpu0/alu/alu8/SLICE_1299 SLICE R10C28D )
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. @@ H\ . B ,<@< H4\4 ,@ 66 ҞҲ 44 ,@ ҞaҲa ҞҲ ҞMҲM HH\H cpu0/k_ind_ea[7] , ' fQ1 \.A1 \A1 P4A0 PLA1 D0 A0 ,^MD0 \A0 " BA0 $ XD0 % IzD0 & :D0 ' :C0 ( XA0 ) XAB0 * ,^~A0 ,\@C0 .A0 /0A0 0ҲD0 3A0 4@C1 5A0 CҲ@D1 G B^D1 J : A0 ,^A0 :}D0 :A0 IzID0 X)C0 XID0 C0 C1 ) ,^UB1 <ҲGC0 <Ҳ_C1 ҲA0 p f gz gz _2ʺ _2ʺ 8(M 8(M + + H 8(M < <* *Ҟ@ _2ʺ p p _2ʺ 8( 8( +9 H@ +91 1
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(~C*B+C*D) K0::H0=(~A*(~D*(~C*B))) F1:F F0:F 4 MODE K1
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8
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K0
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2U 2U 4 4 : 4 : `6 _\ _\ Sp Sp N N W * N N W W WM \A' W/ W W= N W
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 *cpu0/regs/ea/SLICE_1300 SLICE R22C13B )
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W
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! " # $ % & ' ( ?MODE:LOGIC K1::H1=(((A+B)+C)+D) K0::H0=(((D+B)+C)+A) F1:F F0:F 4 MODE K1
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W< N[ Ee Ee :k Ee 9؉ 9؉ : Ee 1S 1S D7 D7 Hld Hld If= H:\: ^^ ,J; ,^; W X If Iz : : : : W X WM XM ,J ,^ : : ,J ,^ :k :k : : If= Iz= W/ X/ W= X= W< X< ,J[ ,^[ cpu0/k_ind_ea[2] ' e Q0 C1 \D1 P:B0 ҲBD0 #@A0 0ҲB0 3(D0 4@D0 AҲ[C1 DҲC1 E@RB1 F>C1 G BRB1 B0 ,@ID0 ,@aD1 -@D0 -@D1 .@A0 .@C1 /@C0 /@C1 = BB0 = BB1 \NB1 H UDM UDM HN R R . R . : ] ]H > |M |MR R, |M ҞB UDMw wɧ ɧҞ wɡ1 ɡ1Ҟ[ ɡ1Ҟ w } } zo zo ɧܖ ܖ (
.R ,a , , , ) ), , , , ,I ,R H\ :: ҞBҲB ,@ ҞҲ (( ,@ Ҟ[Ҳ[ ҞҲ ,R@R >> .R BR ,I@I ,a@a ,@ ,@ ,@ ,@ ,@ ,@ . B . B HN\N cpu0/dec_o_ea_indirect ,F0 =B0 ,^ BA0 ,^ B0 A0 : (B0 B OJB0 \ ]`B0 B (C0 ,^SA1 @;B1 2 :MD0 I Iz B6C0 B1 OPC0 Ҳ ]B1 ( : PA0 ( : PA1 ) ,^CC0 * : \B0 * : tB1 +Ҳ hD0 +Ҳ D1 >\ CA0 >\ CA1 N , , , r r= , 0w 0w 3p (k 3p (k 1 A( 1 A( ' ; ' ; ,J B , #e
#e
,J r #e
5 5 1 'N 1 'N : ( 3p (k (2 H" (2 H"
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K0
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HR
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 e NGID1 cpu0/SLICE_1301 SLICE R18C11C )
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HR . OJ
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~C*(B*~D)+C*(~B*A+B*(~D+A))) K0::H0=(((A+C)+B)+D) F1:F F0:F 4 MODE K1
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HRW [ W [H ]` #e
I 4 I 4 . ( , ,G ,G ,JS 0w dl dl ) ) ,; 0w :M 1 A( D ;& D ;& Hf >S Hf >S If B6 , " A " A (2 H" Q^ Q^ OP D ;& N N0 N N0 E H: E H: : P E H: : P , ,JC 5 : \ 5 : t
>
>Ҟ h
>Ҟ ' ;
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K0
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;
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 textctrl/SLICE_1302 SLICE R23C11D )
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; H C
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! " # $ % & ' ( 5MODE:LOGIC K1::H1=(~B*~C) K0::H0=(B*(C*A)) F1:F F0:F 4 MODE K1
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; H C
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K0
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HR J/ J/ [ [̭ Yj ̭ YjҞ ] == ,J B ,^ B ,J ,^ : ( : ( . OJ B OJ H ]`\ ]` . ( B ( ,JS ,^S ,; @; :M :M If B6 Iz B6 OP OP Ҟ ]Ҳ ] : P : P : P : P ,JC ,^C : \ : \ : t : t Ҟ hҲ h Ҟ Ҳ H C\ C H C\ C cpu0/N_324 \F0 A1 \A1
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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\ H
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NGID1
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cpu0/SLICE_1303 SLICE R19C11C )
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* * z} z} H\ cpu0/k_pp_regs[6] Q0 0A0 @D1 X x(D0 X x@D1 xD0 xDD1 0 v v @ d( d@ d dD 0 0 @ @ d( x( d@ x@ d x dD xD cpu0/k_pp_regs[7] |Q0 C0 4B1 X x.A1 xA0 x2A1 C1 DD1 | 4 d. d d2 D 4 4 d. x. d x d2 x2 D D cpu0/k_pp_regs[5] Q0 4A0 .A1 xB1 D0 N XC1 Y B0 x8B1 j j 4 j j j . j dž dž d dž
X dž dž d8 4 4 . . d x X X d8 x8 cpu0/k_pp_regs[4]
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! " # $ % & ' ( QMODE:LOGIC K1::H1=(~B*(~D+(A*C))+B*~D) K0::H0=(~A*B+A*(~C*B+C*(~D+B))) F1:F F0:F 4 MODE K1
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Q0 \0A0 :C1 4B1 xA1 C0 N RB1 W B0 Y B1 T A0 4 4 H0 4 { { sL sL & & : { 8u 8u n n 4 n d n 2 2 2 R 2 n H0 \0 : : 4 4 d x R R cpu0/N_283 ,F1 "C0 5 C0 C0 B0 4A0 T >C1 , " : : > Z Z o o : : V V _Z _Z 4 " " 4 4 > > cpu0/mode76_5 J )4F0 @ )D1 )4 (< (< > $ > $ , ) , ) @ ) cpu0/dec_op/state_3_sqmuxa_0 ,gF0 C1 ,g L L cpu0/dec_op/mode_4_0_a5_1_1[1] AF0 zC1 A A A ? ? L M L M z z z cpu0/N_880 - ֽF1 \A1 "oA0 ; aD1 R A0 \ fB0 u$uB0 C0 "1D1 ֽ TU TU ) ) Hk Hk H ) k k o u u 9 9 a Hk u u TU z z ph ph f TU y] y] uu TU k u u 1 H \ o "o a a f f uu u$u 1 "1 state_o_c[2] L e ̺9Q0 D0 }D0 u$A1 u$OA1 \C1 %B1 C1 C0 C1 W C1 X A1 Y X CD1 Z ,^D1 [ _C1 \ D1 ] ,^ OnD1 ^ X BB1 _ \XC1 "{C0 "֓C1 H yC1 I 'B0 M /D0 M GD1 Q @]C0 R C0 e HA1 B0 )C0 "AC1 u$oA0 \C1 A0 fD0 C0 B1 %B1 \C1 "C0 =B0 "B0 ;B1 yC1 xC0 @֍B1 C1 ևA1 xyC1 "A1 xA1 A1 ;A0 ! C0 H fC1 M \GC0 OA1 \A1 \D0 \OA1 D1 SA1 B0 B1 \D0 \D1 " C0 " A1 ? x3D0 ? xEC1 r \SA1 x u$A0 y "D0 y "D1 ~ C1 ' PADDO ̺9 ̩ ' ' ,G l ' ̩ ϡ ϡ ϡ ϡ q q Ҙ Ҙ } q l l l l u ϡ H ϡ ) ) % ̩ ϧ ϧ %) %) ϧ m m m q F0 F0 * * F0 B(8 B(8 @Q 3 @Q 3 S ; S ; W C B(8 6 6 ,J 6 _ * @Q 3 @Q N @Q N 6 H. 6 H. ,J On S ; V DD V DD W B m Ý Ý HX ϧ ϧ ϧ { ϧ ֓ y ϧ ) ) ' ) / ) G ) ) } } %) P P ) ) A q uo ) " " {C {C H ) %) ϧ ؉ ؉ ) % ϡ H ϧ ) = ϧ G G %) ; %) Pܻ Pܻ d ϡ 2Ҙ 2Ҙ ,֍ ϧ ϡ Ҙ Ҙ և n n g g ϡ HG O WM WM H ϡ ZҘ ZҘ H HO n R R S ) ܻ ܻ ߲ ߲ ߲ R Z Z H Z H ϡ Ҙ P v v d3 P dE R HS l u G G ϧ @Q N A ! A ! 6x 6x ,G l m m d d m ~m ~m t d t d uO ,] ~m lI lI ~x ~x t t H B(8 S^ S^ ] ] f ~ ~ y ̩ Ý Ý dy ) R Q Q @ܑ @ܑ d ~ an an f ~m d d ; ~m d d } } u u$ uO u$O H \ % % W C X C ,J ,^ _ _ ,J On ,^ On W B X B HX \X { "{ ֓ "֓ y y ' ' / / G G ,] @] H H ) ) A "A uo u$o H \ f f % % H \ " = = " ; ; y y d x ,֍ @֍ և և dy xy " d x ; ; f f HG \G O O H \ H \ HO \O S S H \ H \ d3 x3 dE xE HS \S u u$ " " cpu0/un1_state_13_0 F1 \D0 : : Zd Zd H H \ cpu0/dec_op/un1_state_104_1_a7_0_0 F0 'C1 f f ' ' ' cpu0/N_145 d dF1 \-D1 D1 C xD1 " B0 d ɴ ɴ v v $ $ H- m m d m Tܝ Tܝ H- \- d x " cpu0/dec_op/un1_state_55_0 UF1 2 Iz `B0 U r r |` = |` = z & z & p p S( S( If ` If ` Iz ` state_o_c[4] K f ̺5Q0 A1 וD1 u$A1 fA0 fA1 u$B1 u$[B0 u$yC1 u$D0 u$aD1 sB1 B0 B1 D0 D1 _ \@C0 . "D0 0 \A1 9 "oB1 ; =B0 ; UB1 C xC0 I ?B1 M ;B1 e 6B0 \C1 A1 A0 " A0 u$֍B1 B1 qB0 A1 7A0 #B0 x
B0 B0 B1 iA1 \7A0 oB1 "B1 x!B1 "D1 B0 u$D0 H fB1 M \;A0 O \C0 UB1 \D1 @-D1 AB0 YB1 D1 \B0 \B1 "gD0 "D1 xYB1 "A0 "A1 " D1 % B0 % B1 ? x-C0 ? xKD1 @ AB0 @ YB1 w u$QA0 w u$iA1 ~ B0 ~ B1 {TPADDO ̺5 2օ pT {T }`. pT 2օ 0 0 # # z z 0 P_ P_ ו 0 l/ l/ u 0 aq aq f aq f 2օ б/ б/ Z Z ph} ph} u l/ u[ l/ o m o m uy o m u l/ ua 0 / / s б/ + + + 2օ # # # z " " H@ б/ σ σ Z ]ț ]ț H σ #ț #ț o Z 4> 4> = U + Pm Pm d ? ; z 6 ]ț H z } } ph} u֍ + 2օ б) б) q б/ 7 # Ǫܝ Ǫܝ d
#ț I I + i W W H7 σ ț ț o σ Ǫܝ d! J J 0 kQ kQ u aq ]w ]w f " H ț U # 0M 0M H kQ Py Py ,- A Y Py W H W H #ț g #ț J dY #ț #ț # Ǫܝ Ǫܝ J y y d- 2օ g g dK / A / Y o m uQ o m ui σ σ ț
_ _ }]v }]v }`. ]ț E} E} H; ו ו u u$ f f f f u u$ u[ u$[ uy u$y u u$ ua u$a s s H@ \@ " H \ o "o = = U U d x ? ? ; ; 6 6 H \ " u֍ u$֍ q q 7 7 # # d
x
i i H7 \7 o o " d! x! " u u$ f f H; \; H \ U U H \ ,- @- A A Y Y H \ H \ g "g " dY xY " " d- x- dK xK A A Y Y uQ u$Q ui u$i cpu0/state_cnst_i_a15_11_0[0] 9 ,F0 5A1 'B0 , 5 ' 5 5 ' ' state_o_c[3] E e ̺EQ1 C1 @B0 sB1 A0 _ \RB1 . "C0 / C1 9 "WB0 9 "uC1 G AB0 G YB1 I -C0 Q @QA0 e 0A0 e NB1 \B1 ")C0 \A0 C1 kA0 D1 RB1 ;A0 "
B0 B0 aC0 C0 @֓C1 C1 C1 oB1 \CC0 ׃A1 A1
C1 "A0 ֓C1 GC0 1 ?B1 H fC0 M \AB0 P B0 [C1 B1 \B1 \C0 \=B0 GC0 _C1 A0 A1 \C0 fC0 f
C1 faC0 fyC1
u$D0
u$D1 B1 xAB0 x_C1 "C0 "C1 " A0 Q fWM0 z D0 z D1 CTPADDO ̺E ̯ fW fW 8T CT E`. 8T ̯ ф ф S S zh zh S _ _ , ̯ 6љ 6љ /ȿ /ȿ o o s ̯ # # j j HR 6љ A) A) A) lܻ lܻ /ȿ W /ȿ a a u lܻ %C %C A %C Y %C Z Z - _ ,Q ` ` 0 ` N Z ) %C P P H ф ~xϧ ~xϧ lܻ +! +! k +! ` R +! ] ] ; A)
~xϧ z z a o ~xϧ ,֓ # ) ) o o H H HC ) Z A) z G ~xϧ z) z) ? z o o f ] G G [ G # Xϕ Xϕ H P G P _ z) z) H H ф anϡ anϡ f anϡ f
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K0
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/SLICE_1304 SLICE R21C26C )
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KK KK H cy H= , @ s s HR \R " W "W u "u A A Y Y - - ,Q @Q 0 0 N N H \ ) ") H \ k k R R ; ;
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a a ,֓ @֓ o o HC \C ׃ ׃ " ֓ ֓ G G ? ? f f HA \A [ [ H \ H \ H= \= G G _ _ H \ f f f
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fa fa fy fy u u$ u u$ dA xA d_ x_ " " cpu0/N_1066 h . dMF0 . "A1 "B1 dM P2 P2 P2 " " cpu0/dec_op/un1_mode89_1 ufF0 u$_C1 u$ A0 uf u u l1
l1
u u u_ u_ u$_ u u$ cpu0/N_1553_1 ) dF1 C1 D1 ` u$ B0 \ fD0 "#B0 :UB1 }D0 xD0 oA0 1 EC1 ' d ɴ: ɴ: ? ? ț ț ț ț c c zգ zգ phܗ phܗ u phܗ ] ] f # ɴ: rZd rZd 6T 6T 1 1 :U ? ? hM hM } hM V؉ V؉ o ] pV pV E ' ' d u u$ f f # "# :U :U } } d x o o E E cpu0/N_912 E dF0 "A0 d [] [] ܋ ܋ " cpu0/dec_op/mode52_1 AF1 f \B0 A A A rB =? rB =? l+ N l+ N a Ux a Ux f \ f \ f \ cpu0/dec_op/mode52 f \F0 u$ 6B0 f \ g, \D g, \D j Z j Z lI N lI N l 42 l 42 u 6 u 6 u$ 6 cpu0/state59_1 i F1 \ C0 \D0 B1 u$ 6A0 H " " Q] Q] H " 37 37 _ _ ؉ ؉ z ' z ' p . p . u 6 H \ H \ u 6 u$ 6 cpu0/dec_op/state59_0 F1 \ B0 \C0 y y H y s& s& i i H H \ H \ cpu0/state59 F0 e
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! " # $ % & ' ( >MODE:LOGIC K1::H1=(~D*B+D*C) K0::H0=(~C+(~B*A+B*D)) F1:F F0:F 4 MODE K1
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C1 u$B1 SA1 C1 7 pe pe % } } p? p? k7 k7 u' pe cȭ cȭ EƗ EƗ H % P P Ý Ý d % Ɲ Ɲ cȭ Ho % P P ǘ ǘ d P _ % k7 u
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u S m m s s dA - - ȉ ȉ m R R H ȉ } } ؉ ؉ u' u$' H \ d x H \ Ho \o d x dA xA _ _ u u$ S S cpu0/dec_op/un1_state_54 ` ufF1 ` u$A0 uf v v t ߲ t ߲ u u u$ cpu0/N_1530_1 uf?F1 u$B0 u${C0 A0 UA0 uf? uX uX o` o` u uX o Ӈ o Ӈ u{ uX y]/ y]/ uX y]) y]) zw zw U u u$ u{ u${ U U cpu0/un1_state_44 [ uf3F0 \qB0 u$ B1 uf3 uR uR љ љ
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K0
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ω
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 textctrl/SLICE_1305 SLICE R23C8A )
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ω Hq uR u Hq \q u u$ cpu0/N_1542_1 HF1 \A1 C xC1 \D1 !B1 B0 u$ A0 " A1 A1 A0 A0 A1 ( H :Z :Z z z i
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H i
L L g g d i
i i Wa Wa H :Z ?w ?w ! i ω ω ~ω ~ω z o o lC
b lC
b u xܑ xܑ g ր7 ր7 } } } } ր7 :Z } H \ d x H \ ! ! u u$ " cpu0/dec_op/un1_state_50 F1 \C0 2 Iz ZA0 oA0
: : H : N N E E @] @] Cu Cu If Z zm zm o H \ If Z Iz Z o o cpu0/N_2023_2 H fʟF1 mA1 0 \D0 :B0 AB0 C0 H fD0 T uB0 fA0 fA1 fUA0 fsB1
u$B0
u$A1 וD1 . fʟ gtɛ gtɛ r r Q Q m r 03 03 H gtɛ _2 _2 p p : Q 9 9 A r gtɛ e~ e~ f 03 u gtɛ \A \A N N aw aw f aw f gtɛ e~ e~ fs aw s؉ s؉ u aw u ו gtɛ e~ e~ fU m m H \ : : A A f f u u f f f f fU fU fs fs u u$ u u$ ו ו cpu0/N_1587_2 } d;F1 yC1 0 \C0 0 \D1 ! A1 d; օ օ S S K K ټo ټo y K K K X{ X{ H X{ $o $o H K y y H \ H \ cpu0/N_1533 F1 ; OA1 < x=B0 D1 \D0 D0 0A0 C1 XC1 xA1 N :B0 % C1 ' Z Z } } O } Ǫ Ǫ d= Z s s ; ; b b z z Z W W H s A A A A A 0 ; X s ϧ ϧ ×) ×) d & & : ×) O O d= x= H \ 0 0 X X d x : : cpu0/un1_state_51 F0 \D0 \ fB1 :7A0 f f A A r`T r`T 6x 6x :7 f U U H r`T @KY @KY S S e e f H \ f f :7 :7 cpu0/N_1573_1 dsF1 aD1 וD1 "D0 ds V@ V@ - - ] ] a V@ - Ӎ Ӎ ו a a ו ו " cpu0/N_950 > F1 ցD0 r r }I }I | | p p ܩ ܩ ց ց ց cpu0/N_1027 I F1 I 3D0 M #B0 B0 C0 xD1 C1 P D0 6 6 } } 3 } # 6 ?
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@ @ d G G 3 3 # # d x cpu0/N_947_2 N IF0 C1 D0 I H H H cpu0/dec_op/N_1570 " d%F1 9 "QA0 d% V V m m Q Q "Q cpu0/dec_op/N_1576 # ̺ F1 A1 ̺ 8 8 } } cpu0/N_1586 * 9 d!F1 \D0 / D0 9 "]C0 \}D0 d! k k . . DY DY ǘω ǘω Y Y H DY kQ kQ } } k ] Y H} H \ ] "] H} \} cpu0/N_1065 ' / YF1 / B0 \kA0 D0 r \YB1 Y & & & ޞ ޞ ! ! Hk & o9 o9 HY Hk \k HY \Y cpu0/N_1553_3 ( ̺F1 / A0 A1 xA0 B0 ̺ V V бI бI ~ܵ ~ܵ ߲ ߲ ~ܵ ϕ ϕ ؉ ؉ V p߲ p߲ d { { d x cpu0/dec_op/un1_state_81_1_1 % / MF0
B0 M 2 2
cpu0/regs_o_CCR[7] A H Q0 ,^A0 ҲD0 BA0 ҲwC0 \A0 \D0 BSA1 |Nʺ |Nʺ UD UD #A[ #A[ ,J |Nʺ - - H - ] ] H UD: UD:d dɧ ɧҞ #A[ \ \ . ɧҞw \
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! " # $ % & ' ( 0MODE:LOGIC K1::H1=(B+A) K0::H0=(~C+D) F1:F F0:F 4 MODE K1
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K0
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.S ,J ,^ ҞҲ . B ҞwҲw H \ H \ .S BS cpu0/state59_4
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0
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& AF1 : B0 ? u$D1 @ OhC1 \B0 \B0 u$ 6D0 D1 +C1 @'B0 " A A A z N z N * Hp * Hp , Oh A | _ | _ N N | _ o o lC ' lC ' u 6 | _ z z z + | _ N N ,' N ȿ ȿ j[ j[ H N j j H | _ pD pD l1
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, l} l} u u u$ , Oh @ Oh H \ H \ u 6 u$ 6 + + ,' @' cpu0/un1_state59 }F0 6 RB1 \C1 6B0 D1 A0 } ! ! i i R ! H 6 ! R R H \ 6 6 cpu0/dec_op/k_ofshi_1_sqmuxa ) ֱF0 ֙D1 \ցD0 ֱ HU HU ӷ ӷ ֙ HU NϏ NϏ jϏ jϏ $؉ $؉ Hց ֙ ֙ Hց \ց cpu0/dec_op/N_314 * ,F0 ` u$D0 f
B0 :OA1 ,
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A A T T EN EN 9 9 :O u u$ f
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:O :O cpu0/k_cpu_data_o_4_sqmuxa fF0 f1D1 A fC0 f g,o g,o f f f1 f f f1 f1 f f cpu0/N_1559 F1 B0 B1 B0 u$D0 u$D1 ] x7A0 u$ B0 C0 > Z Z < S p p R | z] z] Y > @ C Zs Zs u u$ u u$ d7 x7 u u$ < < R R Y Y @ @ cpu0/N_972_2 dF1 B1 B1 C xA0 C xA1 Q @cD0 u$ D0 \C1 D1 \{D1 D0 @ցD0 A1 "C0 M \MD0 T {C0 C0 ? x!A0 @ MD0 C d hg hg hg ? ? W W H h h hg e% e% }ӷ }ӷ h ǼI ǼI 0 hg G G L L : : d! 0 M 0 HM e% M M .} .} 1 1 1 1 d 1 d 0 3 3 ,c ? Z Z # # > > s s u 1 A A 9 9 H{ M M ,ց 1 Xa Xa { Xa
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NGID1
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A1 f 5A0 f 5A1 X (C0 X (A1 f (tA0 f (A1 f 6C0 f 6C1 C0 R uf u W 6 X 6 W 6 X 6 W 6 X 6 W 66 X 66 W 5 X 5 W 5 X 5 W 5" X 5" W 5: X 5: If 6 Iz 6 If 6 Iz 6 If 6 Iz 6 If 66 Iz 66 If 5 Iz 5 If 5 Iz 5 u l ' l ' a . a . W 19 W 19 W 6 W 19 W 6 W 19 W 6 W 19 W 66 W 19 W 5 W 19 W 5 W 19 W 5" W 19 W 5: a . DR .B DR .B Hx 19 Hx 19 If 6 Hx 19 If 6 Hx 19 If 6 Hx 19 If 66 Hx 19 If 5 Hx 19 If 5 u s s u DR .B @ ' @ ' Cu % Cu % If )v u of o of o P P z z l ' u 5 l ' u 5( l ' a a W ( a W )
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cpu0/SLICE_1306 SLICE R11C18B )
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a . f 5 a . f 5 a V $ V $ W ( a W ( a f (t a f ( a . e 19 e 19 f 6 e 19 f 6 u y] y] a . e 19 e 19 f 6* u u u$ If )v Iz )v f 6* f 6* u 5 u$ 5 u 5( u$ 5( W ( X ( W )
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! " # $ % & ' ( DMODE:LOGIC K1::H1=(C*B) K0::H0=(~A*~D+A*(~C*~D+C*(B*~D))) F1:F F0:F 4 MODE K1
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X )
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K0
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f 5 f 5 f 5 f 5 W ( X ( W ( X ( f (t f (t f ( f ( f 6 f 6 f 6 f 6 cpu0/k_pp_regs[0] ,F1 \"C0 6 ^D1 \D1 B0 \B0 A1 D0 B0 xBD0 xHA1 , S S : : 9v 9v H" S ^ : K1 K1 H S : H K1 @C @C : 8e 8e S dB : : dH H" \" ^ ^ H \ H \ dB xB dH xH cpu0/N_1742_1 F1 A0 BD0 LA1 xD1 z A1 r r ?: ?: r B r L ?: ӊ ӊ L3 L3 d ӊ Q Q B B L L d x cpu0/k_pp_regs_0_sqmuxa_1 ,zF0 D1 D1 W C1 x,D0 ,z _ _ #p #p #p m m d, _ &I &I d, x, cpu0/un1_state_35 0 ʟF1 D1 0 \B0 O \D1 A1 ʟ :ɛ :ɛ :ɛ N~ N~ H $ $ H ] ] h h H \ H \ cpu0/un1_state_51_1 ɗF0 0 \A0 B1 ɗ d; d; ƣ ƣ d; H H \ cpu0/N_1104 F0 xRB1 Y A0 x&C0 NB1 f f I I n n N f I I ×V ×V dR n d& dR xR d& x& N N cpu0/k_cpu_we_3 W ` ufF0 ` u$DI0 u$A0 uf u u u$ u u u lI lI u u u$ cpu0/k_cpu_we_3_RNI4P5E [ ufֱF0 W CE X CE Y X CnCE Z ,^CE [ CE \ CE ] ,^ OCE ^ X BrCE ufֱ uU W Cn X Cn ,J ,^ ,J O ,^ O W Br X Br uU m> m> a a ) )
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 [ NGID1 cpu0/SLICE_1307 SLICE R23C16B )
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,
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! " # $ % & ' ( OMODE:LOGIC K1::H1=(~B*A+B*D) K0::H0=(~D*(~B+~C)+D*(~B*~A+B*(~C*~A))) F1:F F0:F 4 MODE K1
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,
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K0
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,
>
> ) %6 (w %6 (w V. JG V. JG O! A O! A W Cn
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu16/SLICE_1308 SLICE R14C10D )
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,
> O! A W Br V. JG ph HR ph HR SL HR SL HR 6 H" 6 H" + Q^ + Q^ ,J O
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! " # $ % & ' ( ;MODE:LOGIC K1::H1=(~C*(~A*(~B*D))) K0::H0=(C*~A) F1:F F0:F 4 MODE K1
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, 'H 'H ,J cpu0/k_pp_regs[1]
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K0
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F1 A1 ZD1 6 FD0 6 XC1 \B1 \C0 B1 x B0 x > d > " d x " " @ @ O O cpu0/N_279 HzF0 X x"C0 xD0 A1 xNB1 Hz 4_ 4_ +N +N P P d" P v v d 4_ 4_ P P j j dN d" x" d x dN xN cpu0/k_pp_regs[3] ̺lF1 (D0 5 B0 5 B1 xB0 (D0 D0 C0 FD0 B1 [C1 W A0 T ,D0 T DD1 HA1 ' ̺l ̬9 ̬9 #n #n ( ̬9 # # # ̬9 d ̬9 бV бV ( # K K бV w w w F w a a [ w ֒ ֒ бV , бV D ֒ H ( ( d x ( ( F F [ [ , , D D H H cpu0/k_pp_regs[2] OFX0 \(D0 \DI0 5 C1 W xB1 \A1 xA0 B0 B0 :B0 UB1 T B0 T 8B1 x6B0 ' - H \ - H - E E H( - \ \ \ Ǫ Ǫ s s d - hI hI ' ' H Ǫ p p d Ǫ ' d d s 8 8 : 8O 8O U Ǫ Ǫ 8 s s s d6 H( \( d x H \ d x : : U U 8 8 d6 x6 cpu0/N_327 ̺`F0 >C1 ̺` ̦E ̦E > > > cpu0/un1_k_p2_valid6_1 S ,F0 A0 [C1 , Q Q ܑ ܑ Q [ [ [ cpu0/N_1032 HF0 G ;A0 D0 kA0 AC1 r \eD1 z A0 H ( ( c c Ӈ Ӈ k A : : ? ? He Ӣʺ Ӣʺ V9 V9 ~ ~ ? d d ր ր ; ; ; k k A A He \e cpu0/N_952 V HgF0 A1 Hg 4L 4L cpu0/un1_mode109 _ ufF0 XM0 1 :D0 1 :D1 4 @D0 4 @B1 XD0 u$AC1 D1 @ A1 D0 uf u W X u o0P o0P bF bF V V W u P P , u lc lc bFY bFY W u uA P P c c , P bF E* E* : P , E* : : : : : , @ , @ W X uA u$A , @ cpu0/mode_7[2] 6 ufOFX0 1 :B0 4 @A1 XC0 u$5A1 @%B1 uf u^4 u^4 o`6 o`6 l= l= aϕ aϕ W u^4 l1 l1 ~ܩ ~ܩ ,% u^4 u
u
u5 l1 aܣ aܣ Dܣ Dܣ 1 1 : u^4 y]c y]c r r 8 8 , : : , @ W X u5 u$5 ,% @% cpu0/dec_o_p1_mode[2] ' < XJֱF0 7 IzA0 8 : B0 8 :4B1 9 :B0 9 :B1 : : B0 : :8B1 ; :A0 ; :A1 < ,^A0 < ,^.A1 = ,^A0 = ,^A1 > ,^A0 > ,^2A1 ? ,^A1
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 w NGID1 cpu0/SLICE_1309 SLICE R22C13A )
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9A1 IzC0 IzC1 XC1 \C0 ֍B1 C1 wC0 \A1 5A1 xD0 D1 ]C0 \/D0 ֓C1 x)C0 A0 GC0 = ,^QA0 > XD0 P C1 D0 +C1 \oA0 \ևA1 D0 'C1 A fA0 A fC1 x u$C0 x u$C1 X@C0 XXC1 :@C0 :^D1 IzC0 IzC1 :B0 :B1 ,^D0 ,^*D1 :]C0 :uC1 XJֱ XU XU RJ RJ . . K K Hև XU r r ϛ ϛ ֓ .
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! " # $ % & ' (
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K0
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~ ~ r o o H/ ϛ Ñ Ñ g g XU R R Q o ր ր 9 XU W o H . z7 z7 ֍ r ϕ ϕ ϛ w o H ր 5 ϛ Ë Ë s s d Ñ ] d) ր Ñ a a G Q )|P )|P #} #} ,JQ Q O O W Ë ܵ ܵ + K Ho o ܵ ܵ ' R a\ a\ f a\ u a\ u O W@ O WX #} 5 5 If 5 If Q O O D D : D : 5 :] 5 :u D @ @ Ic Ic If )|P %u %u 5 5 : 5 :4 D 1 1 : 1 : 5 : 5 :8 O D; D; 1 1 4 4 : 4 : D (l (l #5d #5d ,G ,G ,J ,G ,J. )|P # # #N #N ,J #5d ,G ,G ,J #5d ,J #5d ,J2 # #S #S ,J @ Ic Ic If Ic If 1 :@ (l ,J (l ,J* . 8 8 [ [ 1 4 4 :^ a\ eX eX f If Iz : : :4 :4 : : : : : : :8 :8 : : : : ,J ,^ ,J. ,^. ,J ,^ ,J ,^ ,J ,^ ,J2 ,^2 ,J ,^ 9 9 If Iz If Iz W X H \ ֍ ֍ w w H \ 5 5 d x ] ] H/ \/ ֓ ֓ d) x) G G ,JQ ,^Q W X + + Ho \o Hև \և ' ' f f f f u u$ u u$ W@ X@ WX XX :@ :@ :^ :^ If Iz If Iz : : : : ,J ,^ ,J* ,^* :] :] :u :u cpu0/N_873 1 ;.F1 1 :C0 \B0 u$GD1 \ID0 ֙D1 " D0 A fD0 A fD1 ;. ; ; : ; d d l l Y Y յ յ ֙ d ]s} ]s} p p uG d l l HI l l 9} 9} H ]s} f ]s} f : : H \ uG u$G HI \I ֙ ֙ f f f f cpu0/mode88_1[0] 4 F0 XA0 1 :A0 4 @D1 u$;B1 @+C1 o o G G ~ ~ u; o ,+ G ~ ~ a a W W W G , a D D 9 9 : W X : : , @ u; u$; ,+ @+ cpu0/state81 1 ;.}F0 \ B0 cD0 [ n\D0 [ ntD1 \ fD1 e BD0 :ID0 \D1 D0 1D1 kA0 , ;.} ; ; 5.P 5.P 3 3 d d b b B ; 9 9 :I 5.P E E b4 b4 f d e e eR eR ey ey nt ey n\ E R R E E H R ʺ ʺ 9 9 c b4 ~ ~ l l H R z z z z R 2| 2| 1 z k k k H \ c c n\ n\ nt nt f f B B :I :I H \ 1 1 k k cpu0/un1_state_7_2_i_o2_RNIFDCC1_0
HɣF1
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 cpu0/alu/alu8/SLICE_1310 SLICE R7C30D )
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?B1 gD0 @ D0 [ nPB0 D1 \D0 B0 D1 A0 \;B1 \֙D1 }D0 * Hɣ ۨ; ۨ; B B +o +o ? ۨ; g ۨ; ۨ; ' ' l l fb fb nP ǘ ǘ ' ' ǘܣ ǘܣ s s H ۨ; ƣ ƣ s 9I 9I ~Y ~Y ' Ǽ Ǽ U U ' | | H; 9I WӁ WӁ H֙ ~Y } ? ? g g nP nP H \ H; \; H֙ \֙ } } cpu0/state57[0] YF1 \A0 wC0 Y & & W W H & ܯ ܯ ӱ ӱ w H \ w w cpu0/dec_op/state_2_sqmuxa C MF0 \[B0 QA0 M 2 2 - - H[ 2 I I ! ! Q H[ \[ Q Q cpu0/un1_state_55_3 HF1 2 Iz fC0 [C1 CC0 H T T p p ]y ]y S S H0 H0 If f V V [ C If f Iz f [ [ C C cpu0/dec_op/un1_cpu_reset_11_1 F ,F0 :=B0 , f f ^ ^ S( S( 6 6 := := := cpu0/dec_op/k_cpu_addr_1_sqmuxa G ;.F1 :CC0 ;. ; ; :C :C :C cpu0/next_state10
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! " # $ % & ' ( 3MODE:LOGIC K1::H1=(~A*(~D*~B)) K0::H0=~A F1:F F0:F 4 MODE K1
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ʟF1 \UA0 \mA1 C0 iA1 @ B0 @ D1 C0 C0 C1 ʟ ɛ ɛ y] y] vK vK HU vK Hm vK i րQ րQ ~ ~ րQ ~ ~ ɛ vK o o o o HU \U Hm \m i i cpu0/dec_op/next_state21 K ʓF0 B0 \cD0 C1 ʓ ɛ ɛ E E o o E Hc ɛ Hc \c cpu0/next_state_4_sqmuxa \ !F1 A0 \]C0 D1 ! k k k H] k H] \] cpu0/dec_op/un1_next_state_3_sqmuxa L HɗF0 \gD0 \D1 D0 oB1 Hɗ ۜ; ۜ; zф zф iȿ iȿ Hg iȿ H iȿ u u o ۜ; ǘo ǘo ~ ~ Hg \g H \ o o cpu0/next_state_10[2] ,ɗF0 DI0 ,ɗ ; ; cpu0/next_state_10[4] ,F0 uC1 EDI0 , k E E k E k u u u cpu0/next_state_10[5] ,!F1 KDI1 ,! k K K k K cpu0/dec_op/next_state_cnst_i_1[0] P F0 \aC0 k k o o Ha Ha \a cpu0/next_state_10[0] F0 \IDI0 HI \I HI cpu0/dec_op/k_memhi_0_sqmuxa R ?F1 uB0 ? u u u cpu0/k_memhi_0_sqmuxa_RNIGVP52 3F0 ,^CE ,^CE ,^CE ׳CE 3 ,J ,^ ,J ,^ ,J ,^ ׳ ׳ }Ӂ }Ӂ ׳ / / cZ cZ 2 2 2 2 'ZG 'ZG #q #q ,J #q ,J #q ,J cpu0/mode53_0 c F0 ;B1 \C0 u$ 6C0 z ' z ' o .B o .B u 6 & & ǘ ǘ ; o o -s -s E E H ; ; H \ u 6 u$ 6 cpu0/next_state_0_sqmuxa_1
sF1 \A0 s @ @ W W H H \ cpu0/next_state_cnv_4[0] 2 3 F1 \D0 H H \ cpu0/mode53_0_RNIULGBO gF0 \ CE ɝCE CE
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K0
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g L H \ ɝ ɝ L 6 6 u u H u ɝ cpu0/dec_op/k_pp_regs60 Y HF0 @ A1 C0 xB0
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REG1 REG0 Q1 Q0 F1 F0 GSR K0K1MUX CLKMUX CEMUX LSRMUX OFX1 FXMUX SRMODE OFX0 LSRONMUX M1MUX M0MUX REGMODE ALU2_MULT FCO CCU2 WDO0 WDO1 WADO0 WADO1 WADO2 WADO3 WDO2 WDO3 WD0MUX WD1MUX WD2MUX WD3MUX WAD0MUX WAD1MUX WAD2MUX WAD3MUX WD0BUF WD1BUF WD2BUF WD3BUF WAD0BUF WAD1BUF WAD2BUF WAD3BUF DPRAM WCKMUX WREMUX NGID0 NGID1 zdata_io[0] PIO PT15B PADDI:PADDI TRIMUX:PADDT:::PADDT=#INV IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,CLAMP=ON DATAMUX:PADDO VREF:OFF PGMUX:INBUF ODMUX:TRIMUX INRDMUX:PGMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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H ۜo ۜo ǘU ǘU d d x cpu0/un1_state_23 ̺F0 5B0 6B0 aC0 3 \'B0 3 \9A1 @ C0 A0 B1 B1 x A1 \GD1 & ̺ o o P C P C . . . . . . 5 . 6 P C uK uK H' K K X X H9 X Ɨ Ɨ o a a d uK HG F F b b a b b ~ ~ 5 5 6 6 a a H' \' H9 \9 d x HG \G cpu0/dec_op/state_3_sqmuxa_2 [ ,sF1 ]C0 ,s @ @ ,6 ,6 m m ] ] ] cpu0/N_905 H;F1 wC0 {C0 H; օ օ w օ ټ؉ ټ؉ { w w { { cpu0/N_953 X H/F0 qB0 H/ ۺօ ۺօ ?) ?) q q q cpu0/dec_op/k_eahi_0_sqmuxa_2 ` 3F0 D0 3 cpu0/k_eahi_cnv_3[0] 1 ֽF1 C0 ֽ pU pU cpu0/dec_op/un1_state_80_0 b /F0 B0 / օ օ ^6 ^6 ; ; cpu0/k_eahi_0_sqmuxa_2_RNI9C57A E ֱF0 u$ɝCE fַCE u$5CE u$ CE ֱ dU uɝ u$ɝ fַ fַ u5 u$5 u u$ dU rTZ rTZ l= l= uɝ l= aa aa ] ] fַ dU y y ~ϕ ~ϕ u5 l= u cpu0/k_pp_regs_12_sqmuxa ̺F1 [ nnC1 xA0 xAB0 ̺ V V f2 f2 iw iw nn V pd pd d V jd jd dA nn nn d x dA xA cpu0/dec_op/un1_state_82_0 f 9 dF0 xD0 d k k ɮ ɮ m] m] sS sS d d x cpu0/un1_state_82_1_RNI3MDV1 4 ̺yF0 u$ʙCE u$CE CE u$CE ̺y J uʙ u$ʙ u u$ u u$ J ƺ ƺ k k u
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u cpu0/dec_o_p1_mode[0] < XJ{OFX0 1 :C1 3 \-C0 ևA1 qB0 B1 x+C1 B0 cD0 \ A0 xMD0 xB1 B1 x5A1 MD0 $ XA1 % IzA1 & :C1 ' :'C1 ( XB1 ) XeD1 * ,^A1 = ,^oB1 > XD1 J : B1 P A1 ,^C1 :׃A1 : B1 IzUB1 X;B1 XUB1
B0 %B1 \{C0 \֓C1 2 IzBD0 2 IzZD1 3 XA0 3 X.A1 4 XD0 4 XD1 5 Iz B0 5 Iz4B1 R :C1 m :D0 m :D1 ,^D0 ,^D1 Iz B0 Iz8B1 ,^D0 ,^&D1 :B0 :B1 XJ{ X3l X3l DR DR @U @U B B @V @V IfZ B 5 5 #4 #4 ,J X3l Q Q љ љ c c H- Q a\ϧ a\ϧ w w և љ Ϗ Ϗ q љ z z Ϗ d+ c Ϗ ֤_ ֤_ / / c c H Ϗ Åȿ Åȿ dM d c ܩ ܩ d5 Ϗ ȿ ȿ M X3l RDP RDP O O W @U If @U 5ܻ 5ܻ : 5ܻ :' Q O O W Q O O We #4 ,J O Do Do '~o '~o ,Jo O W 5 24 24 : љ ,r ,r ț ț #4 ,J RDP W; O WU ,r
% w ϧ ϧ H{ ϧ H֓ @V IfB O W O W. O W O W O D D If D If4 D If D If O W& O W> D If D If8 #4 ,J& D 1 1 : 1 : 5ܻ 2! 2! :׃ 2! : O DU DU IfU @V 5 5 :< 5 :T DU 1 1 : 1 : O D D ( ( ,J ( ,J DR : : : H- \- և և q q d+ x+ c c H \ dM xM d x d5 x5 M M W X If Iz : : :' :' W X We Xe ,J ,^ ,Jo ,^o W X : : ,J ,^ :׃ :׃ : : IfU IzU W; X; WU XU
% % H{ \{ H֓ \֓ IfB IzB IfZ IzZ W X W. X. W X W X If Iz If4 Iz4 :< :< :T :T If Iz If Iz W& X& W> X> : : : : ,J ,^ ,J ,^ If Iz If8 Iz8 ,J ,^ ,J& ,^& : : : : cpu0/dec_o_p1_mode[1] 4 gF0 = :C1 > DD1 ? ,^D1 @ IzC1 A :A1 M C1 N ,^D1 O D1 P ,^ZD1 Q XC1 R ,^LA1 S :C1 T :[C1 U :A1 V IzB1 IzM0 4 @C1 ֓C1 3D0 @1D1 D0 WB0 \)C0 x#B0 AB0 P D1 A0 A1 \uB0 \֍B1 A1 i g nL If Iz nL nL ; ; , nL y] y] H H H) 3 -? -? H֍ y] r`: r`: Bʺ Bʺ 6x 6x : &o &o W / / A -? Hu -? g g ,1 / + + Bʺ B@{ B@{ u) u) J J : u) D 6x 1
1
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4Y 4Y : Bʺ 63 63 ,J J 6x +& +& ,JZ 6x X 6x ,JL 4Y : 1
:[ / % % r` r` @K @K If Bʺ @c @c @cyf @cyf @a @a @tl @tl @i @i If nL e; e; ~ϡ ~ϡ ֓ Ǫ Ǫ d# : : ? ? ? : : D D ,J ,^ If Iz : : ,J ,^ ,JZ ,^Z X X ,JL ,^L : : :[ :[ : : If Iz , @ ֓ ֓ 3 3 ,1 @1 W W H) \) d# x# A A Hu \u H֍ \֍ cpu0/path_left_addr_1[3] OFX0 NDI0 C1 B0
m N N m N m ʞ ʞ y y 8σ 8σ ʞ Ñ Ñ ϛ ϛ cpu0/k_forced_mem_size 2 ַQ0 \A0 וD1 D0 ַ U U H U ) ) :S :S ו :S H \ ו ו cpu0/k_pp_active_reg[3] ̺
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PAD
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Q1 S f;A0 S fSA1 T fD0 U fB0 V :UA0 B1 A0 D1 < fA1 X XD1 :A1 w u$oB1 x0A0 , ̺
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID ( NGID0 cpuclk_o PIO PB13A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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#: #: |M |M ]y
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f ]yA SK SK 6xK 6xK :U P P 8i 8i գ գ գ P . . ]yA ] ] f 6xK : ]yA pQ pQ t~ t~ uo a a d0 SK N9 N9 W W W f; f; fS fS f f f f :U :U f f W X : : uo u$o d0 x0 cpu0/state_cnst_0_a15_2_0[2] HF1 C0 ցD0 H ֵ ֵ ֵ Ҙ Ҙ ց ց ց cpu0/N_988 Y HF0 A0 H ֵ ֵ Ҙ Ҙ cpu0/dec_op/next_state_2_sqmuxa_1 p ?F1 3 \!A0 ? h h 'G 'G H! H! \! cpu0/next_state_cnv_3[0] 3 3 F0 3 \KD1 E E HK HK \K cpu0/un1_state_48 ֽF1 \C0 \A0 ֽ U U H U W W H H \ H \ cpu0/k_inc_su_5 - F0 \DI0 . H \ . H cpu0/N_1048 ,;F1 }D0 A1 x/D0 B0 -D1 x u$D0 ,; օ օ ؉ ؉ } օ , , d/ Uc Uc s s - s ~s ~s bs bs u s ߲ ߲ } } d/ x/ - - u u$ cpu0/N_1007 T ,/F0 oA0 ,/ օ օ ؉ ؉ o o o cpu0/N_1074 f ,cF0 !A0 C1 xB0 xB0 ,c ! #] #] d E E O7 O7 d ! ! d x d x cpu0/N_954 Q ,F0 B0 , dž dž cpu0/N_262 ^ cF0 1 :A1 4 @C0 C1 A0 c f f , f f f U>d U>d 6 6 1 1 : : : : : , @ cpu0/mode_7[1] 5 OFX0 1 :B1 4 @A0 A1 C0 " " j j , " y f y f c c 1
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/ օ օ F F S S ,/ օ , օ y) y) w w օ , , @ , @ ,/ @/ cpu0/k_pp_regs_4_sqmuxa_1 5 ,hF1 A0 5 D0 ,h cpu0/un1_k_pp_regs_4_sqmuxa 5 ,\F0 \BD0 &C0 ,\ & & {V {V HB & HB \B & & cpu0/dec_op/k_p2_valid7 F1 CC0 7A0 Q Q 7 7 7 Q C C C 7 7 cpu0/un1_state_17 O vF0 UA0 D0 =B0 O \A1 v @ @ e e U = H U U = = H \ cpu0/un1_state_18 # @ F0 B0 ID0 Y Y I G G I I cpu0/k_p3_valid_3 F0 +DI0 Q + + Q + cpu0/dec_op/N_218 7 ufF0 XB1 uf u u jG jG SL SL W W X cpu0/dec_op/un1_mode93 uf F1 >M0 u$ M0 XA1 uf u > > u u$ u y]w y]w z z > y]w z z p܋ p܋ l l u
u
u u jA jA S S W W X cpu0/dec_op/N_224_i OF1 tB1 O N N A A & & t t t cpu0/dec_op/N_236 F0 nA1 . " . " f f n n n cpu0/dec_op/mode_4_0_1[1] : F0 D1 cpu0/N_243 @ uf PF0 u$EC1 7 u$=B0 @ O\A1 u$ PdC1 uf P u OZ u OZ u Pd u OZ HL HL , O\ u OZ y] M y] M | )g | )g ph ph u= ph l% l% uE uE u$E u= u$= , O\ @ O\ u Pd u$ Pd cpu0/dec_op/mode_4_0_1[2] ? ufoF1 u$?B1 ufo u u s s u? u? u$? cpu0/dec_op/optype32[0] }F0 @B1 @wC0 @A0 } f f |x |x _ _ ؉ ؉ , _ ؉ ؉ ,w _ Q Q 2 2 , , @ ,w @w , @ cpu0/dec_op/N_19 t MF0 @}D0 M n2 n2 | | ,} ,} @} cpu0/dec_op/optype_3[1] ֱF0 @C0 ֱ U U , , @ cpu0/un1_state_37
N HF0 \ B0 \.A1 5 D1 6 LA1 X x B0 eD1 .A1 N ^D1 O \C1 D0 xZD1 8B1 * H ۜ ۜ ?v ?v y y e ۜ ^ ۜ б б dZ ?v H H. ۜ ǘ ǘ L ǘ Å Å s s d ۜ . H ǘ * * 8 H \ H. \. L L d x e e . . ^ ^ H \ dZ xZ 8 8 cpu0/dec_op/k_p2_valid8_3 u ufF0 CC0 uf uR uR e e m m C C C cpu0/dec_op/k_p2_valid8_4 F1 =B0 y y O O = = = cpu0/k_p2_valid6 F1 C0 ID0 I I I cpu0/state192 vF0 SA1 D1 v H H 1 1 S H \ \ S S cpu0/dec_op/un1_state_81_0 F0 YB1 *o *o e e Y Y Y cpu0/dec_op/next_mem_state_cnv_2[0] F1 @ B1 ? ? e e cpu0/dec_op/N_290 f}F0 u$eD1 u$/D0 f} gJ gJ j} j} lIU lIU u/ gJ jw jw ue ue u$e u/ u$/ cpu0/dec_op/mode75[0] XJF0 u$YB1 XJ X X \A} \A} pV pV uY uY u$Y cpu0/k_pp_regs_2_sqmuxa_2 6 ,F1 TC1 6 :B0 , T : T T : : cpu0/un1_k_pp_regs_10 ,}F0 C1 HA1 6 @C0 C1
,} ! ! H @ ! ! # # h
h
H H @ @ cpu0/un1_k_pp_regs_6_sqmuxa 6 ,F0 :B0 6B0 , | | : dž dž 6 : : 6 6 cpu0/N_280 HF0 X xA0 :C1 > ֓ > ta ta ֓ ֓ cpu0/next_state_1_m P ʓF0 xB0 xQA0 ʓ ɛ ɛ E E ju ju džu džu d džu :o :o dQ d x dQ xQ cpu0/dec_op/k_p2_valid7_2 v F0 A1 OA1 fQ fQ C C C O O O cpu0/dec_op/k_p2_valid7_6 yF0 B1 UB1 y y y U l+ l+ U U U U cpu0/dec_op/un1_cpu_reset_11_0 ,F1 B0 , Z Z cpu0/dec_op/un1_state_104_1_0 ; ,F0 C0 , cpu0/dec_op/un1_state_104_1_1 < ̺F0 A0 ̺ J J cpu0/dec_op/un1_state_104_1_2 F1 D0 r r ? ? Ǽܗ Ǽܗ cpu0/dec_op/un1_state_33 HF0 UA0 A1 H 4 4 H H z z 4 U U U cpu0/N_1904_i HF0 IDI0 H 4 I I 4 I cpu0/N_2100_1 D ~ ֱF0 u$A1 H gD0 {C0 ֱ *U *U Z Z ~} ~} l%ț l%ț u *U { *U ȿ ȿ g u u$ g g { { cpu0/dec_op/k_ealo_9_5_627_a4_0 w ufF0 u$D1 uf uk uk u u u$ cpu0/k_ealo_9_5_627 6 ufʟF1 u$DI1 ufʟ vɛ u u$ vɛ u cpu0/dec_op/N_1578 F1 C0 6o 6o cpu0/mode79 H fF1 u @[C1 fC0 f gV gV f gV `P `P l| l| ,[ ,[ @[ f f cpu0/dec_op/mode_8_sqmuxa_1_93_2 f F0 fD0 f g, g, ` o ` o ]gs ]gs f f f cpu0/un1_postbyte0_22 K > F0 > xB1 fB0 $ 6$A1 H H z
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, pD pD f H * * x H } } z 4 z 4 6$ x x f f 6$ 6$ cpu0/dec_op/mode_4_i_0[0] 7 ufF1 7 u$CC0 uf v v uC uC u$C cpu0/N_863 a ,F1 B0 8 \B1 ׃A1 @ B1 C0 D1 xD0 xC0 , o o o
H o , , ׃ o 6 6 , _ _ OQ OQ d OQ d o ܗ ܗ ܗ ]յ ]յ } } , H \ ׃ ׃ , @ d x d x cpu0/dec_op/N_5 ,F0 B0 , o o cpu0/dec_op/N_21_mux ,F1 A0 , cpu0/dec_op/N_22_mux F0 8 \D0 o o H H \ cpu0/dec_op/N_17 8 IF0 8 \C1 I H H \ cpu0/N_1571_1 y dʟF1 9 "cD0 " B1 dʟ ɛ ɛ ~ ~ c ɛ Ӈ Ӈ c "c " cpu0/N_1588 ;F1 \wC0 D0 ; օ օ Hw օ Ze Ze ؉ ؉ Hw \w cpu0/k_dec_su_3 U ufF0 u$DI0 ` u$C0 uf uRf u u$ uRf u uRf ~x ~x eU eU ~ܻ ~ܻ u u u$ cpu0/dec_op/N_2108_tz = ufgF0 7 u$UB1 ufg uRL uRL o*P o*P uU uU u$U cpu0/dec_op/mode76 f *F1 XB0 f ZA0 C0 f * g8 g8 f 0 f 0 f Z g8 \A ` \A ` N N W g8 _ _ p p W X f Z f Z cpu0/mode77 L uf *F1 f lD0 $ 66D1 uf * u u j ` j ` f l u y] y] z & z & 66 f l f l 66 66 cpu0/mode80 I f F1 f fC0 f bC0 f f y f y f f f y ` ` f b f f f f f b f b cpu0/un1_state_40 ufF1 u$B0 C1 < fC1 uf uXZ uXZ uXZ u uXZ l=1 l=1 a a f u u$ f f cpu0/dec_op/N_235 *F1 : A0 * cpu0/dec_op/N_239 : F1 : D0 y y
P
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o o cpu0/N_960_2 F0 u$C0 C0 eD1 H H y]G y]G u y]G H e u u$ e e cpu0/N_1564_1 %F1 u$A0 Q @uC1 [B0 SA1 ! B1 A1 % } } |`8 [ } z}- z}- z}a z}a S p p u u |`8 z z * * ,u z}a p p s s u u u$ ,u @u [ [ S S cpu0/use_s_1 L uf 6NF0 @ B 5B0 @ B 54C1 A\ 6A0 A\ 6A1 B\ 6B0 B\ 6*B1 C\ 5A0 C\ 5A1 D\ 5B0 D\ 5.B1 E 6A0 E 6A1 F 6B0 F 6*B1 G 5A0 G 5A1 I B 'B0 I B (C1 J\ )pA0 J\ )A1 K\ (B0 K\ )B1 L\ (tA0 L\ (A1 M\ 'B0 M\ (B1 N )pA0 N )A1 O (B0 O )B1 P (tA0 P (A1
xD0
xD1 x@C0 u$ 6C1 @ Iz )C1 B IzuB0 ` : 5A1 h : )B1 f 6 D0 XցD0 Iz/D0 :D0 :!A0 :D0 :ցD0 :D0 Iz}D0 Iz (tA0 Iz (A1 : C2C0 : CJC1 : A0 : A1 : (D0 : (D1 ,^ 5A0 ,^ 5A1 IzCC0 IzaD1 0 X (D0 0 X (D1 1 Iz (D0 1 Iz ( D1 Y ,^ 5A0 Y ,^ 5(A1 Z BA0 Z BA1 \ Iz CC0 \ Iz CC1 f : 5A0 f : 5.B1 X C8D0 X CPD1 uf 6N u 5V . 54 B 54 . ( B ( u 5V o0 : o0 : bF ; bF ; W C8 u 5V F / F / ' . ' . ,J 5 F / / / @ @ B @ B @ H4 H4 A A . 5 A = 2( = 2( . 54 A ; ;9 3 9 3W 2" W 2"H 6 W 2"H 6 W 2"H 6 W 2"H 6* 9 3H 5 9 3H 5 9 3H 5 9 3H 5. ; 3 3 2" 2" 6 2" 6 2" 6 2" 6* 3 5 3 5 A O '` O '` = % = % . ' A n . n . & &
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PAD
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 clk40_i PIO PL22A NPADDI:PADDI IOBUF:::PULLMODE=DOWN,CLAMP=ON VREF:OFF PGMUX:INBUF INRDMUX:PGMUX
PADDI TRIMUX IOBUF
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PAD
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 ldata_io[7] PIO PL8B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID E NGID0 (ldata_io[6] PIO PL8A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID F NGID0 )ldata_io[5] PIO PL6B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID G NGID0 *ldata_io[4] PIO PL6A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID H NGID0 +ldata_io[3] PIO PL4B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID I NGID0 ,ldata_io[2] PIO PL4A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID J NGID0 -ldata_io[1] PIO PL3B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF
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d o o ɨt ɨt s s dO o + o / / dO xO + "+ " cpu0/N_1890_1 % ,F1 yC1
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PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID K NGID0 .ldata_io[0] PIO PL3A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD
DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID L NGID0 /lcen_o PIO PL17A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID D NGID0 0lwen_o PIO PL17B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID C NGID0 1loen_o PIO PL19A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID B NGID0 2laddr_o[5] PIO PL12B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID < NGID0 3laddr_o[4] PIO PL12A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID = NGID0 4laddr_o[3] PIO PL10B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID > NGID0 5laddr_o[2] PIO PL10A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID ? NGID0 6laddr_o[1] PIO PL9B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID @ NGID0 7laddr_o[0] PIO PL9A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID A NGID0 8blue_o PIO PR24A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD ! DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID ; NGID0 9green_o PIO PR23A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF " PAD # DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID : NGID0 :red_o PIO PR21A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF $ PAD % DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID 9 NGID0 ;vsync_o PIO PR23B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF & PAD ' DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID 8 NGID0 leds_o[7]_MGIOL IOLOGIC IOL_R2A GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG . TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[6] PIO PR2B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF / PAD 0 DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID 0 NGID0 ?leds_o[6]_MGIOL IOLOGIC IOL_R2B GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG 1 TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[5] PIO PR3A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF 2 PAD 3 DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID 1 NGID0 @leds_o[5]_MGIOL IOLOGIC IOL_R3A GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG 4 TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[4] PIO PR3B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF 5 PAD 6 DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID 2 NGID0 Aleds_o[4]_MGIOL IOLOGIC IOL_R3B GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG 7 TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[3] PIO PR5A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF 8 PAD 9 DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID 3 NGID0 Bleds_o[3]_MGIOL IOLOGIC IOL_R5A GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG : TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[2] PIO PR5B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF ; PAD < DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID 4 NGID0 Cleds_o[2]_MGIOL IOLOGIC IOL_R5B GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG = TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[1] PIO PR7A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF > PAD ? DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID 5 NGID0 Dleds_o[1]_MGIOL IOLOGIC IOL_R7A GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG @ TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX leds_o[0] PIO PR7B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:IOLDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF A PAD B DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID 6 NGID0 Eleds_o[0]_MGIOL IOLOGIC IOL_R7B GSR:DISABLED SRMODE:ASYNC OUTREG:::GSR=DISABLED,SRMODE=ASYNC IOLDO:IOLDO MODE:IREG_OREG CEOMUX:CEMUX LSROMUX:0 CLKOMUX:CLK OPOSMUX:OPOS CEMUX:CE GSR CEIMUX SRMODE OUTREG C TSREG FF IN IOLDO IOLTO MODE CEOMUX INDD CLKIMUX LSROMUX TSMUX LSRIMUX CLKOMUX OPOSMUX DELAY CEMUX LSRMUX TSDREG ODDR IDDR IP ONEGMUX state_o[5] PIO PL25B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF D PAD E DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID ) NGID0 Fstate_o[4] PIO PL25A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF F PAD G DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID * NGID0 Gstate_o[3] PIO PL24B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF H PAD I DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID + NGID0 Hstate_o[2] PIO PL24A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF J PAD K DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID , NGID0 Istate_o[1] PIO PL22B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF L PAD M DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID - NGID0 Jstate_o[0] PIO PL19B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF N PAD O DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID . NGID0 Kdata_io[7] PIO PT15A PADDI:PADDI TRIMUX:PADDT:::PADDT=#INV IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,CLAMP=ON DATAMUX:PADDO VREF:OFF PGMUX:INBUF ODMUX:TRIMUX INRDMUX:PGMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF P PAD Q DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID ! NGID0 Ldata_io[6] PIO PT11A PADDI:PADDI TRIMUX:PADDT:::PADDT=#INV IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,CLAMP=ON DATAMUX:PADDO VREF:OFF PGMUX:INBUF ODMUX:TRIMUX INRDMUX:PGMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF R PAD S DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID " NGID0 Mdata_io[5] PIO PT10A PADDI:PADDI TRIMUX:PADDT:::PADDT=#INV IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,CLAMP=ON DATAMUX:PADDO VREF:OFF PGMUX:INBUF ODMUX:TRIMUX INRDMUX:PGMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF T PAD U DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID # NGID0 Ndata_io[4] PIO PT9A PADDI:PADDI TRIMUX:PADDT:::PADDT=#INV IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,CLAMP=ON DATAMUX:PADDO VREF:OFF PGMUX:INBUF ODMUX:TRIMUX INRDMUX:PGMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF V PAD W DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID $ NGID0 Odata_io[3] PIO PT9B PADDI:PADDI TRIMUX:PADDT:::PADDT=#INV IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,CLAMP=ON DATAMUX:PADDO VREF:OFF PGMUX:INBUF ODMUX:TRIMUX INRDMUX:PGMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF X PAD Y DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID % NGID0 Pdata_io[2] PIO PT10B PADDI:PADDI TRIMUX:PADDT:::PADDT=#INV IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,CLAMP=ON DATAMUX:PADDO VREF:OFF PGMUX:INBUF ODMUX:TRIMUX INRDMUX:PGMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF Z PAD [ DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID & NGID0 Qdata_io[1] PIO PT11B PADDI:PADDI TRIMUX:PADDT:::PADDT=#INV IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,CLAMP=ON DATAMUX:PADDO VREF:OFF PGMUX:INBUF ODMUX:TRIMUX INRDMUX:PGMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF \ PAD ] DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID ' NGID0 Rcen_o PIO PB13B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF ^ PAD _ DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 Swen_o PIO PT35A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF ` PAD a DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 Toen_o PIO PB18B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF b PAD c DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 Uaddr_o[18] PIO PB37B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF d PAD e DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 Vaddr_o[17] PIO PT36D TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF f PAD g DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 Waddr_o[16] PIO PB38B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF h PAD i DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 Xaddr_o[15] PIO PT36C TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF j PAD k DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 Yaddr_o[14] PIO PB38A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF l PAD m DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 Zaddr_o[13] PIO PB31B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF n PAD o DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 [addr_o[12] PIO PB35B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF p PAD q DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 \addr_o[11] PIO PB26A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF r PAD s DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID
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NGID0 ]addr_o[10] PIO PB18A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF t PAD u DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 ^addr_o[9] PIO PB26B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF v PAD w DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 _addr_o[8] PIO PB31A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF x PAD y DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID
NGID0 `addr_o[7] PIO PB35A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF z PAD { DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 aaddr_o[6] PIO PB29B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF | PAD } DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 baddr_o[5] PIO PB29A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF ~ PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 caddr_o[4] PIO PB23B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 daddr_o[3] PIO PB23A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 eaddr_o[2] PIO PB16B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 faddr_o[1] PIO PB16A TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 gaddr_o[0] PIO PB12B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 hreset_o PIO PL15B TRIMUX:PADDT:::PADDT=0 IOBUF:::PULLMODE=DOWN,DRIVE=8,SLEWRATE=SLOW,HYSTERESIS=NA DATAMUX:PADDO VREF:OFF ODMUX:TRIMUX LVDSMUX:DATAMUX
PADDI TRIMUX IOBUF PAD DATAMUX VREF PGMUX ODMUX PGBUF INRDBUF LVDSBUF INRDMUX LVDSMUX #%PAD%PINID NGID0 itextctrl/chars/textmem4k_0_0_3 EBR EBR_R20C10 MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,GSR=DISABLED,INITVAL_00=0x00000000000000000000000000000109C4E088E41C84E09C441C8E409C4E088E41C84E09C441C8E4,INITVAL_01=0x00000000031000000000000000000000000000000000000000000000000208000000000000000000,INITVAL_02=0x00000000000000000000000000000000000000001800000000000000000000000000000000000000,INITVAL_03=0x00000000000000000002080000000000000000000000000000000000000000000000010000000000,INITVAL_04=0x18000000000000000000000000000000000000000000000003100000000000000000000000000000,INITVAL_05=0x00000000000000000000000000000100000000000000000000000000000000000000000000000000,INITVAL_06=0x000000000101C4E088E41C84E09C441C8E409C4E088E41C84E09C441C8E408000000000000000000,INITVAL_07=0x00000000000000000000000000000000000000020800000000000000000000000000000000000000,INITVAL_08=0x00000000000000000000180000000000000000000000000000000000000000000000031000000000,INITVAL_09=0x08000000000000000000000000000000000000000000000001000000000000000000000000000000,INITVAL_0A=0x00000000000000000000000000000310000000000000000000000000000000000000000000000002,INITVAL_0B=0x00000000010000000000000000000000000000000000000000000000000018000000000000000000,INITVAL_0C=0x1C84E09C441C8E409C4E088E41C84E09C441C8E40800000000000000000000000000000000000000,INITVAL_0D=0x000000000000000000020800000000000000000000000000000000000000000000000101C4E088E4,INITVAL_0E=0x18000000000000000000000000000000000000000000000003100000000000000000000000000000,WID=0b0000000011,MEM_INIT_FILE=textmem2k.mem,MEM_LPC_FILE=textmem4k.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB3=0,DIB4=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/yptr[0] #%DP8KC%SIGNAME:ADA10 textctrl/yptr[9] #%DP8KC%SIGNAME:ADA11 textctrl/yptr[10] #%DP8KC%SIGNAME:ADA12 textctrl/yptr[11] #%DP8KC%SIGNAME:ADA2 textctrl/yptr[1] #%DP8KC%SIGNAME:ADA3 textctrl/yptr[2] #%DP8KC%SIGNAME:ADA4 textctrl/yptr[3] #%DP8KC%SIGNAME:ADA5 textctrl/yptr[4] #%DP8KC%SIGNAME:ADA6 textctrl/yptr[5] #%DP8KC%SIGNAME:ADA7 textctrl/yptr[6] #%DP8KC%SIGNAME:ADA8 textctrl/yptr[7] #%DP8KC%SIGNAME:ADA9 textctrl/yptr[8] #%DP8KC%SIGNAME:ADB1 addr_o_c[0] #%DP8KC%SIGNAME:ADB10 addr_o_c[9] #%DP8KC%SIGNAME:ADB11 addr_o_c[10] #%DP8KC%SIGNAME:ADB12 addr_o_c[11] #%DP8KC%SIGNAME:ADB2 addr_o_c[1] #%DP8KC%SIGNAME:ADB3 addr_o_c[2] #%DP8KC%SIGNAME:ADB4 addr_o_c[3] #%DP8KC%SIGNAME:ADB5 addr_o_c[4] #%DP8KC%SIGNAME:ADB6 addr_o_c[5] #%DP8KC%SIGNAME:ADB7 addr_o_c[6] #%DP8KC%SIGNAME:ADB8 addr_o_c[7] #%DP8KC%SIGNAME:ADB9 addr_o_c[8] #%DP8KC%SIGNAME:CEB textctrl/video_en_RNIFLVI #%DP8KC%SIGNAME:CLKA
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f OF0 u$ PLC0 f O f N f N j M j M u PL u PL u$ PL cpu0/un1_postbyte0_21_6 G f F1 > fC0 > ~C1 f g8 g8 f f S
> S
> ~ ~ f ~ ~ f f ~ ~ cpu0/dec_op/mode77_1
|
cpu_clkgen #%DP8KC%SIGNAME:CLKB
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XJ}F0 u$ D1 XJ} X X a a l l u
u
u u u$ cpu0/state128 C F0 @yC1 n n ;m ;m ,y ,y @y cpu0/dec_op/mode76_0
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cpu_clkgen #%DP8KC%SIGNAME:DIB2 cpu0_data_out[0] #%DP8KC%SIGNAME:DIB5 cpu0_data_out[1] #%DP8KC%SIGNAME:DOA0 textctrl/chars_bus[0] #%DP8KC%SIGNAME:DOA1 textctrl/chars_bus[1] #%DP8KC%SIGNAME:DOB0 textctrl/data_from_video[0] #%DP8KC%SIGNAME:DOB1 textctrl/data_from_video[1] #%DP8KC%SIGNAME:OCEB textctrl/video_en_RNIFLVI #%DP8KC%SIGNAME:WEB textctrl/un1_cpu0_we_1_0 NGID0 textctrl/chars/textmem4k_0_1_2 EBR EBR_R20C7 %MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,GSR=DISABLED,INITVAL_00=0x00000000000000000000000000000014A5001455000A50A00A0AA0014A5001455000A50A00A0AA00,INITVAL_02=0x00000000000000000000000000000000000000010000000000000000000000000000000000000000,INITVAL_03=0x00000000000000000001080000000000000000000000000000000000000000000000010800000000,INITVAL_04=0x08000000000000000000000000000000000000000000000001080000000000000000000000000000,INITVAL_05=0x00000000000000000000000000000210000000000000000000000000000000000000000000000002,INITVAL_06=0x000000000004A5001455000A50A00A0AA0014A5001455000A50A00A0AA0010000000000000000000,INITVAL_08=0x00000000000000000001000000000000000000000000000000000000000000000000000000000000,INITVAL_09=0x08000000000000000000000000000000000000000000000001080000000000000000000000000000,INITVAL_0A=0x00000000000000000000000000000108000000000000000000000000000000000000000000000001,INITVAL_0B=0x00000000021000000000000000000000000000000000000000000000000208000000000000000000,INITVAL_0C=0x000A50A00A0AA0014A5001455000A50A00A0AA001000000000000000000000000000000000000000,INITVAL_0D=0x000000000000000000000000000000000000000000000000000000000000000000000004A5001455,INITVAL_0F=0x00000000000000000000000000000008000000000000000000000000000000000000000000000001,WID=0b0000000100,MEM_INIT_FILE=textmem2k.mem,MEM_LPC_FILE=textmem4k.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB3=0,DIB4=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/yptr[0] #%DP8KC%SIGNAME:ADA10 textctrl/yptr[9] #%DP8KC%SIGNAME:ADA11 textctrl/yptr[10] #%DP8KC%SIGNAME:ADA12 textctrl/yptr[11] #%DP8KC%SIGNAME:ADA2 textctrl/yptr[1] #%DP8KC%SIGNAME:ADA3 textctrl/yptr[2] #%DP8KC%SIGNAME:ADA4 textctrl/yptr[3] #%DP8KC%SIGNAME:ADA5 textctrl/yptr[4] #%DP8KC%SIGNAME:ADA6 textctrl/yptr[5] #%DP8KC%SIGNAME:ADA7 textctrl/yptr[6] #%DP8KC%SIGNAME:ADA8 textctrl/yptr[7] #%DP8KC%SIGNAME:ADA9 textctrl/yptr[8] #%DP8KC%SIGNAME:ADB1 addr_o_c[0] #%DP8KC%SIGNAME:ADB10 addr_o_c[9] #%DP8KC%SIGNAME:ADB11 addr_o_c[10] #%DP8KC%SIGNAME:ADB12 addr_o_c[11] #%DP8KC%SIGNAME:ADB2 addr_o_c[1] #%DP8KC%SIGNAME:ADB3 addr_o_c[2] #%DP8KC%SIGNAME:ADB4 addr_o_c[3] #%DP8KC%SIGNAME:ADB5 addr_o_c[4] #%DP8KC%SIGNAME:ADB6 addr_o_c[5] #%DP8KC%SIGNAME:ADB7 addr_o_c[6] #%DP8KC%SIGNAME:ADB8 addr_o_c[7] #%DP8KC%SIGNAME:ADB9 addr_o_c[8] #%DP8KC%SIGNAME:CEB textctrl/video_en_RNIFLVI #%DP8KC%SIGNAME:CLKA
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XJF1 f rA1 XJ X X bX bX ]a f ]a f f r f r f r cpu0/N_278 ̺\F0 xD1 W C0 Y C0 D1 ̺\ , , @ @ d , g g \) \) , б б , ƴ/ ƴ/ d x cpu0/un1_state_40_0 ; dֱF0 "D1 dֱ U U ӱ ӱ " cpu0/k_ealo[1] 7 ufʥQ1 u$ A1 J :*D1 w u$cD0 ,^B0 ufʥ vɛ vɛ k k u k bjg bjg ) ) $ $ 6f 6f 1 1 :* vɛ t"~ t"~ uc $ #G #G ,J u u$ :* :* uc u$c ,J ,^ cpu0/dec_op/mode_4_0_1_1[2]
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cpu_clkgen #%DP8KC%SIGNAME:CLKB
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? ufcF0 ? u$A1 ufc u u s s u u u$ cpu0/k_new_pc28_1 ] oF1 A1 A1
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cpu_clkgen #%DP8KC%SIGNAME:DIB2 cpu0_data_out[2] #%DP8KC%SIGNAME:DIB5 cpu0_data_out[3] #%DP8KC%SIGNAME:DOA0 textctrl/chars_bus[2] #%DP8KC%SIGNAME:DOA1 textctrl/chars_bus[3] #%DP8KC%SIGNAME:DOB0 textctrl/data_from_video[2] #%DP8KC%SIGNAME:DOB1 textctrl/data_from_video[3] #%DP8KC%SIGNAME:OCEB textctrl/video_en_RNIFLVI #%DP8KC%SIGNAME:WEB textctrl/un1_cpu0_we_1_0 NGID0 textctrl/chars/textmem4k_0_2_1 EBR EBR_R13C7 ?MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,GSR=DISABLED,INITVAL_00=0x154AA154AA154AA154AA154AA154AB1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF,INITVAL_01=0x154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA,INITVAL_02=0x154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA,INITVAL_03=0x154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA,INITVAL_04=0x1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA,INITVAL_05=0x154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB,INITVAL_06=0x154AA154AB1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1D4AA154AA154AA154AA,INITVAL_07=0x154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA,INITVAL_08=0x154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA,INITVAL_09=0x1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA,INITVAL_0A=0x154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB,INITVAL_0B=0x154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA,INITVAL_0C=0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1D4AA154AA154AA154AA154AA154AA154AA154AA,INITVAL_0D=0x154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1FEFF1FEFF,INITVAL_0E=0x1D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB1D4AA154AA154AA154AA154AA154AA,INITVAL_0F=0x0000000000000000000000000000001D4AA154AA154AA154AA154AA154AA154AA154AA154AA154AB,WID=0b0000000101,MEM_INIT_FILE=textmem2k.mem,MEM_LPC_FILE=textmem4k.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB3=0,DIB4=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/yptr[0] #%DP8KC%SIGNAME:ADA10 textctrl/yptr[9] #%DP8KC%SIGNAME:ADA11 textctrl/yptr[10] #%DP8KC%SIGNAME:ADA12 textctrl/yptr[11] #%DP8KC%SIGNAME:ADA2 textctrl/yptr[1] #%DP8KC%SIGNAME:ADA3 textctrl/yptr[2] #%DP8KC%SIGNAME:ADA4 textctrl/yptr[3] #%DP8KC%SIGNAME:ADA5 textctrl/yptr[4] #%DP8KC%SIGNAME:ADA6 textctrl/yptr[5] #%DP8KC%SIGNAME:ADA7 textctrl/yptr[6] #%DP8KC%SIGNAME:ADA8 textctrl/yptr[7] #%DP8KC%SIGNAME:ADA9 textctrl/yptr[8] #%DP8KC%SIGNAME:ADB1 addr_o_c[0] #%DP8KC%SIGNAME:ADB10 addr_o_c[9] #%DP8KC%SIGNAME:ADB11 addr_o_c[10] #%DP8KC%SIGNAME:ADB12 addr_o_c[11] #%DP8KC%SIGNAME:ADB2 addr_o_c[1] #%DP8KC%SIGNAME:ADB3 addr_o_c[2] #%DP8KC%SIGNAME:ADB4 addr_o_c[3] #%DP8KC%SIGNAME:ADB5 addr_o_c[4] #%DP8KC%SIGNAME:ADB6 addr_o_c[5] #%DP8KC%SIGNAME:ADB7 addr_o_c[6] #%DP8KC%SIGNAME:ADB8 addr_o_c[7] #%DP8KC%SIGNAME:ADB9 addr_o_c[8] #%DP8KC%SIGNAME:CEB textctrl/video_en_RNIFLVI #%DP8KC%SIGNAME:CLKA
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o r r | | Q Q 6q 6q | " " 6W 6W cpu0/dec_op/next_state_10_1[1]
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cpu_clkgen #%DP8KC%SIGNAME:CLKB
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ʟF1 \sB1 ʟ ɛ ɛ K K Hs Hs \s cpu0/next_state_10[1] %F1 \ODI1 % HO \O HO cpu0/dec_op/next_mem_state_cnv_1[0]
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cpu_clkgen #%DP8KC%SIGNAME:DIB2 cpu0_data_out[4] #%DP8KC%SIGNAME:DIB5 cpu0_data_out[5] #%DP8KC%SIGNAME:DOA0 textctrl/chars_bus[4] #%DP8KC%SIGNAME:DOA1 textctrl/chars_bus[5] #%DP8KC%SIGNAME:DOB0 textctrl/data_from_video[4] #%DP8KC%SIGNAME:DOB1 textctrl/data_from_video[5] #%DP8KC%SIGNAME:OCEB textctrl/video_en_RNIFLVI #%DP8KC%SIGNAME:WEB textctrl/un1_cpu0_we_1_0 NGID0 textctrl/chars/textmem4k_0_3_0 EBR EBR_R13C10 _MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,GSR=DISABLED,WID=0b0000000001,MEM_INIT_FILE=textmem2k.mem,MEM_LPC_FILE=textmem4k.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB3=0,DIB4=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/yptr[0] #%DP8KC%SIGNAME:ADA10 textctrl/yptr[9] #%DP8KC%SIGNAME:ADA11 textctrl/yptr[10] #%DP8KC%SIGNAME:ADA12 textctrl/yptr[11] #%DP8KC%SIGNAME:ADA2 textctrl/yptr[1] #%DP8KC%SIGNAME:ADA3 textctrl/yptr[2] #%DP8KC%SIGNAME:ADA4 textctrl/yptr[3] #%DP8KC%SIGNAME:ADA5 textctrl/yptr[4] #%DP8KC%SIGNAME:ADA6 textctrl/yptr[5] #%DP8KC%SIGNAME:ADA7 textctrl/yptr[6] #%DP8KC%SIGNAME:ADA8 textctrl/yptr[7] #%DP8KC%SIGNAME:ADA9 textctrl/yptr[8] #%DP8KC%SIGNAME:ADB1 addr_o_c[0] #%DP8KC%SIGNAME:ADB10 addr_o_c[9] #%DP8KC%SIGNAME:ADB11 addr_o_c[10] #%DP8KC%SIGNAME:ADB12 addr_o_c[11] #%DP8KC%SIGNAME:ADB2 addr_o_c[1] #%DP8KC%SIGNAME:ADB3 addr_o_c[2] #%DP8KC%SIGNAME:ADB4 addr_o_c[3] #%DP8KC%SIGNAME:ADB5 addr_o_c[4] #%DP8KC%SIGNAME:ADB6 addr_o_c[5] #%DP8KC%SIGNAME:ADB7 addr_o_c[6] #%DP8KC%SIGNAME:ADB8 addr_o_c[7] #%DP8KC%SIGNAME:ADB9 addr_o_c[8] #%DP8KC%SIGNAME:CEB textctrl/video_en_RNIFLVI #%DP8KC%SIGNAME:CLKA
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! @ HʓF0 @ C1 Hʓ ɛ ɛ cpu0/k_pp_regs60_RNIHUUP8 @ HʟF1 CE CE Hʟ ɛ ɛ ɛ ~ ~ cpu0/N_862 g cF0 \C1 A0 c H @ @ H \ cpu0/dec_o_alu_size f BlF0 B ,^ 6B1 C@ BB1 D ,^ CJC1 E\ B1 F@aD1 d xC0 aD1 ,^ BB1 ,^ D1 D1 : ) D1 B OnD1 \ ]D1 B (C1 f+C1 :aD1 xC1 f BB1 ;Ҳ BD0 I Iz BBA1 C0 OnD1 BGC0 \ PB1 Ҳ ]D0 A fB0 ,^ D1 ] f Bl g, B g, B \A ? g, B _ M _ M 8 8 2
P 2
P :a g, B 8 = 8 = = Nx = Nx . On 8 = C 4V C 4V . ( _ M SL SL 6 6 ,J 6 ,J g, B ` G ` G _\ )a _\ )a 8"~ 8"~ a \A ? ) < 8 =X ;P X ;P< ;P < ;P N NҞ ] g, B f ?x f ?x f B \A ? E ; E ; If BB 8 = ;> ;> Nx Nx On _ M ] ] f ) ,J B ? N0W Y| W Y|H ] ) < #G 4 #G 4 ,J 6 ;> +J >S +J >S ,J CJ 8 H ] pVσ pVσ r r tϕ tϕ d ] f+ tϕ d \A ? EN ; EN ; 1 3 1 3 : ) < ;P DD DD, B ,a < ;Pz DD z DDҞ B 8"~ n n ,J 6 ,^ 6 , B@ B ,J CJ ,^ CJ H \ ,a@a d x aa ,J B ,^ B ,J ,^ : ) : ) . On B On H ]\ ] . ( B ( f+ f+ :a :a d x f B f B Ҟ BҲ B If BB Iz BB On On .G BG H P\ P Ҟ ]Ҳ ] f f ,J ,^ cpu0/N_1086 W ̺F1 W xC0 A0 Y A1 ZD1 ̺ 8 8 d 8 ր ր ր ր Z d x Z Z cpu0/un1_state59_16_i_1 F0 ^D1 cD0 y "C0 * * } } ^ * _ _ c _ 9 9 ~ ~ ^ ^ c c " cpu0/dec_regs/k_write_exg_1_sqmuxa_1
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cpu_clkgen #%DP8KC%SIGNAME:CLKB
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) 5^F1 5D0 5^ p 4 p 4 2R 2R 5 5 5 cpu0/dec_regs/k_write_tfr_1_sqmuxa_1
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cpu_clkgen #%DP8KC%SIGNAME:DIB2 cpu0_data_out[6] #%DP8KC%SIGNAME:DIB5 cpu0_data_out[7] #%DP8KC%SIGNAME:DOA0 textctrl/chars_bus[6] #%DP8KC%SIGNAME:DOA1 textctrl/chars_bus[7] #%DP8KC%SIGNAME:DOB0 textctrl/data_from_video[6] #%DP8KC%SIGNAME:DOB1 textctrl/data_from_video[7] #%DP8KC%SIGNAME:OCEB textctrl/video_en_RNIFLVI #%DP8KC%SIGNAME:WEB textctrl/un1_cpu0_we_1_0 NGID0 textctrl/font/fontrom_0_0_3 EBR EBR_R13C16
MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,CSDECODE_B=0b111,GSR=DISABLED,INITVAL_00=0x0000000000000021F000000031E00000000100000000215000000BF1FEE0000950AA600000000000,INITVAL_01=0x0000C19800000BF1FEF000000006F0000080548000000014A01FEF50BEFF0000A140001FEFF1FEFF,INITVAL_02=0x0008200400000AA000000008014020000FF1FEF0000A2154A00000200400000AA154A80000004000,INITVAL_03=0x00000014000002800000000021C00000008000000000010000000001000000008000000000000400,INITVAL_04=0x00000000000008004000000A0014000002A10480000080100000000000A800000000000000000000,INITVAL_05=0x00000014000000000000000001000000000000000000010000000081900000000000000000000000,INITVAL_06=0x00000014A00002A100000002A1002000080100000002A11480000A00048000080000000002F1FE80,INITVAL_07=0x0000000480000001000000002010000008000080000000000000000000000000A154800002A11480,INITVAL_08=0x000AA1048000000004A0000A8004A00000A1540000028004800002A11480000AA150000000215400,INITVAL_09=0x0002A15480000AA154A0000FF1FEF0000A800000000A8004A000000000200000000000000AA154A0,INITVAL_0A=0x000AF1FEF00000B1FEF00002A154A000000002F00002A00480000AA014800102A154800000001480,INITVAL_0B=0x018000000000000000800000000000000A8000000000000000000F4004F000000016F0000F8004F0,INITVAL_0C=0x000000100000000000000002014000000800000000020040000002A1000000080000000000000000,INITVAL_0D=0x0002A14000000AA14000000FF1F0000000000000000A001000014AA150A00000000000000AA14000,INITVAL_0E=0x000BF1F8000000B1F800000800000000020000000002004000000001400004000010000002A14000,INITVAL_0F=0x0002A100000000000020000000400000000000000008000020000A001000004AA15000000E005800,INITVAL_10=0x00082010000008000000000800000000080000000008000000000201400000080000000040A00480,INITVAL_11=0x000AA14000000AA14008000000000000000000800000000020000201400000020140200002014000,INITVAL_12=0x000800000000080000000002A140000002A140200002A140000008004020000C21F000000A001400,INITVAL_13=0x0000004038000EA1D0A000003060B000020000000000B006800002A154880002A15408004AA15020,INITVAL_14=0x00000000000000004400000AA15482000AA1402000080000000002A1400000000000000008000000,INITVAL_15=0x000001000000008010000000000000014AA00480018B8004800002A1400000000040000002800000,INITVAL_16=0x154AA10000154AA154AA0000000000000000000000000000001BADD1BADD13299132990221102211,INITVAL_17=0x0000000000000000000000000154AA00000154AA154AA15000154AA154AA154AA154AA0000000000,INITVAL_18=0x154AA1D4AA0000019800000001800000000180000000018000000001800000000180000000018000,INITVAL_19=0x0000019800154AA19CAA0000019800154AA19CAA154AA198000000019CAA154AA198000000019CAA,INITVAL_1A=0x154AA1D4AA154AA1800000000198000000019800000001D4AA154AA180000000019800000001D4AA,INITVAL_1B=0x0000007EFF1FEFF1FEFF00000000001FEFF180001FEFF1FEFF000001800000000000000000019800,INITVAL_1C=0x000000040000002154000000001000000A000480000000040000000004A00002A000000008001000,INITVAL_1D=0x000AA1540000000000000000B1F4C00000B1F0000002A1402000080054000000A150000008214080,INITVAL_1E=0x00002010000000010000000000000000000006E000080000000008004000000C0040000002010400,INITVAL_1F=0x0000000000000000000000000000000000000000000000000C000000000000000000000000000000,WID=0b0000000110,MEM_INIT_FILE=font256x16l.mem,MEM_LPC_FILE=fontrom.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=1,OCEB=1,CLKB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/line_cnt[0] #%DP8KC%SIGNAME:ADA10 textctrl/chars_data[5] #%DP8KC%SIGNAME:ADA11 textctrl/chars_data[6] #%DP8KC%SIGNAME:ADA12 textctrl/chars_data[7] #%DP8KC%SIGNAME:ADA2 textctrl/line_cnt[1] #%DP8KC%SIGNAME:ADA3 textctrl/line_cnt[2] #%DP8KC%SIGNAME:ADA4 textctrl/line_cnt[3] #%DP8KC%SIGNAME:ADA5 textctrl/chars_data[0] #%DP8KC%SIGNAME:ADA6 textctrl/chars_data[1] #%DP8KC%SIGNAME:ADA7 textctrl/chars_data[2] #%DP8KC%SIGNAME:ADA8 textctrl/chars_data[3] #%DP8KC%SIGNAME:ADA9 textctrl/chars_data[4] #%DP8KC%SIGNAME:CLKA
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- 5F1 6C0 5 5& 5& 6 6 6 cpu0/state133_0 F0 A1 %B1 Ho Ho Ho % % % cpu0/dec_regs/un1_postbyte0_21_0
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cpu_clkgen #%DP8KC%SIGNAME:DOA0 textctrl/font_bus[0] #%DP8KC%SIGNAME:DOA1 textctrl/font_bus[1] NGID0 textctrl/font/fontrom_0_1_2 EBR EBR_R13C21
MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,CSDECODE_B=0b111,GSR=DISABLED,INITVAL_00=0x0000B1C000000EB1FE80000E90BE800000B1F0000002F1FE00000FD07CF0000C2182300000000000,INITVAL_01=0x000AB0F48000054006300000000630000AE1AA70000BF1C4F01FECB1C6FF00034038001FEF403EFF,INITVAL_02=0x000EF156E0000FF000000067B0BC1C000AA154B0000510AA500002F156E00001F1FED00000017000,INITVAL_03=0x0000A1FE000003F1D000000051A8000000C0000000000180000000B1F000000BE154A0000AA156E0,INITVAL_04=0x00000000000007F1B6E00005016800014D50E07A000FF1FEC00000000254000A215EE00000000000,INITVAL_05=0x0000016800000A0000000000018000000A8000000000A1D000000071E8000002F1FE80000E0000B0,INITVAL_06=0x0000016A70000D50E020000D50E030000FF1FEF0000D50EA70000D005A70000EA154A0000D014070,INITVAL_07=0x000A215A700000B0F0000000301800000780164000028014000002801400000B50EA70000D50EA70,INITVAL_08=0x00095180700000015070000D015070000B50AAE0000D000070000D50EA70000551AE80000CF1EAC0,INITVAL_09=0x000D50AA70000551FA500000005E40000D0000000005715A50000BF1FEF0000EA154B0000550EA50,INITVAL_0A=0x0005E10000000B400000000D50AA50000EA154B0000D51C270000551EA7001EF50AA700000006A70,INITVAL_0B=0x01800000000000000078000FF1FEF00001F10000000C000030000C005A30000EA168000000715A00,INITVAL_0C=0x05EFF1E80000000002E0000D01B8000007F1FEF0000D003800000D50F0000007F1F0000000000020,INITVAL_0D=0x000D50B800000550B800000AA16800000EA154A00005E1680006A550B850000EA150A0000550B800,INITVAL_0E=0x0007A00000000B4000000007F1F800000D001800000DE03800000000B80007EFF1E800000D50B800,INITVAL_0F=0x000350F00000000000D00002A17480000AA114A0000EA114B0000D01780005AD50A8000001E1A000,INITVAL_10=0x0067D00E000007F1F0B80007F1F0800007F1F0300007F1F0E0000D01B82C0007F1F83001AF400070,INITVAL_11=0x000570BC2E000570BC04000EA15080000EA15078000EA15010000D01B880000D01B810000D01B8E0,INITVAL_12=0x0007F1F8800007F1F8E0000D50B880000D50B810000D50B8E0000FF1FEF00007B15800000D018E02,INITVAL_13=0x004AA174AC000151A65C000AB17640000D000078000AC000E8000D50AA44000D50AAC405AD50A810,INITVAL_14=0x00000064F800000066FC000571EA4D000550B8D00007F1F808000D50B808000EA1502C0007F1F008,INITVAL_15=0x0000B0F0000000716800000BF150A000ADD05A0001E6C05A00000150E0000000006000000D400000,INITVAL_16=0x0AA55180000AA550AA55154AA154AA154AA154AA154AA154AA0EE770EE7713299132990884408844,INITVAL_17=0x154AA1000000000154AA000001AA55000001AA550AA550B8000AA550AA550AA550AA55154AA15000,INITVAL_18=0x0AA550AA55154AA1DCAA154AA1D4AA0000018000154AA1D4AA154AA18000000001D4AA000001D4AA,INITVAL_19=0x0000019CAA0AA5508A5500000198000AA5508A550AA55098000000018A550AA55098000000018A55,INITVAL_1A=0x0AA551AA550AA5518000154AA1D800000001DCAA000001AA550AA5518000154AA19800000001AA55,INITVAL_1B=0x0000007EFF1FEFF1FEFF00000000001FEFF180001FEFF1FEFF154AA1800000000154AA154AA1DCAA,INITVAL_1C=0x000AA15A000000D0AA000002A15800000D0102C0000FF1FE000000000270000D51DEE00007A16800,INITVAL_1D=0x000550AAC0000C0060300000C15A000000E15800000D50FC30000FF1AAE0000B51AE80000ED0BCC0,INITVAL_1E=0x0000D0680000028194000002A154AA154AA154B0000CE004C0000C21BC00000C2174000003018600,INITVAL_1F=0x00000000000003F1FE0000000050200000007EF8000FF1FEFC0000200000000021000000000004F8,WID=0b0000000111,MEM_INIT_FILE=font256x16l.mem,MEM_LPC_FILE=fontrom.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=1,OCEB=1,CLKB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/line_cnt[0] #%DP8KC%SIGNAME:ADA10 textctrl/chars_data[5] #%DP8KC%SIGNAME:ADA11 textctrl/chars_data[6] #%DP8KC%SIGNAME:ADA12 textctrl/chars_data[7] #%DP8KC%SIGNAME:ADA2 textctrl/line_cnt[1] #%DP8KC%SIGNAME:ADA3 textctrl/line_cnt[2] #%DP8KC%SIGNAME:ADA4 textctrl/line_cnt[3] #%DP8KC%SIGNAME:ADA5 textctrl/chars_data[0] #%DP8KC%SIGNAME:ADA6 textctrl/chars_data[1] #%DP8KC%SIGNAME:ADA7 textctrl/chars_data[2] #%DP8KC%SIGNAME:ADA8 textctrl/chars_data[3] #%DP8KC%SIGNAME:ADA9 textctrl/chars_data[4] #%DP8KC%SIGNAME:CLKA
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0 F1 > rA1 r r } } z} z} r r r cpu0/un1_state_14_1 IF0 R C1 I f f I I ܵ ܵ cpu0/dec_regs/state_cnst_i_a2_0_0[0]
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cpu_clkgen #%DP8KC%SIGNAME:DOA0 textctrl/font_bus[2] #%DP8KC%SIGNAME:DOA1 textctrl/font_bus[3] NGID0 textctrl/font/fontrom_0_2_1 EBR EBR_R20C21
MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,CSDECODE_B=0b111,GSR=DISABLED,INITVAL_00=0x000071A000000D71FE40000D615E400001F1FA000007F1FC00000FE07AF0000C1184300000000000,INITVAL_01=0x0005716A40000AA156B0000BF1FEF00005D1D4B0000C007A101FEC71A6FF00038058001FEF805EFF,INITVAL_02=0x000DF0AED0000FF000000060E0168C000550EA70000A2154A00001F0AED0000011FA000000B1FE80,INITVAL_03=0x0001F1FE000003F1FA000000A1D0000000C000000000E1D80000004188000007D0AA50000550AED0,INITVAL_04=0x00000004FC000C00FCB00000B0800000AC006035000AE15C8000000004A8000510BED00000000000,INITVAL_05=0x0000B08000000500000000000180000065400000000051A8000000B1F000000D0000700001F1FE40,INITVAL_06=0x000FF08030000C0060B0000C0060300004019640000C006030000C21A030000D50AED0000E00A0B0,INITVAL_07=0x000510A030000B400E8000003018000000716800000D400A000001400A00000C006030000C006030,INITVAL_08=0x000E0080B0000EA174B0000EA174B0000EA154B0000E0000B0000EA174B000000184D0000C50A0C0,INITVAL_09=0x000C0000300000003E800000003E80000EA154B0000AA1F4A0000C000010000D50AA700000006000,INITVAL_0A=0x000AD080000007800000000C000000000D50AA70000C007030000AA174B0000D400030000EA174B0,INITVAL_0B=0x0180000000000000002D000C000030000011F000000FF1FEF0000C21A030000D50F0000000B0BC00,INITVAL_0C=0x060C001800000EA174B0000C019800000C005810000C001800000EA15CA0000C019800000000001F,INITVAL_0D=0x000C001800000AA14800000550F000000D50AA70000AB1D4A00740000000000D50B850000AA174A0,INITVAL_0E=0x000B5000000007800000000C0000000007F1FED0000C311800000EA16800020C001800074EA14800,INITVAL_0F=0x0003005A000000000070000D508A700005508A50000150EA40000CB09800060C0000000002D1C000,INITVAL_10=0x0060E15600000C0198EC000C019878000C019800000C0198B4000C0198D0000C00000001838000B0,INITVAL_11=0x000030163B0000301640000D50B878000D50B8B4000D50B820000C019878000C019800000C0198B4,INITVAL_12=0x000C000078000C00003C000C001878000C001800000C0018B400000060B0000D70F000000EA1D62D,INITVAL_13=0x01A550EA50000EA156AC000570EE80000EA15CAC0005C000D4000C000000000C0000C0060C000000,INITVAL_14=0x00000066AC00000066AC000000FC07000AA14870000C0000B4000C0018B4000D50B8D0000C0198B4,INITVAL_15=0x000061C8000000E0D8000007F0A850000D21A000008121A00000000060000000006000000C0178F0,INITVAL_16=0x1FEFF180001FEFF1FEFF0AA551BA550AA551AA550AA550AA551BADD1BADD13299132990221102211,INITVAL_17=0x0AA5518000000001BA55000001FEFF0000019EFF1FEFF198001FEFF1FEFF1FEFF19EFF0AA551B800,INITVAL_18=0x1FEFF1FEFF0AA550AA550AA551AA5500000180000AA550AA550AA5518000000001AA55000000AA55,INITVAL_19=0x0000019A551FEFF19EFF00000198001FEFF1FEFF1FEFF198000000019EFF1FEFF1F800000001FEFF,INITVAL_1A=0x1FEFF1FEFF1FEFF180000AA550A800000000AA55000001FEFF1FEFF180000AA5519800000001FEFF,INITVAL_1B=0x0000007EFF00000000001FEFF1FEFF1FEFF180001FEFF1FEFF0AA5508000000001AA550AA551BA55,INITVAL_1C=0x000550AE00000AE15400000D50B800000CB0F0C0000AA1560000000000300000002030000D50B800,INITVAL_1D=0x00000000C00007A174D00002F0B8000000D0B800000EA162D0000AA100B0000E0184C0000DE15AC0,INITVAL_1E=0x00007038000001418A00000D50AA550AA550AA40000C11DA00000CD002C0000C10EA000003018600,INITVAL_1F=0x00000000000003F1FE0000000064DC00000054A40007A100000000100000000010800000000006AC,WID=0b0000001000,MEM_INIT_FILE=font256x16l.mem,MEM_LPC_FILE=fontrom.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=1,OCEB=1,CLKB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/line_cnt[0] #%DP8KC%SIGNAME:ADA10 textctrl/chars_data[5] #%DP8KC%SIGNAME:ADA11 textctrl/chars_data[6] #%DP8KC%SIGNAME:ADA12 textctrl/chars_data[7] #%DP8KC%SIGNAME:ADA2 textctrl/line_cnt[1] #%DP8KC%SIGNAME:ADA3 textctrl/line_cnt[2] #%DP8KC%SIGNAME:ADA4 textctrl/line_cnt[3] #%DP8KC%SIGNAME:ADA5 textctrl/chars_data[0] #%DP8KC%SIGNAME:ADA6 textctrl/chars_data[1] #%DP8KC%SIGNAME:ADA7 textctrl/chars_data[2] #%DP8KC%SIGNAME:ADA8 textctrl/chars_data[3] #%DP8KC%SIGNAME:ADA9 textctrl/chars_data[4] #%DP8KC%SIGNAME:CLKA
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4 F0 UB1 f f U U U cpu0/dec_regs/un1_postbyte0_6_1
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cpu_clkgen #%DP8KC%SIGNAME:DOA0 textctrl/font_bus[4] #%DP8KC%SIGNAME:DOA1 textctrl/font_bus[5] NGID0 textctrl/font/fontrom_0_3_0 EBR EBR_R20C16
MODE:DP8KC DP8KC:::DATA_WIDTH_A=2,DATA_WIDTH_B=2,RESETMODE=ASYNC,CSDECODE_B=0b111,GSR=DISABLED,INITVAL_00=0x0000000000000011E800000031E000000011A000000071FA000007F1FED00006A154900000000000,INITVAL_01=0x0000C19800006F50AA50000F4000000000402A400007F1A0001FEFA15EFF000050A0001FEFF1FEFF,INITVAL_02=0x0004100200000FF00000002C11E8740000003ED0000510AA5000001002000000006000000BF1FEF8,INITVAL_03=0x000000BE000003D08000000011A0000000F1E000000011A000000001800000004000000000000200,INITVAL_04=0x00000002000007F1A240000B401E000007803ED00005D0BA40000000005400000000000000000000,INITVAL_05=0x000B4000000000000000000001800000000000000000008000000041880000000000000000000000,INITVAL_06=0x00000000F00007F1FE400007007EF0000001E80000070000D0000FD000D000040002000001F1FE40,INITVAL_07=0x00000006D0000400004000001008000000008000000000000000000000000004003ED00007F1BED0,INITVAL_08=0x0001F1FE40000D50AA70000D50AA70000D50AA700001F1FE40000D50AA70000FF1FA000007F1FE40,INITVAL_09=0x0007F1FED0000FF1FEF0000FF1FEF0000D50AA70000D50AA700007F000000000000000000FF1FEF0,INITVAL_0A=0x0005F1FEF0000071FEF00007F1FEF000000004F00007C00ED0000D50AA700007F1FED0000D50AA70,INITVAL_0B=0x018000000000000000D000000000000000003E800000000000000FD004F00000000EF0000F4002F0,INITVAL_0C=0x0387F1E800000D50EA400007F1E8000007F1A0000007F1E800000550AA700007F088000000000000,INITVAL_0D=0x0007F1E800000550B800000FF1F8000000000000000D50AA7000A00000000000000000000D50AA70,INITVAL_0E=0x0007F1F800000071F8000007F1F8000000001800000700E800000D50B8000007F1E80006A550B800,INITVAL_0F=0x0003F1A00000000000D0000400001000000000000000002000000F4078000607F1F800000D003800,INITVAL_10=0x000010A8000007F088100007F088040007F088300007F088400007F1E8000007F1F830008071FE40,INITVAL_11=0x000FF1E804000FF1E80C0000000004000000004000000000100007F1E8040007F1E8300007F1E840,INITVAL_12=0x0007F1F8040007F1F8D00007F1E8040007F1E8300007F1E840000FF1FE400007D00800000D50AE10,INITVAL_13=0x00E0002000000D50AA5C0000306070000F50BA50000071FE400007F1FECC0007F1FE4C0207F1F830,INITVAL_14=0x00000020500000002050000FF1FECD000550B8D00007F1F8400007F1E84000000000000007F08840,INITVAL_15=0x0000D03800000011A00000000000000002D01EFC0002D01EFC00000060000003F1E0000007F08000,INITVAL_16=0x000001800000000180000000019800000001800000000000000EE770EE7713299132990884408844,INITVAL_17=0x00000180000000019800000001800000000198000000019800000000000000000198000000019800,INITVAL_18=0x00000000000000000000000001800000000180000000000000000001800000000180000000000000,INITVAL_19=0x00000198000000019800000001980000000000000000019800000001980000000000000000000000,INITVAL_1A=0x00000180000000000000000000000000000000000000000000000001800000000198000000018000,INITVAL_1B=0x0000007EFF00000000001FEFF1FEFF1FEFF180001FEFF1FEFF000000000000000180000000019800,INITVAL_1C=0x0000001A00006550AA000007F1E800000F400EC0000550AE00000FF1FEF0000FF1FED00007F1E800,INITVAL_1D=0x000FF1FE40000050AA00000D71E800000071E8000001508000000D50FE400001F1FA00000410A040,INITVAL_1E=0x0000D0680000000080000007F00000000000000000040020000004000000000C0020000003018600,INITVAL_1F=0x0000000000000150AA000000007A340000002A5C0000518000000000000000000000000000000050,WID=0b0000001001,MEM_INIT_FILE=font256x16l.mem,MEM_LPC_FILE=fontrom.lpc:CEA=1,OCEA=1,WEA=0,CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=1,OCEB=1,CLKB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA0=0,DIA1=0,DIA2=0,DIA3=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA1 textctrl/line_cnt[0] #%DP8KC%SIGNAME:ADA10 textctrl/chars_data[5] #%DP8KC%SIGNAME:ADA11 textctrl/chars_data[6] #%DP8KC%SIGNAME:ADA12 textctrl/chars_data[7] #%DP8KC%SIGNAME:ADA2 textctrl/line_cnt[1] #%DP8KC%SIGNAME:ADA3 textctrl/line_cnt[2] #%DP8KC%SIGNAME:ADA4 textctrl/line_cnt[3] #%DP8KC%SIGNAME:ADA5 textctrl/chars_data[0] #%DP8KC%SIGNAME:ADA6 textctrl/chars_data[1] #%DP8KC%SIGNAME:ADA7 textctrl/chars_data[2] #%DP8KC%SIGNAME:ADA8 textctrl/chars_data[3] #%DP8KC%SIGNAME:ADA9 textctrl/chars_data[4] #%DP8KC%SIGNAME:CLKA
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6 F1 @ C0 , , @ cpu0/dec_regs/un1_postbyte0_16_5
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cpu_clkgen #%DP8KC%SIGNAME:DOA0 textctrl/font_bus[6] #%DP8KC%SIGNAME:DOA1 textctrl/font_bus[7] NGID0 bios/bios2k_0_1_0 EBR EBR_R13C13 dMODE:DP8KC DP8KC:::DATA_WIDTH_A=4,DATA_WIDTH_B=4,RESETMODE=ASYNC,GSR=DISABLED,INITVAL_00=0x0000000000000000000000000000000000000000000000000E05C2811E2509E2118A8A1140418CE8,INITVAL_1F=0x01E00000000000000000000000000000000000000000000000000000000000000000000000000000,WID=0b0000001010,MEM_INIT_FILE=test1.mem,MEM_LPC_FILE=bios2k.lpc:CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=0,OCEB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,ADA1=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA10 addr_o_c[8] #%DP8KC%SIGNAME:ADA11 addr_o_c[9] #%DP8KC%SIGNAME:ADA12 addr_o_c[10] #%DP8KC%SIGNAME:ADA2 addr_o_c[0] #%DP8KC%SIGNAME:ADA3 addr_o_c[1] #%DP8KC%SIGNAME:ADA4 addr_o_c[2] #%DP8KC%SIGNAME:ADA5 addr_o_c[3] #%DP8KC%SIGNAME:ADA6 addr_o_c[4] #%DP8KC%SIGNAME:ADA7 addr_o_c[5] #%DP8KC%SIGNAME:ADA8 addr_o_c[6] #%DP8KC%SIGNAME:ADA9 addr_o_c[7] #%DP8KC%SIGNAME:CEA
un1_bios_en_0 #%DP8KC%SIGNAME:CLKA
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: f &F1 X D1 Iz nA1 f & gt " gt " S S W S H< H< If n W X If n Iz n cpu0/dec_regs/un1_postbyte0_3_4
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cpu_clkgen #%DP8KC%SIGNAME:CLKB
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= XJF1 X A0 Iz VA0 XJ X X N N R R W N E E If V W X If V Iz V cpu0/dec_regs/N_1064
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cpu_clkgen #%DP8KC%SIGNAME:DIA0 cpu0_data_out[4] #%DP8KC%SIGNAME:DIA1 cpu0_data_out[5] #%DP8KC%SIGNAME:DIA2 cpu0_data_out[6] #%DP8KC%SIGNAME:DIA3 cpu0_data_out[7] #%DP8KC%SIGNAME:DOA0 data_from_bios[4] #%DP8KC%SIGNAME:DOA1 data_from_bios[5] #%DP8KC%SIGNAME:DOA2 data_from_bios[6] #%DP8KC%SIGNAME:DOA3 data_from_bios[7] #%DP8KC%SIGNAME:OCEA
un1_bios_en_0 #%DP8KC%SIGNAME:WEA
un1_cpu0_we_0 NGID0 bios/bios2k_0_0_1 EBR EBR_R20C13 MODE:DP8KC DP8KC:::DATA_WIDTH_A=4,DATA_WIDTH_B=4,RESETMODE=ASYNC,GSR=DISABLED,INITVAL_00=0x0000000000000000000000000000000000000000000000000A01E6003A6C18E60038560AE011880E,WID=0b0000001011,MEM_INIT_FILE=test1.mem,MEM_LPC_FILE=bios2k.lpc:CSA0=0,CSA1=0,CSA2=0,RSTA=0,CEB=0,OCEB=0,WEB=0,CSB0=0,CSB1=0,CSB2=0,RSTB=0,DIA4=0,DIA5=0,DIA6=0,DIA7=0,DIA8=0,ADA0=0,ADA1=0,DIB0=0,DIB1=0,DIB2=0,DIB3=0,DIB4=0,DIB5=0,DIB6=0,DIB7=0,DIB8=0,ADB0=0,ADB1=0,ADB2=0,ADB3=0,ADB4=0,ADB5=0,ADB6=0,ADB7=0,ADB8=0,ADB9=0,ADB10=0,ADB11=0,ADB12=0 MODE SP8KC PDPW8KC DP8KC FIFO8KB #%DP8KC%PINNAME:0 DOA0 #%DP8KC%PINNAME:1 DOA1 #%DP8KC%PINNAME:10 DOB1 #%DP8KC%PINNAME:11 DOB2 #%DP8KC%PINNAME:12 DOB3 #%DP8KC%PINNAME:13 DOB4 #%DP8KC%PINNAME:14 DOB5 #%DP8KC%PINNAME:15 DOB6 #%DP8KC%PINNAME:16 DOB7 #%DP8KC%PINNAME:17 DOB8 #%DP8KC%PINNAME:18 DIA0 #%DP8KC%PINNAME:19 DIA1 #%DP8KC%PINNAME:2 DOA2 #%DP8KC%PINNAME:20 DIA2 #%DP8KC%PINNAME:21 DIA3 #%DP8KC%PINNAME:22 DIA4 #%DP8KC%PINNAME:23 DIA5 #%DP8KC%PINNAME:24 DIA6 #%DP8KC%PINNAME:25 DIA7 #%DP8KC%PINNAME:26 DIA8 #%DP8KC%PINNAME:27 DIB0 #%DP8KC%PINNAME:28 DIB1 #%DP8KC%PINNAME:29 DIB2 #%DP8KC%PINNAME:3 DOA3 #%DP8KC%PINNAME:30 DIB3 #%DP8KC%PINNAME:31 DIB4 #%DP8KC%PINNAME:32 DIB5 #%DP8KC%PINNAME:33 DIB6 #%DP8KC%PINNAME:34 DIB7 #%DP8KC%PINNAME:35 DIB8 #%DP8KC%PINNAME:36 ADA0 #%DP8KC%PINNAME:37 ADA1 #%DP8KC%PINNAME:38 ADA2 #%DP8KC%PINNAME:39 ADA3 #%DP8KC%PINNAME:4 DOA4 #%DP8KC%PINNAME:40 ADA4 #%DP8KC%PINNAME:41 ADA5 #%DP8KC%PINNAME:42 ADA6 #%DP8KC%PINNAME:43 ADA7 #%DP8KC%PINNAME:44 ADA8 #%DP8KC%PINNAME:45 ADA9 #%DP8KC%PINNAME:46 ADA10 #%DP8KC%PINNAME:47 ADA11 #%DP8KC%PINNAME:48 ADA12 #%DP8KC%PINNAME:49 ADB0 #%DP8KC%PINNAME:5 DOA5 #%DP8KC%PINNAME:50 ADB1 #%DP8KC%PINNAME:51 ADB2 #%DP8KC%PINNAME:52 ADB3 #%DP8KC%PINNAME:53 ADB4 #%DP8KC%PINNAME:54 ADB5 #%DP8KC%PINNAME:55 ADB6 #%DP8KC%PINNAME:56 ADB7 #%DP8KC%PINNAME:57 ADB8 #%DP8KC%PINNAME:58 ADB9 #%DP8KC%PINNAME:59 ADB10 #%DP8KC%PINNAME:6 DOA6 #%DP8KC%PINNAME:60 ADB11 #%DP8KC%PINNAME:61 ADB12 #%DP8KC%PINNAME:62 WEA #%DP8KC%PINNAME:63 WEB #%DP8KC%PINNAME:64 RSTA #%DP8KC%PINNAME:65 RSTB #%DP8KC%PINNAME:66 CSA0 #%DP8KC%PINNAME:67 CSA1 #%DP8KC%PINNAME:68 CSA2 #%DP8KC%PINNAME:69 CSB0 #%DP8KC%PINNAME:7 DOA7 #%DP8KC%PINNAME:70 CSB1 #%DP8KC%PINNAME:71 CSB2 #%DP8KC%PINNAME:72 CLKA #%DP8KC%PINNAME:73 CLKB #%DP8KC%PINNAME:74 CEA #%DP8KC%PINNAME:75 CEB #%DP8KC%PINNAME:76 OCEA #%DP8KC%PINNAME:77 OCEB #%DP8KC%PINNAME:8 DOA8 #%DP8KC%PINNAME:9 DOB0 #%DP8KC%PINTYPE:0 OUT #%DP8KC%PINTYPE:1 OUT #%DP8KC%PINTYPE:10 OUT #%DP8KC%PINTYPE:11 OUT #%DP8KC%PINTYPE:12 OUT #%DP8KC%PINTYPE:13 OUT #%DP8KC%PINTYPE:14 OUT #%DP8KC%PINTYPE:15 OUT #%DP8KC%PINTYPE:16 OUT #%DP8KC%PINTYPE:17 OUT #%DP8KC%PINTYPE:18 IN #%DP8KC%PINTYPE:19 IN #%DP8KC%PINTYPE:2 OUT #%DP8KC%PINTYPE:20 IN #%DP8KC%PINTYPE:21 IN #%DP8KC%PINTYPE:22 IN #%DP8KC%PINTYPE:23 IN #%DP8KC%PINTYPE:24 IN #%DP8KC%PINTYPE:25 IN #%DP8KC%PINTYPE:26 IN #%DP8KC%PINTYPE:27 IN #%DP8KC%PINTYPE:28 IN #%DP8KC%PINTYPE:29 IN #%DP8KC%PINTYPE:3 OUT #%DP8KC%PINTYPE:30 IN #%DP8KC%PINTYPE:31 IN #%DP8KC%PINTYPE:32 IN #%DP8KC%PINTYPE:33 IN #%DP8KC%PINTYPE:34 IN #%DP8KC%PINTYPE:35 IN #%DP8KC%PINTYPE:36 IN #%DP8KC%PINTYPE:37 IN #%DP8KC%PINTYPE:38 IN #%DP8KC%PINTYPE:39 IN #%DP8KC%PINTYPE:4 OUT #%DP8KC%PINTYPE:40 IN #%DP8KC%PINTYPE:41 IN #%DP8KC%PINTYPE:42 IN #%DP8KC%PINTYPE:43 IN #%DP8KC%PINTYPE:44 IN #%DP8KC%PINTYPE:45 IN #%DP8KC%PINTYPE:46 IN #%DP8KC%PINTYPE:47 IN #%DP8KC%PINTYPE:48 IN #%DP8KC%PINTYPE:49 IN #%DP8KC%PINTYPE:5 OUT #%DP8KC%PINTYPE:50 IN #%DP8KC%PINTYPE:51 IN #%DP8KC%PINTYPE:52 IN #%DP8KC%PINTYPE:53 IN #%DP8KC%PINTYPE:54 IN #%DP8KC%PINTYPE:55 IN #%DP8KC%PINTYPE:56 IN #%DP8KC%PINTYPE:57 IN #%DP8KC%PINTYPE:58 IN #%DP8KC%PINTYPE:59 IN #%DP8KC%PINTYPE:6 OUT #%DP8KC%PINTYPE:60 IN #%DP8KC%PINTYPE:61 IN #%DP8KC%PINTYPE:62 IN #%DP8KC%PINTYPE:63 IN #%DP8KC%PINTYPE:64 IN #%DP8KC%PINTYPE:65 IN #%DP8KC%PINTYPE:66 IN #%DP8KC%PINTYPE:67 IN #%DP8KC%PINTYPE:68 IN #%DP8KC%PINTYPE:69 IN #%DP8KC%PINTYPE:7 OUT #%DP8KC%PINTYPE:70 IN #%DP8KC%PINTYPE:71 IN #%DP8KC%PINTYPE:72 IN #%DP8KC%PINTYPE:73 IN #%DP8KC%PINTYPE:74 IN #%DP8KC%PINTYPE:75 IN #%DP8KC%PINTYPE:76 IN #%DP8KC%PINTYPE:77 IN #%DP8KC%PINTYPE:8 OUT #%DP8KC%PINTYPE:9 OUT #%DP8KC%SIGNAME:ADA10 addr_o_c[8] #%DP8KC%SIGNAME:ADA11 addr_o_c[9] #%DP8KC%SIGNAME:ADA12 addr_o_c[10] #%DP8KC%SIGNAME:ADA2 addr_o_c[0] #%DP8KC%SIGNAME:ADA3 addr_o_c[1] #%DP8KC%SIGNAME:ADA4 addr_o_c[2] #%DP8KC%SIGNAME:ADA5 addr_o_c[3] #%DP8KC%SIGNAME:ADA6 addr_o_c[4] #%DP8KC%SIGNAME:ADA7 addr_o_c[5] #%DP8KC%SIGNAME:ADA8 addr_o_c[6] #%DP8KC%SIGNAME:ADA9 addr_o_c[7] #%DP8KC%SIGNAME:CEA
un1_bios_en_0 #%DP8KC%SIGNAME:CLKA
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? dɗF0 "B1 "B0 dɗ ; ; ƣ ƣ ; / / G G " " cpu0/dec_regs/N_350
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cpu_clkgen #%DP8KC%SIGNAME:CLKB
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A 'F1 (B1 ' ' ' %z %z ( ( ( cpu0/N_995_2 t YF1 x B0 @D1
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cpu_clkgen #%DP8KC%SIGNAME:DIA0 cpu0_data_out[0] #%DP8KC%SIGNAME:DIA1 cpu0_data_out[1] #%DP8KC%SIGNAME:DIA2 cpu0_data_out[2] #%DP8KC%SIGNAME:DIA3 cpu0_data_out[3] #%DP8KC%SIGNAME:DOA0 data_from_bios[0] #%DP8KC%SIGNAME:DOA1 data_from_bios[1] #%DP8KC%SIGNAME:DOA2 data_from_bios[2] #%DP8KC%SIGNAME:DOA3 data_from_bios[3] #%DP8KC%SIGNAME:OCEA
un1_bios_en_0 #%DP8KC%SIGNAME:WEA
un1_cpu0_we_0 NGID0
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Y t& t& yI yI Fܵ Fܵ bܵ bܵ j߲ j߲ d t& ; ; , d x , @ cpu0/dec_regs/un1_k_opcode_3_4
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GSR_INST GSR GSR "GSRMODE:ACTIVE_HIGH SYNCMODE:ASYNC GSRMODE SYNCMODE NGID0 cpu0_data_out[0] L ufmQ0 PADDO C Y:OPOS |EDIB2 _DIA0 ufm uUF @ \p C Y: |E
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{^VCLK {^CLK {^ZCLK OCLK OVCLK OCLK OZCLK A&CLK A&@CLK 2CLK 2 ,^ (2CLK @ u$ 4CLK A f 6HCLK B f 5CLK C f 5LCLK D f 4CLK E X 6HCLK F X 5CLK G X 5LCLK I CLK J u$sCLK K u$CLK L u$wCLK M u$CLK N fsCLK O fCLK P fwCLK Q fCLK | CLK } CLK ~ CLK CLK CLK x CLK x CLK x CLK x (2CLK x 'CLK ).CLK (CLK (2CLK @pCLK @CLK @
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B 5F1 @ OnD1 5 5& 5& L : L : M M ; LV ; LV , On , On @ On cpu0/dec_regs/N_401
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@ʍCLK {^wCLK {^CLK
z]CLK {CLK z{CLK wCLK CLK CLK {^CLK aCLK {^ʍCLK $ʍCLK ҲCLK \CLK Ҳ-CLK @CLK ɑCLK ʍCLK zCLK GCLK -CLK CLK ! ʍCLK " ,^sCLK # ,^ɑCLK $ :ɑCLK % B-CLK & ,^֫CLK ' Iz-CLK ( BwCLK ) ,^GCLK * ɑCLK + XCLK , X@CLK -ɑCLK . @tCLK /CLK 0 ,^CLK 1 @pCLK 2 (2CLK 3 f ).CLK 4$CLK 5\CLK 6\קCLK 7 IzʍCLK 8 5CLK 9֫CLK :z&CLK ; :{CLK < ,^@CLK = :z&CLK > ,^{CLK ? ,^zCLK @ :{"CLK A ,^
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C OF0 O\A1 \B0 u$ PD0 ! @ CD0
O N N y] L y] L u P N O\ N } T } T \ N M M e A e A , C O\ O\ \ \ u P u$ P , C @ C cpu0/dec_regs/un1_state_24_4
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{ CLKA
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B%CLKA $%CLKA z CLKA CLKB z%CLKA %CLKB d{J {J{^ d{F {F{^V d{J {J{^ d{JZ {JZ{^Z dO OO dO OOV dO OO dOZ OZOZ *txA AA& *txA@ A@A&@ *tx2 22 *tx2 22< *tx2 22 *tx2@ 2@2@ dhD{Jn {Jn{^n dhD{Fm {Fm{^n dhD{Jm {Jm{^m dhD{Jm {Jm {^m du^{Jz {Jz{^z du^{Jz& {Jz&{^z& du^l{ l{l{ du^lz lzl{" du^lz lzlz du^lz& lz&lz& O Ifa Ifa Iza O : : : O : : :] O : : : O :a :a :a ,J ,J ,^ ,F ,F ,^] ,J ,J ,^ O " If ' If ' Iz ' O " : ). : ). : ). O " : (< : (< : ( O " : (2 : (2 : (2 O " : ' : ' : ' " ,J ). ,J ). ,^ ). " ,F (< ,F (< ,^ ( " ,J (2 ,J (2 ,^ (2 0 u 4 u 4 u$ 4 O 0 f 6H f 6H f 6H O 0 f~ 5V f~ 5V f 5 O 0 f 5L f 5L f 5L O 0 f 4 f 4 f 4 O 0 W 6H W 6H X 6H O 0 W 5V W 5V X 5 O 0 W 5L W 5L X 5L 1 1 us us u$s 1 u u u$ 1 uw uw u$w 1 u u u$ O1 fs fs fs O1 f~ f~ f O1 fw fw fw O1 f f f T T " " T T T d d x T ` " ` " x T d d x T " d (2 d (2 x (2 T " d ' d ' x ' T " ). ). ). T " (< (< ( T " (2 (2 (2 ( (@p , ,@ x( (@< x < x ( (@V eH- H-\- TK Hʍ Hʍ \ʍ OK W W X C Ox W W X< T = Bp Bp B O f f f u u u$ O W{ W{ X{ , , @ e u- u- u$- e ֫ ֫ ֫ e ק ק ק ( ( @V C , , @ K e ,ק ,ק @ק e ֵ ֵ ) G G G ( ( @C e ,֫ ,֫ @֫ e (ֵ (ֵ @) e ,- ,- @- K ,ʍ ,ʍ @ʍ , , @ e - - - O 0 Ib 5V Ib 5V Iz 5 " . ). . ). B ). " . (2 . (2 B (2 " . ' . ' B ' O " f ' f ' f ' " u ). u ). u$ ). "Ҟ ). Ҟ ).Ҳ ). $ Ҟ{ Ҟ{Ҳ{ $ 0 4 4 4 0 6H 6H 6H " (< (< ( eק קק w e,- ,-@- eֵ ֵ) O = : A : A : A dK{J {J{^ 1Ҟs ҞsҲs ,Z ,Z@Z V $ xҞ@ Ҟ@Ҳ@ x~ ~< x, ,@ $ ,t ,t@t KҚɛ ҚɛҲ K 1f fz ~ ~C a aa xҞ ҞҲ Kɑ ɑ$ɑ e,֫ ,֫@֫ K,ʍ ,ʍ@ʍ d{F {F{^w d{J {J{^ b bz] { {{ f{ f{z{ w d{J {J{^ a aa dK{Jʍ {Jʍ{^ʍ Kʍ ʍ$ʍ Ҟ ҞҲ H H\ eҞ- Ҟ-Ҳ- , ,@ Kɑ ɑɑ Kʍ ʍʍ f fz G GG e- -- K ʍ ʍ ʍ 1 ,Js ,Js ,^s K ,Jɑ ,Jɑ ,^ɑ OK :ɑ :ɑ :ɑ e .- .- B- e ,J֫ ,J֫ ,^֫ Oe If- If- Iz- * * Bw ,JG ,JG ,^G K ɑ ɑ ɑ O W W X Ox W@ W@ X@ Kɑ ɑɑ ,t ,t @t Kɛ ɛ x ,J ,J ,^ ( ( @p " (2 (2 (2 O " f ). f ). f ). $ KDɛ Dɛ\ eHק Hק\ק OK Ifʍ Ifʍ Izʍ 0 5V 5V 5 e֫ ֫֫ u^z& z&z& Ou^ :{ :{ :{ x ,J@ ,J@ ,^@ Ou^ :z& :z& :z& u^ ,J{ ,J{ ,^{ u^ ,Jz ,Jz ,^z Ou^ :z :z :{" x ,F ,F ,^< O W W X u u u$w O : : : O f f f O W " W " X O If If Iz ,J ,J ,^ O " W (2 W (2 X (2 1 ,F ,F ,^ * " * " B ua ua u$a O f f f u{ u{ u${ u u u$ O f~ f~ fw O f f f u u u$ u u u$ ft ftzt 1Қ ҚҲ u^,z ,z@z u^,{ ,{@{ d1^.s ^.s^Bs d1^* ^*^B d1^. ^.^B eֵ ֵ) eק קק Kf fz dxl ll ( (@w { {{ KHɑ Hɑ\ɑ dl llp dl ll x@ @@ xf fz x x < e(ֵ (ֵ@) e- -- d{J {J{^ Z ZZ dxl@ l@l@ KHʍ Hʍ\ʍ Oe Ifק Ifק Izק , , @ e - - - K ɛ ɛ K K .ɑ .ɑ Bɑ Oe If֫ If֫ Iz֫ . . B e *ֵ *ֵ B) O W W X O W W X O W W X u " u " u$ O Ib " Ib " Iz O 0 : 5L : 5L : 5L O 0 If 5L If 5L Iz 5L O : : : O W W Xw O 0 If 4 If 4 Iz 4 O " Ib (< Ib (< Iz ( O f f f O 0 If 6H If 6H Iz 6H 1 s s s 1 ,Jw ,Jw ,^w K ,J ,J ,^ K ,Jʍ ,Jʍ ,^ʍ K ,Fɛ ,Fɛ ,^ 1 w w w O W W X e .֫ .֫ B֫ K .ʍ .ʍ Bʍ K *ɛ *ɛ B .{ .{ B{ Oe Ibֵ Ibֵ Iz) ,J ,J ,^ O1 W W X O : : :C O f f f O W W X e ,Jק ,Jק ,^ק O : : : O If If Iz O Wa Wa Xa e ,Fֵ ,Fֵ ,^) O WG WG XG w ,F " ,F " ,^ O Ib Ib Iz] ,J ,J ,^ Oe :- :- :- Oe W- W- X- Oe :֫ :֫ :֫ OK :ɛ :ɛ : O : : :w O If If Iz O f~ f~ f] OK :ʍ :ʍ :ʍ O If If Iz ,J ,J ,^ O1 :w :w :w O W W X] O :G :G :G Oe Wֵ Wֵ X) O : : : O IfG IfG IzG Oe :ֵ :ֵ :) O = : Bp : Bp : B eH֫ H֫\֫ e .ק .ק Bק O : : : Қ ҚҲ] C u u u$ u u u$ e u֫ u֫ u$֫ 1 ,J ,J ,^ O Ib Ib IzC 1s ss 1fs fszs O : " : " : ,J ,J ,^ ,F ,F ,^p O : : : O If{ If{ Iz{ O :{ :{ :{ 1| @ @ C@ 1|u @z @z Cw& 1| s @ @ C 1| s @ @ C 1| Y @ @ C 1| Y @ @ C 1| r% @ vP @ vP C uQ 1| r% @ v @ v C sP 1| W @ \ @ \ C [ 1| W @ \ @ \ C Y {% G G|*% d^+ ^+P&% d^+G ^+GP% d ^+
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X^Q0 X^ByLSR Y^BID0 Y^BaD1 Z^BMD0 q^BD1 ^_ ^.y^By _]@d ]@d^.y ]@d^.I ]@d^.a ]@d^.M ]@d^. ^.I^BI ^.a^Ba ^.M^BM ^.^B cpu_clk_mx VzF0 V@zDI0 zzN ,z@z zN,z textctrl.vsyncrc_i + *OF0 C^OPOS OP @ C^ Py1 y1[ [ *1 *1 [ [ 81 81 ! ! 7 7 <> <> @ textctrl.vsync_cnt[10] AhQ1 A&A1 ^lLSR nlFLSR vlD0 yO~A0 CFLSR AhAh ll lFlF @ CF AhA AhJ Jhf hfl hflF hfl JN NO~ J T T 9 9 T T
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3D0 M )C0
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K BxF1 5C0 E @ BTD1 Bx p B p B ;8 ;8 DD DD , BT p B 4V 4V 5 5 5 , BT @ BT cpu0/N_973_2 $ ?F1 . "D1 @uB0 @ GC0 } "qB0 ? t t љ љ 0Ϗ 0Ϗ ) ) t ,u 0Ϗ q t y/ y/ G " ,u @u G G q "q cpu0/dec_regs/state_cnst_i_0[5]
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e u of6 of6 b b T8 T8 P 7 P 7 P \ P \ 0z | 0z | (; | (; | 7 7 @ 7 89 89 8y O 8y O t t & w & w c c ~ w ~ w } } = = } O } O P P P c c textctrl/chars_bus[6]
|
uf &F1 @ BD0 BA0 uf & v " v " y] y] z 'N z 'N z @ z @ B z @ ; ; , B , B @ B B B cpu0/dec_regs/path_right_addr[0]
|
{ DOA0 _@M0 { {G
k ,@ {G
k ^ ^ l l 5 5, textctrl/chars_bus[7]
|
6HOFX0 6~DI0 6H ~ 5V 6~ 6~ ~ 5V 6~ cpu0/dec_o_right_path_addr[0] + 6TQ0 n@eD1 $D0 ҲD0 C0 $uB0 uB0 ʷM0 9M0 ,^M0 BmM0 WM0 M0 M0 M0 M0 \SM0 \M0 M0 \M0 \ M0 @WM0 @M0 $M0 @ɻM0 @=M0 M0 M0 @M0 @mM0 ҲqM0 ҲM0 Ҳ=M0 M0 ҲWM0 ҲSM0 SM0 M0 ҲM0 $וD1 ҲD1 D0 D1 6T 5V ʷ ʷ 9 9 ,J ,^ .m Bm W W HS\S H\ H\ H \ ,W@W ,@ $ ,ɻ@ɻ ,=@= ,@ ,m@m ҞqҲq ҞҲ Ҟ=Ҳ= ҞWҲW ҞSҲS SS ҞҲ 5V UD / UD / / /x - x -s sI Iו x -N N ,e x -x xɉ~ ɉ~Ҟ s IP_ P_ɉQ ɉQҞ ssI sI Iu sIu x -b b #;I #;I ? ? ʷ ? ~ ~ 9 ɉQқ қҞq ɉQқ қҞ b 8܋ 8܋ .m ? 7 7 n_ n_ #5Q #5Q ,J bQՑ QՑHS b9I 9IH QՑ
|
{ DOA1 _@M1 { {G
_ ,@ {G
_ YK YK) ), textctrl/data_from_video[6]
|
w
|
|E DOB0 eD0 |E {G
e {G
e ' ' textctrl/data_from_video[7]
|
w ؉ ؉ 9I
|
|E DOB1 fzAB0 |E {G
Y {G
Y K KfA fAzA textctrl/line_cnt[0]
|
_
|
dm|Q0 dlA0 dlD1 el:B0 l{^FD0 nlC1
ADA1 '
ADA1
'jADA1 jADA1 + m|m ) :
,G : '
,G 'j ) j ml mk kl mk kl: mq p q p{JF mb{: b{:U v U vhn hnk kl q p:e :e6 6ܺ ܺ ) : n n қ
қ
] L ] L ' ' ,G : :ee e #) #) &Y9 &Y9 ,G
|
_ ؉ ؉ W b #5k #5k bK K
|
dmQ1 dlA1 elFD0 l{^4A0 nlA1 ulDD1
ADA2 '
ADA2
'pADA2 pADA2 ( mm ) L
,G L '
,G 'p ) p ml mq v q v{J4 mc cl clD q vt6 t6. .9 9* * 8 8 ) L * J J ,G L . * * #YU #YU &Y? &Y? ,G U U5 58J 8J) x xY, Y,k klF ll lFlF {J4{^4 ll lDlD textctrl/line_cnt[2] emQ0 el4A0 elRB1 nlD1 ul>C1
ADA3 '
ADA3
'vADA3 vADA3 " mml қ ^
^ '
'v қ v mll4 mll llR mlc cl cl> mle e Ѱ Ѱ қ ^ ^ mlg I g I c c
|
|
b;
|
K6 6 s 6 KE EH KE EH x -ܖܑ ܖܑ,m x -ɧՑ ɧՑҞS ɧՑܖw ܖw؉ ؉, ܖw؉ ؉,W x -y y, y I I;m ;m,ɻ I;g ;g,= x -܋ ɧՑ̭s ̭sҞ= ɧՑq qS sI ɧՑ̭Ӎ ̭ӍҞW qҘ Ҙ ܋Ց Ց Ց ܋ x -ɉk ɉkҞ ɉk ,e@e $ ҞҲ u$u uu ו$ו ҞҲ cpu0/dec_regs/path_right_addr[1]
|
b;; ;b b қ l4l4 lRlR ll l>l> textctrl/line_cnt[3] em
|
F0 DI0 f f cpu0/dec_o_right_path_addr[1] Q0 ҲD0 $GC0 $C0 $ID0 $C0 #B0 ҲD0 D0 ,^A0 C0 )C0 \A0 /D0 \-C0 @B0 @C0 -C0 @D0 ҲD0 ҲaC0 Ҳ{C0 qB0 ҲC0 D1 ҲC1 $B1 [A0 T ` ` | | U&ф U&фZ Z * *, Zh} h} Zɭ ɭ}a }aҞ ɭh h# Z Ҟ U&ф ϡ ϡ U&ф #e #e ,J ϡ * *) ϡq qH ϡ ) ) / ZW WH- Zrσ rσ, - Z*ϛ *ϛS S, ɭҞ Ҟa qϡ ϡҞ{ h}q ɭҞ | z z Zɳț ɳțҞ h h G 79 79 79I 9 9 ҞҲ G$G $ I$I $ ## ҞҲ ,J ,^ )) H\ / / H-\- ,@ ,@ -- ,@ ҞҲ ҞaҲa Ҟ{Ҳ{ qq ҞҲ ҞҲ $ cpu0/dec_regs/path_right_addr[2]
|
Q1 elLA1 nlB1 ul2A1
ADA4 '
ADA4
'|ADA4 |ADA4 ! m
|
F1 DI1 Z Z cpu0/dec_o_right_path_addr[2] Q1 ҲA0 $MD0 $D0 $CC0 $D0 /D0 ҲC0 $C0 ${C0 uC1 BB1 ևA1 C1 D1 \C1 \A1 @֓C1 $!B1 @D1 D1 @A1 Ҳ5A1 A1 ҲוD1 A1 ҲD1 $׃A1 [D0 [-D1 C1 ` T T z1 z1 z z p { p { 8
|
mx @
: @ '
: '| | mxlL mxc cl ll ll2 mxf f
|
j 8
|
|
j|o |o? T y]A y]A FT FT
|
@ 5 5 9 9 : @ ( ( 9J 9J : ; ; lLlL ll l2l2 textctrl/chars_data[0] iQ0
#ADA5 '
#ADA5
'ADA5 ADA5 R :
# : : '
# : ' R% %> >
h>
h>
|
T
|
|
T
= =׃
|
:
|
T, ,Ҟ ?ɉ7 ɉ7Ҟ
={ 8
|
6 6 : :
h> 2 2 : >0
0
2 2 textctrl/chars_data[1] iQ1
)ADA6 '
)ADA6
'ADA6 ADA6 ^ )
) ,G '
) ,G5 ' )5 ^ V q V q ) V q ,G 9 q 9 q 3 3 1 1 (2 (2 ,G5 (2
|
j u 8
|
/
|
j I I . FT
|
// /; ;)5 textctrl/chars_data[2] hQ0
/ADA7 '
/ADA7
'ADA7 ADA7 n )
/ ,G '
/ ,G ' ) n , , ) ,
n
n ( ( +V +V ,G n 2A 2ANA NA; ;) NA n n + ; + ; ,G textctrl/chars_data[3] hQ1
5ADA8 '
5ADA8
'ADA8 ADA8 z )
5 ,G '
5 ,G/ ' )/ z r r , , ) r 5 5 ,G Bj Bj @{g @{g 60/ 60/ +; +; ,G/ zr r) ) )/ textctrl/chars_data[4] gQ0
;ADA9 '
;ADA9
'ADA9 ADA9 n қ
; '
; ' қ n ɉ ɉ қ
|
|
қ
|
H
!
|
қ ɉ j j n n nrl rl J J rl > >n; n;қ textctrl/chars_data[5] g
Q1
AADA10 '
AADA10
'ADA10 ADA10
z қ
A '
A ' қ z z z h h қ z " "
|
TY Yj j
|
C
|
T "e "e tS tSҞו "e
,܅ ,܅ɛm ɛmҞ Yjg jg- ={ { jgG GX XM X X C X j/ m m և
|
C C C " ɧC ɧCқ textctrl/chars_data[6] _Q0
GADA11 '
GADA11
'ADA11 ADA11 ) R
G ,G R '
G ,G ' ) F F ) R F
|
E EH ?, jg
|
|
,܅,
, ,Ҟ5 =͜ϛ ͜ϛ,֓ ҞҲ M$M $ C$C $ // ҞҲ $ {${ u u . B և և H\ H\ ,֓@֓ !$! ,@ ,@ Ҟ5Ҳ5 ҞוҲו ҞҲ ׃$׃ -- cpu0/dec_regs/path_right_addr[3]
|
'$ '$ + + ,G R *r *r %u %u # # ,G yw ywj j ; ;) textctrl/chars_data[7] _Q1
MADA12 '
MADA12
'ADA12 ADA12 ) F
M ,G F '
M ,G ' )
n
n ( ( ,G (
|
4OFX0 5DI0 4 4 5 5 4 5 cpu0/dec_o_right_path_addr[3] - 4Q0 ҲB0 $AB0 $B0 $=B0 $B0 ҲA0 $A0 A1 ]C0 ,^-D1 BB0 ցD0 C1 B0 B0 ;B1 \qB0 \A1 ;B1 \D0 \EC1 @ցD0 @C1 $C0 @C1 @aC0 ?B1 B0 @!B1 @C0 ҲC1 Ҳ A0 ҲyC1 D0 Ҳ֓C1 ҲqB0 C1 D0 Ҳ1D1 A1 ҲB1 $C1 [ B0 ['C1 4 4 4 | E | E U&ޞ U&ޞzޞ zޞɹ ɹҞ zޞ , zޞNܩ Nܩ,! ɹD D D? zޞ! ! ,a , zޞܻ ܻ ܻ' !Ҟy ɹҞ ɹD DA D D= D ܻ ߲ ߲ U&ޞ ܣ ܣ Nܩjܩ jܩ ny ny ,J- ܣ . ց ܣ I I I| | |; zޞi iHq iH ; zޞc cH cHE NܩM M,ց M, !Ҟ֓ zޞɿ ɿҞq | E z z !Ҟ ܻ߲ ߲ 4 } - } - |x( |x( U>0 U>00 0ɡ ɡҞ1 0_ _Q Qbs ܻ! !ϧ ϧ bsѪ߲ Ѫ߲Ҟ a a ] ! !{ { { ܣpt ptܵ ܵҞ ҞҲ A$A $ =$= $ ҞҲ $ ] ] ,J- ,^- . B ց ց ;; Hq\q H\ ; ; H\ HE\E ,ց@ց ,@ $ ,@ ,a@a ?? ,!@! ,@ ҞҲ Ҟ Ҳ ҞyҲy Ҟ֓Ҳ֓ ҞqҲq Ҟ1Ҳ1 ҞҲ $ '' cpu0/dec_regs/path_left_addr_1[0]
|
|
OFX0 DI0 | | cpu0/dec_o_left_path_addr[0] Q0 2 :eD1 IzuC1 y ` y ` c s c s 1 1 :e o o rZ rZ @ie @ie Ifu :e :e Ifu Izu cpu0/dec_regs/path_left_addr_1[1]
|
t t) # # ) F # H H
|
OFX0 @ NDI0 z m , N @ N z m , N cpu0/dec_o_left_path_addr[1] $Q0 2 :_C1 :C1
|
|
$ | o | o c c 1' 1' :_ 1' 1 1 1/ 1/ : :_ :_ : : cpu0/dec_regs/path_left_addr_1[2]
|
' ' +\ +\ ,G F textctrl/font_bus[0] DOA0 `M0 қ
k қ
k o o textctrl/font_bus[1] DOA1 `M1 қ
_ қ
_ N N textctrl/font_bus[2] ' DOA0 a M0 '
k
k G G an an ]o ]o o o z z textctrl/font_bus[3] ' DOA1 a %M1 '
_ % %
_ o o G G ~x ~x z
t z
t } } % textctrl/font_bus[4]
'(DOA0 b M0 '( " " V: V: z} z} zգ zգ } } textctrl/font_bus[5]
'.DOA1 b M1 '. G G n& n& ~u ~u z z textctrl/font_bus[6] (DOA0 c\ɻM0 (қ Hɻ\ɻ қ 5 5E Eb bWȉ WȉWa WaHɻ textctrl/font_bus[7] .DOA1 c\M1 .қ H\ қ̸ ̸pe pe{ {Eƣ EƣH textctrl/tshift[0] j5Q0 fD0 5օ օy) y)` ` ` ` textctrl/hsync_cnt[2] "mzQ1 "l{B1 fB0 l{^D0 mlB0 B0 mzmxzN mxzNdh< dhQ1 #lzB1 fA0 l{^ A0 ml~A0 A0 mz>my myfw fwlz myf fv v v{J fl~ v lzlz {J {^ l~l~ textctrl/shift_7[0] f.FF0 fvDI0 .F+ vv +v reset_cnt_1[3] Z^F0 Z^B/DI0 ^^p ^./^B/ ^p^./ textctrl/video_en hfYF1 gD0 sB1 zAB0 zYB1 C0 C1 D0 D1 h$B0 i${C0 eB0 eB1 fzMD0 fzeD1 g7A0 gOA1 hA0 hA1 izA0 izA1 8 fYX& X& g s ss LI LIfA LIfY Lܗ Lܗ X& X&= ={ A AfM Afe C C 7 O LIV " >V "l. l.ϕ ϕ. k. kIi textctrl/N_44 j^NF1 dlB0 dlB1 el@C0 elXC1 nlB1 j^BD0 mlB1 nlD0 o^BD0 ^BD0 ^N_ _b{B b{Bc cl cl cl@ clX _b{< b{
|
'OFX0 @ 'DI0 ' k ' , ' @ ' k ' , ' cpu0/dec_o_left_path_addr[2] 'Q0 V :D1 2 :YB1
|
]
|
' q ' q ' c # c # 4@ 4@ 1ȿ 1ȿ : c # 2 2 2o 2o :Y : : :Y :Y cpu0/dec_o_left_path_addr[3] $Q0 V :gD0 2 :SA1 :D1
$ j j s s P P EN3 EN3 :g P EN EN 1a 1a :S EN3 : :g :g :S :S : : cpu0/dec_regs/dest_reg_3[1]
|
^. b{
|
\OFX0 @ \DI0 f BC0 \ z [ , \ @ \ z [ , \ z [ c WI c WI ] N ] N f B f B f B cpu0/dec_regs/dest_reg_3[2]
|
^. ]
|
BOFX0 @ CDI0 f BD0 B B@ , C @ C B@ , C B@ ? ? p ; p ; f B f B f B cpu0/dec_regs/dest_reg_3[3]
|
^. ll ll l@l@ lXlX ll ^.^B ll ll ^.^B ^.^B textctrl/N_30_i emF0 el(DI0 mmf l(l( mfl( textctrl/N_31 " gF1 UA0 t t2 2y' y'U UU cpu0_data_in[0]
F0 "C0 $ B0 IDI0
zA1 %\ʷM0 &$LA1 '$C1 ] ,^M0 a M0 \M0 ҲM0 ,^#M0 3 II Hʷ\ʷ ,J ,^ H\ ҞҲ ,J# ,^# I I I " @ @ f X X
|
BfOFX0 BDI0 f BA0 Bf A B B A B A y] ? y] ? b" ; b" ; f B f B f B cpu0/dec_regs/state_32_iv_2[1]
|
>{
|
ֱ̺F0 d xA1 ֱ̺ U U aӷ aӷ d d x cpu0/dec_regs/state_cnst_0_12[1]
|
>{$o $oHʷ L
|
,F1 d x
C1 , Q Q # # O O d
d
x
cpu0/dec_regs/state_cnst_0_13[1]
|
>{ [ [ M M G G X գ գ
|
̺oF1 d xD1 ̺o 8 8 ƴ6 ƴ6 Ñ Ñ d d x cpu0/dec_regs/un1_state_118
|
}
|
H?F1 d xB1 f xwC0 f xC1 uB0 D0 kA0 H? : : { { : u : ~ϛ ~ϛ Ҙ Ҙ k : бA бA d : б б dw б d d x dw xw d x u u k k cpu0/state_32[1] d ̺F1 d xDI1 ̺ Vֵ d x Vֵ d cpu0/dec_regs/state_32_iv_2[0]
|
}$؉ $؉H $ $ Ѫ ѪҞ M #q #q %`6 %`6 #k
, #k
, ,J# #q &YS &YS ,J "" $ fz L$L $ data_io_in[4] a c PADDI ~A0 A0 h=PADDO c d v hJ h= I ir hJ d vl l $ $ / /j 6 j 6j jj
j
~ j 6 ܩ ܩX X /i Ws i Ws WI WI VC VC[ h [ h[ f [ fI ir ~~ N_35 ( hyF0 C0 D0 yh h a a h2 2yyT yyT cpu0_data_in[4]
IF0 @D0 yDI0 KD1 X 9M0 &$XC1 '$B1 5 BɻM0 _ ,^ʷM0 ,^ M0 X#M0 $$C0 O ,^#M0 6 IJ yy 9 9 .ɻ Bɻ ,Jʷ ,^ʷ ,J ,^ W# X# ,J# ,^# Jy J6 6\ \ N NM M, 6 K X J TK TK I I .ɻ I [ [ 5[ 5[ S[ S[ VU VU W# [ + U + U ,J# \l l 11 11 &) &) K K 9 [ ȭ ȭ 'lu 'lu +&o +&o ,Jʷ 11 9 9 1 1 ( ( ,J ,@ KK X$X $ $ textctrl/visible_2_i_o3_2 & vmF0 j^BC0 mlA1 mm mb{ b{ ^. mk kl ^.^B ll textctrl/N_99 ' sAhF0 nlD1 j^BB0 mlD1
|
̺F0 d xB0 ̺ ,k ,k ~ ~ d d x cpu0/state_1_m ֽ̺F1 xC0 ֽ̺ U U d d x cpu0/dec_regs/state_cnst_m[0]
|
AhA AKRr KRrhnr hnrl KRr\ \^. hnrl ll ^.^B ll textctrl/N_97 ( ){{F0 nlA1 j^B~A0 mlC1
|
/F0 d xA0 / Hօ Hօ nq nq d d x cpu0/state_32[0] d ̺F0 d xDI0 ̺ Jֵ d x Jֵ d cpu0/dec_regs/state_32_0_iv_0_581_i_1
|
{{|0z |0zq w q wc cl cY Y^.~ cl ll ^.~^B~ ll textctrl/N_75_i ) j^BF0 fLCE gzCE hCE iHCE ^B^ LL fz HH ^S S y yv vL vf v vH textctrl/hsync_cnt[9] * {zQ0 {^zA0 ){^{A0 k{^D0 p{|A1 vlB1 w{^D0 C1 {z{zN {zN{Jz {zN{Gw {Gw{J{ {zNs s| |{| {zNud ud{J udg gl ud{J ud {Jz{^z {J{{^{ {J{^ {|{| ll {J{^ textctrl/N_52_6 + k{NF1 k{^C0 l{^*D1 vl&D1 {N| | {J | {J* | q q l& {J{^ {J*{^* l&l& textctrl/N_155_i - k{BF0 {^ B0 {^4B1
{^B0
{^B1 {^ B0 {^8B1 {^B0 {^B1 {B| |rM rM{J rM{J4 |B B v~ v~{J v~{J v~{J v~{J8 v~{J v~{J {J {^ {J4{^4 {J{^ {J{^ {J {^ {J8{^8 {J{^ {J{^ textctrl/y_cnt_s[0] . OlF1 ODI1 OlO9 OO O9O textctrl/y_cnte / nm`F0 OCE ObCE OCE OfCE m`lE OO ObOb OO OfOf lEY YN NO NOb NO NOf textctrl/yptr_5 0 OrQ1 OA1 ^BA1
|
̺F0 f x}D0 ̺ ̦ ̦ б б ' ' S S d} d} x} cpu0/dec_regs/state_cnst_i_8[4]
|
^B@C0 ^BA1 OA1 l{^^D1 ll0A0 llHA1 OrO3 ^.@^B@ O3II IIO O3Y, Y,]: ]:^. O3O Y,v vrA rA{J^ rAh\ h\\ \^.@ h\^. h\l0 h\lH OO ^.^B ^.^B OO {J^{^^ l0l0 lHlH textctrl/y_cnt_s[1] 1 OF0 ODI0 OPJ OO PJO textctrl/y_cnt[1] 3 OQ0 O:B0 OB1 ^B B0
|
,IF0 f xkA0 ,I #I #I Ý! Ý! dk dk xk cpu0/dec_regs/state_cnst_i_9[4]
|
^B4A0 OA0 ul8B1 OPP PPII IIO: PPF FO
|
,3F0 f xqB0 ,3 #) #) dq dq xq cpu0/N_1739_i f ̺/F0 f x_DI0 ̺/ ,օ d_ x_ ,օ d_ cpu0/dec_regs/N_858
|
O
|
̺IF0 f xוD1 ̺I , , mՑ mՑ sӍ sӍ dו dו xו cpu0/dec_regs/state_32_iv_2[5]
|
O PPYP YP^. IIY Y] ]^.4 PPO YPl8 O:O: OO ^. ^B ^.4^B4 OO l8l8 textctrl/y_cnt_s[2] 5 OF1 ODI1 OPV OO PVO textctrl/y_cnt[2] 6 OQ1 O4A0 OLA1 ^B8B1 O2A1 ll6B0 OP\ P\F FI IO4 IOL P\Yt Yt^.8 P\O2 FYt Ytl6 O4O4 OLOL ^.8^B8 O2O2 l6l6 textctrl/y_cnt_s[3] 7 O\F0 ODI0 O\Ph OO PhO textctrl/y_cnt[3] 8 ObQ0 OA0 ORB1 ^BA0 OA0 ulA0 ObPn PnF FO OO OOR PnY Y^. PnO Yl OO OROR ^.^B OO ll textctrl/y_cnt_s[4] 9 OhF1 ODI1 OhPt OO PtO textctrl/y_cnt[4] : OnQ1 OB0 OB1 ^BB1 OA1 ul,D0 OnPz PzE_& E_&8EV 8EVJz JzNp NpO NpO PzSV SV^. PzO SVh hl, OO OO ^.^B OO l,l, textctrl/y_cnt_s[5] ; OF0 O
|
̺ʓF0 f x׃A1 ̺ʓ Jɛ Jɛ Ƅ Ƅ d׃ d׃ x׃ cpu0/dec_regs/state_32_0_iv_0[3]
|
DI0 OP O
|
{ ̺ɗF0 e xևA1 ̺ɗ ; ; aӱ aӱ dև dև xև cpu0/next_push_state[0] Q f9Q0 e x֓C1 xcD0
|
O
|
f9 f f Tљ Tљ > > @o @o dc > × × d֓ d֓ x֓ dc xc cpu0/dec_regs/state_cnst_m[3]
|
PO
|
HֱF0 e x֍B1 Hֱ ۜU ۜU б б d֍ d֍ x֍ cpu0/dec_regs/un1_state_1_sqmuxa_2
|
textctrl/y_cnt[5] < OQ0 O0A0 OA1 ^BA0 OA0 xlC1 OP PF~ F~O OO0 PS\ S\^. PO S\g gl PE_ E_ 8 8K
|
F1 e xցD0 e x֙D1 xD0 ֍B1 xgD0 xA0 xWB0 6! 6! JI JI sȉ sȉ dց sȉ d֙ sȉ s{ s{ d JI ȉ ȉ Ӎ Ӎ ֍ sȉ dg sȉ d sȉ dW dց xց d֙ x֙ d x ֍ ֍ dg xg d x dW xW cpu0/state_32[3] e ̺?F1 e xiDI1 ̺? ̬ di xi ̬ di cpu0/dec_regs/state_32_0_iv_0[2]
|
K
|
,ʓF0 e xuB0 ,ʓ ɛ ɛ >ϧ >ϧ 4؉ 4؉ du du xu cpu0/next_push_state[2] ,Q1 e xoA0 xUA0
|
O O0O0 OO ^.^B OO ll textctrl/y_cnt_s[6] = OF1 ODI1 OP OO PO textctrl/y_cnt[6] > OQ1 O.A1 mD0 OP PO. PyK yKNz Nz O.O. textctrl/x_cnt_s[0] ? {lF1 {^DI1 {l{9 {J{^ {9{J textctrl/N_76_i @ l{F0 {^CE
{^bCE {^CE {^fCE {{h {J{^ {Jb{^b {J{^ {Jf{^f {hre re{G {G{J {G{Jb {G{J {G{Jf textctrl/x_cnt_s[1] B {F0 {^DI0 {{ {J{^ {{J textctrl/x_cnt_s[2] D {F1 {^DI1 {| {J{^ | {J textctrl/x_cnt[2] E {Q1 ^BB1 {^2A1 l{^XC1 xlB1 {| |h h^. |{J2 |ujI ujI{JX hl ^.^B {J2{^2 {JX{^X ll textctrl/x_cnt_s[3] F
{\F0
{^DI0 {\| {J{^ |{J textctrl/x_cnt[3] G
{bQ0 ^BA0
{^A0 xlA0 {b| |h8 h8^. |{J h8l ^.^B {J{^ ll textctrl/x_cnt_s[4] H
{hF1
{^DI1 {h| {J{^ | {J textctrl/x_cnt[4] I
{nQ1 ^B2A1
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234h 34h2 22 34h<4 <4Yr Yr^.& <4O 22 ^.&^B& OO textctrl/vsync_cnt_s[2] S 2F1 2DI1 23:h 22 3:h2 textctrl/vsync_cnt[2] T 2Q1 2 B1 o^BB1 tOD1 23@h 3@h*qn *qn*UgL *UgL) )2 3@h
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oF1 xA0 o d d ܅ ܅ d d x cpu0/dec_regs/state_cnst_i_RNO_0[5]
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2T3^ 3^2 3^<~ <~O <~Y~ Y~]4 ]4^. 22 OO ^.^B textctrl/vsync_cnt_s[5] Y 2F0 2DI0 23j 22 3j2 textctrl/vsync_cnt[5] Z 2Q0 2A0 *O&D1 sA&&D1 ^BB1 23p 3p2 3p
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F1 xB0 : : IY IY a a d d x cpu0/N_1010 ̺UF1 xC0 ̺U 8 8 d d x cpu0/dec_regs/state_cnst_i_7[5]
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]] |N |N UD UD Ƀ Ƀ a aӍ Ӎ] textctrl/tshift[3] n kEQ1 gz$C1 E
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F0 xD0 Hk Hk _- _- g g d d x cpu0/dec_regs/N_961
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No {J {^ No | C | C U8 U8 & & tu tu r ruY uY{J textctrl/tshift[4] p l{Q0 hB0 {{ {rk rk textctrl/font_data[5] q b Q1 l{^"M1 Zo {J"{^" Zo U8t U8tt t&ޞ &ޞtu tur}V r}V{G {G{J" textctrl/tshift[5] r l{
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| | $ $$ textctrl/font_data[6] s cɝQ0 mM0 ɝ; ;o o@ @' ' textctrl/tshift[6] t m.fQ0 i~A0 .f ? ?4 4~ ~~ textctrl/font_data[7] u cɩQ1 mM1 ɩ; ; ` ` ]n ]nx x textctrl/tshift[7] v m.rQ1 iB1 .r#3 #3 textctrl/shift[0] w f.LQ0 fD1 .L % % textctrl/N_25 x f.RF1 f|DI1 .R || | textctrl/shift[1] y f.XQ1 gz C0 .X# #d df f z textctrl/shift_7_i_m3[2] z gF0 gzDI0 h fz hf textctrl/shift[2] { gQ0 gz B1 h hc cf f z textctrl/N_27 | gF1 gzDI1 h fz hf textctrl/shift[3] } gQ1 hD0 "h "h% % textctrl/N_28 ~ h.F0 hDI0 .h h textctrl/shift[4] h.Q0 hA1 .h h textctrl/shift_7_i_m3[5] h.F1 hDI1 .h h textctrl/shift[5] h.Q1 iC0 .h h textctrl/shift_7_i_m3[6] i.BF0 irDI0 .B rr r textctrl/shift[6] i.HQ0 iA1 .H textctrl/shift_7_i_m3[7] i.NF1 ixDI1 .N xx x textctrl/shift[7] i.TQ1 ^lA1 .T vx vxl ll textctrl/N_91 dmvF0 dlDI0 mvm ll ml textctrl/line_cnte o^F0 dl|CE elCE ^_ l|l| ll _Ud Udhn hnk kl| kl textctrl/N_26_i dmF1 dlDI1 mm ll ml textctrl/N_60_i emF1 el.DI1 mmr l.l. mrl. textctrl/hsync_cnt_s[0] #mz8F1 #lzbDI1 mz8mz lzblzb mzlzb textctrl/hsync_cnt_s[1] "mzF0 "lzDI0 mzmfzN lzlz mfzNlz textctrl/hsync_cnt_s[2] "mzF1 "lzDI1 mzmrzN lzlz mrzNlz textctrl/hsync_cnt_s[3] !m{(F0 !l{XDI0 m{(mz~ l{Xl{X mz~l{X textctrl/hsync_cnt[3] !m{.Q0 !l{jB0 {^{vD0 {^{D1
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HF0 xD1 H ۺQ ۺQ Ӵ Ӵ (s (s d d x cpu0/N_946 HF1 C1 H cpu0/dec_regs/state_cnst_m_7[0]
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m{.mz~ mz~k| k|l{j mz~vsp vspz&| z&|{J{v z&|{J{ l{jl{j {J{v{^{v {J{{^{ textctrl/hsync_cnt_s[4] !m{4F1 !l{^DI1 m{4mz~ l{^l{^ mz~l{^ textctrl/hsync_cnt[4] !m{:Q1 !l{B1 {^{dA0 {^{|A1 m{:mz~ mz~vsd vsd{J{d vsd{J{| mz~g r g rc_z `Z\c_z `Z\cl cll{ l{l{ {J{d{^{d {J{|{^{| textctrl/hsync_cnt_s[5] m{F0 l{DI0 m{mz l{l{ mzl{ textctrl/hsync_cnt[5] m{Q0 l{B0 ){^{A1 k{^B1 p{pC0
m{mz mzkv kvl{ mzq x( q x({J{ q x(re re{J q x(s s{p l{l{ {J{{^{ {J{^ {p{p textctrl/hsync_cnt_s[6] m{F1 l{DI1 m{mz l{l{ mzl{ textctrl/hsync_cnt[6] m{Q1 l| B1 ){^| D1 k{^D1 p{dA0 w{^B0 m{mz mzch< chQ1 {^zB1 ){^{C0 ){^|C1 k{^A1 p{B1 w{^A1 {z>{y {yuj uj{J {yx" x"{ uj{J {yur urr__z o[Z\r__z o[Z\r)k r)k{Jz r)k{J{ r)k{J| {Jz{^z {J{{^{ {J|{^| {J{^ {{ {J{^ textctrl/hsync_cnt_s[9] {zF0 {^zDI0 {z{zN {Jz{^z {zN{Jz textctrl/hsync_cnt_s[10] {zF1 {^zDI1 {z| zN {Jz{^z | zN{Jz textctrl/hsync_cnt[10] {zQ1 {^zA1 ^lB0 nlC0 p{jB0 r{^ C1 vlB0 B1 {z|zN |zN{Jz |zNq w q wc" c"l c"l |zN s| s|{j |zNrY rYuY uY{J c"l ll rY {Jz{^z ll ll {j{j {J {^ ll textctrl/bluerc_i ^mF0 ^lDI0 mmfh ll mfhl textctrl/bluer[0] ^mQ0 mC1 mmlh mlhf/ f/v$ v$ textctrl/blink_cnt_s[0] {m F1 {^mHDI1 {m {l {JmH{^mH {l{JmH textctrl/vsync_cnt_0_sqmuxa r{F0 {^nCE {^nCE {^mCE {^mCE {|0 {Jn{^n {Jn{^n {Jm{^m {Jm{^m |0r;yB r;yBuYj` uYj`{Jn uYj`{Jn uYj`{Jm uYj`{Jm textctrl/blink_cnt[0] {m$Q1 {^mfA1 {m${l {l{Jmf {Jmf{^mf textctrl/blink_cnt_s[1] {mF0 {^mDI0 {m{m4 {Jm{^m {m4{Jm textctrl/blink_cnt[1] {mQ0 {^mA0 {m{m4 {m4{Jm {Jm{^m textctrl/blink_cnt_s[2] {mF1 {^mDI1 {m| m4 {Jm{^m | m4{Jm textctrl/blink_cnt[2] {mQ1 {^mA1 {m|m4 |m4{Jm {Jm{^m textctrl/blink_cnt_s[3] {nF0 {^n>DI0 {n|md {Jn>{^n> |md{Jn> textctrl/blink_cnt[3] {nQ0 {^nJA0 {n|md |md{JnJ {JnJ{^nJ textctrl/blink_cnt_s[4] {nF1 {^nDDI1 {n| md {JnD{^nD | md{JnD textctrl/blink_cnt[4] {n Q1 {^nbA1 {n |$md |$md{Jnb {Jnb{^nb textctrl/blink_cnt_s[5] {nF0 {^nDI0 {n|0m {Jn{^n |0m{Jn textctrl/blink_cnt[5] {nQ0 {^nA0 mA0 {n|6m |6m{Jn |6mra rarmtl rmtlf f {Jn{^n textctrl/N_85 l{F1 l{^ C0 {| h | h{J {J {^ textctrl/N_87 ^mF1 ^lD0 mmrh mrhcy cylm lmfr frcn cnl ll textctrl/N_117 *OF1 ^l A0 nlA0 *OC0 tOD0 vlA0 yOD1 OP PS< S
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HcF0 D1 Hc ۺ ۺ cpu0/dec_regs/state_cnst_m_11[0]
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{{(|z~ |z~z| z|{J| |z~rM rM{G {G{J rM{J {J| {^| {J {^ {J{^ textctrl/visible_2_i_o3 mmNF1 l{^A1 mlC0 mNm mq B q B{J ml {J{^ ll textctrl/x_cnt5_x_8_0 .F1 l{^$C1 . w2` w2`z z{J$ {J${^$ textctrl/N_83 w{FF0 nlD0 {F{+ {+g gk kl ll textctrl/N_108 r{F1 nlB0 o^BA0 q^BA0 r{^C0 m{^A0 {|< |
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cpu0/regs/ea/N_240 PF0 PXC1 /NB1 d dX d N XX NN cpu0/regs/ea/N_264 CF1 ҲTC1 #@2A1 CҲ"C0 DҲB0 E@LA1 Ӑ Ӑ ,2 ӐҞ ӐҞ" Ӑ̾I ̾IҞT ̾Iܖ ܖ,L ҞTҲT ,2@2 Ҟ"Ҳ" ҞҲ ,L@L cpu0/regs/ea/N_268 G F1 " BD1 G B:B0 9\B0 9\B1 : BD0 : BC1 ; BBD0 ; BTC1 .T .B . . . + + .: : :H :H . B .: B: H\ H\ . B . B .B BB .T BT cpu0/regs/ea/N_277 " vF0 " BA1 G BFD0 9\A0 9\A1 : BC0 : BD1 ; B6B0 ; BHA1 v .6 .
. . .F H H .H . B .F BF H\ H\ . B . B .6 B6 .H BH cpu0/regs/ea/N_289 #F0 #@>C1 FA0 ,> y\ y\ ,>@> cpu0/regs/ea/regs_o_eamem_addr[8] ) F1 $ XA0 8 X ZA0 >\ CC0 ^ ^ c 4 c 43 3 3 3H C *re *re Oȭ Oȭ W ^ *r *r O 4 O 4 W 0 W 0 W Z W X W Z X Z H C\ C cpu0/k_memhi[0] ׳Q0 : CD0 ҲC0 XA1 $ XC0 4 XA0 4 XA1 >\ CB0 ׳ ֵ ֵ UD UD $2 $2 #) 3 #) 3 6 ; 6 ; : C UD ɕu ɕuɕ ɕҞ 62 626 O 6 O I IE A( E A(H C $2 V:l V:l NY NY N% N% W N% W V:l P P N N W N W : C : C ҞҲ W X W X W X W X H C\ C cpu0/regs/ea/datamux_o_dest_6[8] $ XJF0 : CC0 $ X
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5 Q
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^EFCI ^E^E textctrl/x_cnt_cry[4] ?
{aFCO {aFCI {a{a textctrl/x_cnt_cry[2] A {aGFCO
{aSFCI {aG{aS textctrl/x_cnt_cry[0] B {aFCO {aFCI {a{a textctrl/y_cnt_cry[4] D OFCO OFCI OO textctrl/y_cnt_cry[2] F OGFCO OSFCI OGOS textctrl/y_cnt_cry[0] G OFCO OFCI OO textctrl/vsync_cnt_cry[8] I A)FCO A)FCI A)A) textctrl/vsync_cnt_cry[6] K 2)FCO A)=FCI 2)2, A:A)= 6jA: 2,6j textctrl/vsync_cnt_cry[4] L 2FCO 2FCI 22 textctrl/vsync_cnt_cry[2] M 2-FCO 29FCI 2-29 textctrl/vsync_cnt_cry[0] N 2FCO 2FCI 22 textctrl/blink_cnt_cry[4] P {anwFCO {anFCI {anw{an textctrl/blink_cnt_cry[2] S {amFCO {anFCI {am{an textctrl/blink_cnt_cry[0] T {am{FCO {amFCI {am{{am textctrl/hsync_cnt_cry[8] V {azFCO {azFCI {az{az textctrl/hsync_cnt_cry[6] X l|FCO {az#FCI l|l| {Jz {az# qwP{Jz l|qwP textctrl/hsync_cnt_cry[4] Y !l{FCO l{FCI l{l{ textctrl/hsync_cnt_cry[2] Z "l{FCO !l{ FCI l{l{ textctrl/hsync_cnt_cry[0] [ #lzFCO "lzFCI lzlz cpu0/un1_state_126 FIF0 $@A1 \C0 A0 A1 A0 A1 A0 A1 A0 A1 @A0 @A1 @A0 @A1 @A0 @ A1 G@B1 JҲB1 + If H\ fܖܑ ܖܑ, fI I, I, ܖܑ, ܖܑ, I, I, ܖܑ ܖܑ ܖܑ ܖܑ ܖܑ ܖܑ fɧՑ ɧՑҞ ܖܑ5Ց 5Ց, ܖܑ ܖܑ I ܝ ܝH߲ H߲H ,@ ,@ ,@ ,@ ,@ ,@ , @ ,@ ҞҲ cpu0/un1_regs_o_su_iv_0[0] GF0 $@C1 G@D1 ֵ ,@ ֵQ Q) ), ֵ>Ҙ >Ҙ, ,@ cpu0/un1_cpu_reset_13 F0 $@D1 FҲA0 G@
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ܯ ܯ A R v~ v~{J In n ̭a ̭aҞm Ӂ Ӂq Ix xҞ gҞ v~{J ҞiҲi 44 0$0 AA RR {J{^ ҞmҲm qq ҞҲ ҞҲ {J{^ cpu0/test_cond/N_1005 d }F0 A0 ,o ,o cpu0/test_cond/N_1264 e mgF0 -C0 C0 ~{^C0 mglL lLv$ v$- v$ v${J -- {J{^ cpu0/test_cond/N_1252 f ~{sF1 ;A0 B0 ~{^B0 {s{@ {@] ] ; ] {@{J ;; {J{^ cpu0/test_cond/k_pp_regs_25_sn_m12_1 i ~{gF0 {^D0 {g{L {Lr; r;{J {J{^ state_o_c[0] q 8 [J5Q0 D0 z A1 0uC1 :zDD1 ?:B0 ?RB1 @D0 L{^OA1 [A1 ]l;A0 z^BA1 }+C1 A0 A1 {^A1 'C1 NB1 B0 A1 z^D1 LA1 A1 {^B0 {^B1 zB1 ҲZD1 z4B1 zA1 $_C1 lA0 ҲB1 {^uC1 $D0 1ҲD0 :zB0 ~A0 Ҳ>C1 A0 lOA1 A1 $D0 $D0 $-D1 A0 2A1 $C0 $C1 lB0 lB1 QA0 iA1 R{^D0 R{^D1 Ҳ B1 PADDO J5օ IM օq qw w q ܑ ܑf w] ]\ \u ]o] o]o ofD o^ ^R R: RR w wv= v={JO ^ v=l; v܋ v܋Y܋ Y܋^. ܑ\ \+ օA/ A/ A/ v܋{J \' RN ^ o]^C ^C of^ ^L oT T TzP zP{J v܋rSՑ rSՑ{J oo of ^Cs s ҞZ of4 ]f s_ rSՑh8W h8Wl ̭ ̭Ҟ rSՑ{Ju ̭Ҟ ]6o 6of p p~ N Ṋ ̭Ҟ> ^C v=lO T z z \ - oT T T2 N o^ ^ v܋cՑ cՑl cՑl ]Q ]i v=z\d z\d{J z\d{J NҞ v=>\ >\V= V=IM f z uu fDzD :: RR {JO{^O l;l; ^.^B ++ {J{^ '' NN f^z^ LL {J{^ {J{^ fz ҞZҲZ f4z4 fz _$_ ll ҞҲ {Ju{^u $ ҞҲ fz ~~ Ҟ>Ҳ> lOlO $ $ -$- 22 $ $ ll ll QQ ii {J{^ {J{^ Ҟ Ҳ cpu0/N_925 F1 B0 aD1 tֵ tֵҘ Ҙ tֵg g a aa cpu0/test_cond/N_1002 n F0 C0 hֵ hֵҘ Ҙ cpu0/state_cnv_2[0] vF0 $C0 $C1 v Zw Zw $ $ cpu0/test_cond/un1_state_49_2 p ɗF0 $D0 ɗ; ; ɏ ɏ% % $ cpu0/N_1893_1 .%F1 $A0 $B0 D1 A1 $A0 UA0 "$oB1 .% o o ~ ~ o o1 1 a aU oo g g $ $ $ UU o$o cpu0/test_cond/op[4] u o F0 o B CM0 B 5A0 . C B C (k (k @ @ + ?x + ?x . C @ . 5 . 5 B 5 cpu0/test_cond/cond_taken4 v o CbOFX0 \KD1 Cb Bp Bp| < | < A A HK HK\K cpu0/test_cond/un1_op_3_3 w BlF0 o B CC1 Bl B B + ?~ + ?~ . C . C B C cpu0/test_cond/op[1] x r AF0 o B CA0 o B CD1 p BM1 A A B B A ? ? . C ? J ;& J ;& >S >S B A ? ? . C . C B C . C B C cpu0/test_cond/op[3] y q 4F0 o B CA1 p B0B0 p BNC1 q BB0 q BC1 B B ;> ; ; 3 3 - - . 5 ; . B ; . C . C B C . 5 B 5 . B B B cpu0/test_cond/op[2] | BxF1 o B CB0 p BM0 q BM0 B BA0 Bx B B B B B B + ?l + ?l . C B ~ : ~ : .0 .0 A A B A ?r ?r B A
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zB1 D1 {ֱ{U {U/ / /σ σu uf fz cpu0/test_cond/N_1274 {F0
zM0 M0 zM0 M0 M0 #M0 {^M0 M0 {|0 fz fz ## {J{^ |0uj6 uj6B Bf B Bi ic cf B # |0r5k r5k{J B cpu0/k_pp_regs_25[7] ' .aOFX0 DI0 .aR R cpu0/k_pp_regs[0]
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zB0 zD0 /lC1
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܄ ܄ Ҟ \ ތ 60ܗ 60ܗ : . OP B OP : : Ҟ \Ҳ \ : : cpu0/regs/N_1439 X + F0 $ D1 ӄ " ӄ "] ` ] ` $ cpu0/regs/ACCA[0]
( " Q0 BB0 A0 C0 3 B0 : BB1 ҲA1 Y Y
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mm mq c q c f u uf ml fz fz ll cpu0/k_pp_regs_25[0]
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zDI0 ]( fz (f cpu0/test_cond/k_pp_regs_cnst[6] {ֽF1 B1 zB1 B1 EC1 YB1 {^5A1 {^C0 {ֽ| U | U{J | Ut6> t6> f E Y | UrY rY{J5 fz EE YY {J5{^5 {J{^ cpu0/k_pp_regs_25[6] % {OFX0 {^DI0 {|* {J{^ |*{J cpu0/test_cond/N_1258 /mcF0 zB0 !A0 lD0 mcm m| |Q Qf mv v! mk kl fz !! ll cpu0/k_pp_regs[4] " .Q0 3D0 lC1 lC1 l'B0 ^BC1 plC0 slA0 lC0 B1 {^[C1 . 3 (6 (6v6ܻ v6ܻcC cCl v6ܻl cCl' cCY Y^. cCl cCl v6ܻl %] %] Q Q r/ x r/ x{J[ 33 ll ll l'l' ^.^B ll ll ll {J[{^[ cpu0/test_cond/k_pp_regs_4_sqmuxa_1 ..oF1 'B0 .C0 .o ' '' cpu0/k_pp_regs_25[4] ! .OFX0 DI0 .&4 &4 cpu0/test_cond/k_pp_regs_2_sqmuxa_2 .F0 A0 GC0 ~{^C1 . P P PG - -{J GG {J{^ cpu0/test_cond/k_pp_regs_6_sqmuxa {cF0 B0 MD0 ~{^B1 {c| |z z{J |rM rM{G {G {J {Jw w wM MM {J{^ cpu0/k_pp_regs_25[5] # .OFX0 /DI0 .&N // &N/ cpu0/k_pp_regs[3] .Q0 A0 .D0 .C1 lA1 l3D0 וD1 {^C1 l1D1 slC0 lA1 lMD0 leD1 {^OA1 % . Ց ՑvW vWc cl cc cl3 cv vrS rS{J cl1 cl cl ll clM cle v{JO ՑӍ Ӎו ll l3l3 וו {J{^ l1l1 ll ll lMlM lele {JO{^O cpu0/test_cond/un1_k_pp_regs_4_sqmuxa ..cF0 D0 lA0 .c P P v vl ll cpu0/k_pp_regs_25[3] .wOFX0 DI0 .w cpu0/k_pp_regs[2] Q0 zA0 /lB0 /lD1 l9A1 {^B0 plB0 lB1 lAC1 lA1 lAB0 lYB1 xzC0 {^UB1 " ` `f `%G %Gv vl vlA vlY `P PK? K?f v{JU vr_ r_{J vc cl cl ll ll9 cl llA cl fz ll ll l9l9 {J{^ ll ll lAlA ll lAlA lYlY fz {JU{^U cpu0/k_pp_regs_25[2] {OFX0 zDI0 {l fz lf cpu0/k_pp_regs[1] .Q0 D0 \l=B0 l?B1 #B0 {^D0 plA0 lC1 lGD1 l B0 l!B1 lGC0 l_C1 xz B0 & . ` ` `v6 v6k kl= v6cU cUl? `(P (P# v6k kl cUf fl cUlG fl fl! v6lG v6l_ `%w %wo of oT Tz\ z\{J l=l= l?l? ## {J{^ ll ll lGlG l l l!l! lGlG l_l_ f z cpu0/k_pp_regs_25[1] .{OFX0 DI0 .{l l cpu0/k_pp_regs_cnst_sn_N_36 | R{F1 {^C1 {|< |
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bo . Y Y {: {: . ܨ ܨҞ . B . B ҞҲ cpu0/regs/ea/N_281 3F1 3"C0 F B0 " "" cpu0/regs/ea/N_227 3F0 -_C1 5D1 __ I I _ I cpu0/regs_o_pc[0] 0 L IQ0 ? ,^D1 IzB1 BoB1 @sB1 4@A0 ҲcD0 IzC1 I J ,J ,^ J @ @ 6 6 #e #e ,J J Ic Ic If #e %6 %6 c c .o J BR BR @ @ If J ?%: ?%: ~M ~M ,s J * *< ,^,D0 $D1 B1 :ևA1 ,@7A0 UA0 b ,J, ,^, ] ] C C,7 Ց Ց = =e e C
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fF1 Ҳ]C0 'B0 E{^ցD0 IzKD1 QҲC1 _{^'B0 _{^?B1 $AC1 $-C0 ҲaC0 /D0 ҲC0 " f ͜ ͜Ҟ ͜Ҟa A ͜Ҟ] - ' '/ ]c ]cҞ ' x xr_ r_{Jց ' fK 0 0{J' 0{J? Ҟ]Ҳ] '' {Jց{^ց fKzK ҞҲ {J'{^' {J?{^? A$A -$- ҞaҲa // ҞҲ cpu0/test_cond/k_pp_regs_cnst_sn_m17_2 JF0 $'B0 Jo oތ ތɭ ɭh h' '$' cpu0/test_cond/k_pp_regs_cnst_sn_m17_6 fF0 $!A0 fĺ ĺ1
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! !$! cpu0/dec_o_p1_mode[1] 1 # F1 XUA0 X~A0 XB1 @9A1 + X6B0 , XB0 , XB1 -C0 0 ,^D0 0 ,^&D1 9A0 -$A1 A1 $9A1 @D1 @LA1 )C0 A0 #B0 7A0 $D0 \ A0 A0 SA1 $1D1 B1 # X(D0 $ A0 % XA0 \ B1 BD1 :aD1 { A0 {A1 j y' y'> >9 >
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NA NA Rm Rm Wa En ngL gL *uA *uA N N W N W p Vr r,? N O'V O'V W W W0 N W N W ʺ3 3{ *e #/R #/R ,G ,G ,J pA A σ σ V L L6 p . ʺZ Z ,R r# ': : U U= Lf: ϛ ϛ .E L{ {f U S S; : 9 y y 3 , , L L Wa Xa W X W X $ ,?@? W0 X0 W X W X {{ ,J ,^ $ 66 ?$? .. ,R@R ## == f:z: $ .E BE fz H\ ;; 99 ,@ ,@ cpu0/un1_state_7_1_RNIPAL21 JF1 A0 -C0 -$C1 Iz3D0 IzEC1 _{^3D0 B0 $B1 B1 $A1 gD0 A0 A0 ҲA0 dB0 dB1 oB1 9 J AC AC( ( % %Ɲ Ɲ 6 6- 6 6* *f3 *f ffE ( hJ܅ hJ܅rA rA{J3 ߲ ߲ %
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)|օ |օy y / /lE lEo o /;M ;M,= ,=@= cpu0/regs/ea/N_73 ,F0 ,B0 Q Qۂ ۂl l cpu0/regs_o_pc[2] 1 N , Q0 > ,^DD1 ҲKD1 ҲGD1 :B1 -@C0 {C0 , , ,JD ,^D , # # #S #S ,JD , %`6 %`6 5 5 : ,zj zj C Cқ қҞK zj9 9 , zj&j &j' '{ CҞG ҞKҲK ҞGҲG : : ,@ {{ cpu0/regs/ea/ea_reg[2] OFX0 5B1 -@B0
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z4 z4yc yc ܄ ܄, yc; ; ,@ cpu0/regs/ea/N_74 -zF0 ,D1 zn_ n_ۂI ۂI l+ l+ cpu0/regs/regs_o_pc[3] = Q0 = ,^D0 @A1 @C1 < fD0 .@C0 cD0 ,J ,^ ' ' ,J
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HE HE\E cpu0/test_cond/cond_taken67 5RF0 \9A1 5R 4 4 2 2 ' ''G 'GH9 H9\9 cpu0/dec_o_cond_taken F1 \-C0 H- H-\- cpu0/test_cond/k_pp_regs_3_sqmuxa msF1 lB0 msm@ m@l ll cpu0/test_cond/k_pp_regs_5_sqmuxa_1 mF0 lC0 mmf mfl ll cpu0/un1_state59_10 8 mYF1 g{^B1 lB0 lC0 n{^D0
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mYm& m&q C q C{J m&l m&l q C{J {J{^ ll ll {J{^ cpu0/test_cond/k_pp_regs_6_sqmuxa_1 n{F0 ~{^D1 {{o {oud6 ud6{J {J{^ cpu0/test_cond/N_58 q BfOFX0 p BFXA Bf
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A B B
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A B cpu0/test_cond/N_65 p AOFX0 p B FXB A A B B A B cpu0/state192_6 o .UF1 .A0 {^D1 {^C1 C0 .U 6 6 6w w{J {J {J{^ {J{^ cpu0/un1_state59_6 Y mF1 .A1 lD1 l-C0 l A1
mmr mrq ] q ]f f mrc cl mrl- cl ll ll l-l- l l cpu0/regs_o_CCR[3] I 5F0 Iz 6 DI0 p B6C0 u$C0 D0 u$wC0 @aC0 @?B1 I 5 J. 5& If 6 Iz 6 J. 5& If 6 J. 5& C - C - # # 4 4 B6 J. 5& ?% 2 ?% 2 d 0 d 0 0 3 0 3 Y Y ~ϕ ~ϕ uw Y ,a ~ϕ u Y )9 )9 >1 >1 zA zA zu zu 2 2 ,? zA B6 B6 u u$ uw u$w ,a @a ,? @? cpu0/test_cond/N_59 BF1 p B*A0 B B@ B@ DD DD B* B* B* cpu0/test_cond/op[0] AF1 C>A1 p BS >S C> ;V >S >S B< >S BB >S B >S B v A . B0 C> C> B< B< BB BB B B B B . B0 B B0 cpu0/regs_o_CCR[2] BF0 CJC1 CDI0 p BTD1 D0 IzC0 :D0 D0 f (A0 B B@ C C B@ C B@ : : - - l l ( ( : l GK GK , , z z l ' ' Dd Dd If B@ CJ B@ BT - G G l l a a f ( GK t t z8 z8 CJ CJ BT BT If Iz : : f ( f ( cpu0/test_cond/k_pp_regs_25_sn_m6_0 /moF1 /lC0 mom ml ll cpu0/test_cond/un1_state59_4 mF0 /lA0 mm mf6 f6l ll cpu0/next_push_state[0] Q0 }D0 D0
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ț țW WW ,@ cpu0/regs/ea/N_75 .}F0 +=B0 }! !y y= == cpu0/regs_o_pc[4] 9 O fQ0 = ,^D1 $EC1 C1 IzGD1 /@A0 %B1 f ? ,J ,^ ? / / P P 1
1
E n nU U Gљ Gљ @) @) IfG U% ? '$ '$ +& +& ,J 6 6A AG G, E$E IfG IzG ,@ %% cpu0/regs/ea/ea_reg[4] OFX0 4oB1 /@D0 4 4 / /g go /% %, oo ,@ cpu0/regs/ea/N_76 /yF0 +UB1 y | |A A U UU cpu0/regs/regs_o_pc[5] > Q0 < ,^(D0 $A1 $-D1 7 : D1 /@D1 iA1 l ,J( ,^( l 'l l " \ " \ ˊ ˊhܗ hܗ - 'l 1 1 3 3 1 1 : 3 rZ rZY Y, ˊ a a i hܗ " \ 6 6 : : 0 0 ,J( $ -$- : : ,@ ii cpu0/regs/ea/ea_reg[5] OFX0 3B0 /@A1
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j j1 1, 1ɕA ɕAܺQ ܺQ~ ~ ,@ cpu0/regs/ea/N_77 /F1 *D0 cpu0/regs_o_pc[6] 2 P ,Q0 < ,^@D1 $sB1 D1 :B1 .@D1 ևA1 , -6 ,J@ ,^@ -6 #;v #;v &Y &Y ,J@ -6M M6 6K Ko os Ky[ y[ 6 6fQ 6fQ 1[ 1[ : y[e eև - - , s$s : : ,@ ևև cpu0/regs/ea/ea_reg[6] OFX0 3B1 .@A1 k k5] 5];Y ;Y, k$] $]o o ,@ cpu0/regs/ea/N_78 .F1 *B1 ! ! O O cpu0/regs_o_pc[7] 3 Q Q0 ; :D0 Ҳ B1 ҲB1 X֓C1 -@B1 sB1 l : : l 'l 'l 1 1 : 1 '~ '~m m σ σҞ σҞ σ
hr
hr Ddϛ Ddϛ W֓ l , %ț %țc cs Ҟ Ҳ ҞҲ W֓ X֓ ,@ ss cpu0/regs/ea/ea_reg[7] -OFX0 2\[B0 -@C1 - < < , ) )Qw QwWs WsH[ H[\[ ,@ cpu0/regs/ea/N_79 -F1 )\AB0 tS tSL L$) $)KK KKE EHA HA\A cpu0/regs/regs_o_pc[8] ? ,׳Q0 ; :C1 D1 oB1 8 X ~C1 ҲD0 ,@UB1 ,׳ -6ֵ : : -6ֵ 0/ 0/ 3 3 1 1 : 3 '/ '/ o o o o 0/ 3> 3> D D O O W ~ 3 r r ;o ;o,U ;o,ʍ ,ʍ Ҟ o o W ~ X ~ ҞҲ ,U@U cpu0/regs/ea/ea_reg[8] ! )OFX0 2\sB1 ,@OA1
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c% c%w S w S} w S }} cpu0/test_cond/state_32_0_iv_0[3] .3F0 kA0 .3 k kk cpu0/un1_state_1_sqmuxa_2 9 .;F1 ]zUA0 wC0 A1 A0 zD0 #zqB0 #zB1 .;օ օ%) %)ow owfU օw %)k k օ %)f %)fq %)f fUzU ww fz fqzq fz cpu0/regs_o_CCR[0] XJ OF0 CDB1 f (C1 q BB1 D0 C0 0A0 A0
X PC1 d f OPC0 X OC1 XJ O X O* X O* JG JG | )g | )g | | zh X O* \A M \A M f OP zh \A M 8 J/ 8 J/ C Ap C Ap ;> ;> CD | )g p ! p ! f ( ;> B | z z zh X O* W L W L W P X O* W O z 0 CD CD f ( f ( B B 0 0 W P X P f OP f OP W O X O cpu0/test_cond/N_1802 F1 ҲC0 Ӑ Ӑў ўҞ ҞҲ cpu0/N_1800_i FF0 ҲvDI0 F+ ҞvҲv +Ҟv cpu0/un1_state59 Z
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) ~օ ~օ0 0w wܨ= ܨ=,O w] ]o oHs Hs\s ,O@O cpu0/regs/ea/N_80 " ,F1 )\YB1 Q Qy yO OHY HY\Y cpu0/N_128 ! F1 u$ C1 @ Iz )D0 f 6$A1 Iz (zB0 : C,B0 : D0 : (C0 C0 C1 Iz[C1 u$ 5 C0 u$ 5.B1 X (C0 X )B1 f 5C0 f 5C1 X 'B0 X (B1 f (C0 f (C1 f 6A0 f 6A1 0 X (tA0 0 X (C1 1 Iz (C0 1 Iz (C1 \ Iz CD0 \ Iz CA1 f : 5 C0 f : 5:D1 X C>A1 A0 ` T T } } z X z X p p u p S S @ 'r @ 'r If ) p ] 'r ] 'r f 6$ @ 'r If (z S 5 5 9 9 : z X } } } T U8 U8 5 5 If[ ] 'r p .< p .< u 5 p .< t 19 t 19 u 5. ] 'r S ! S ! W ( S ! V * V * W ) ] 'r ` 2" ` 2" f 5 ` 2" f 5 V * W ' V * W ( ] 'r ` % ` % f ( ` % f ( ` 2" f 6 ` 2" f 6 S ! V * V * W (t S ! W ( S ! If ( S ! If ( S ! @ 4 @ 4 Cu ?< Cu ?< If C S ! O 4 O 4 W C> } @ 4 If C @ 4 Cu ?6 Cu ?6 If Cb If Cb ?% ? ?% ? : C, S O 'r O 'r Dv ! Dv ! : ( O 'r Dv .6 Dv .6 : 5 ] 'r ` 2( ` 2( f 6H f 6H \A 2 \A 2 EN - EN - : 5: u u$ If ) Iz ) f 6$ f 6$ If (z Iz (z : C, : C, : : : ( : ( If[ Iz[ u 5 u$ 5 u 5. u$ 5. W ( X ( W ) X ) f 5 f 5 f 5 f 5 W ' X ' W ( X ( f ( f ( f ( f ( f 6 f 6 f 6 f 6 W (t X (t W ( X ( If ( Iz ( If ( Iz ( If C Iz C If C Iz C : 5 : 5 : 5: : 5: W C> X C> cpu0/regs/SU[10] B 5Q0 3D0 ,^;B1 AC1 r 5A0 Iz (C0 Iz (C1 5 5& 5&" - " -
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1 X 1 X : x ,@ ,և@և : x : x Ҟ7Ҳ7 U$U cpu0/regs/regs_o_su[12] ;. (DF1 : : rA1 ;. (D ; ' ; ' 1 " 1 " : 0 : 0 : r : r : r cpu0/regs/ea/N_1258 g 2 IF0 IzD0 I JL JL If If Iz cpu0/regs/ea/N_1290 i 2 I F1 ? ,^C1 IzD1 I JX ,J ,^ JX ?%@ ?%@ 'Z 'Z #w* #w* ,J JX If If Iz cpu0/regs/k_new_pc[0]
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e $ e $ f )X C ]}r r ˢ ϕ ϕ Gl A (k A (k @K @ @K @ If C m s s d ˢɳ ɳҞ f ' f ' (z (z C$C f f ' ' ue u$e u u$ , @ e e , @ ,S @S ҞҲ $ ҞyҲy d x d x 7 7 If C Iz C d x cpu0/dec_ea/state_32_iv_3[0] fF0 [}D0 fֵ ֵ/ /F% F% } }} cpu0/N_971 /F0 [kA0 /Jօ Jօpq pqk kk cpu0/dec_ea/state_cnst_m_12[0] JֱF0 [qB0 JֱU Uӷ ӷq qq cpu0/state_32[0] [J/F0 [_DI0 J/օ __ օ_ cpu0/dec_ea/state_cnst_m_7[0] JF0 D0 J D6 D6 յ յӱ ӱ cpu0/dec_ea/state_cnst_m_8[0] 8J F1 A0 J ? ? cpu0/dec_ea/state_cnst_m_10[0] J}F0 C0 J}! !ȭ ȭ cpu0/k_pp_regs60 JIF0 BD0 C1 +C1 dC1 {D1 JI xJ xJr;I r;IE E{ r;Is s B ܯ ܯ+ ܯ BB ++ {{ cpu0/un1_state_86_0 . F1 6B0 . 6 66 cpu0/k_pp_regs60_RNI18KD3 .F0 $CE ҲLCE HCE @CE . $ ҞLҲL HH ,@ 1 1 1 t tҞL H , cpu0/k_forced_mem_size41 F0 ҲoA0 K B B0 ҲC0 ӄ ӄI I˴ ˴ɿ ɿNϏ NϏ ] ] . ɿҞ ɿ̭{ ̭{Ҟo ҞoҲo . B ҞҲ cpu0/un1_dec_o_write_flags K F0 qB0 6\B1 K B DI0 D1 . B . H H Y@ Y@|ω |ωH |ωȿ ȿ |ωq qq H\ cpu0/N_1589 D ɣF1 D0 eD1 QA0 ɣ8; 8; @ @ e 8;A AK KQ 8;Ɨ Ɨ ee QQ cpu0/dec_ea/un1_state_87_1_0 f}F0 A0 f}ĺ! ĺ! e eƩ Ʃ cpu0/dec_ea/k_eahi_0_sqmuxa_2 F0 B0
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ӽ $ cpu0/dec_ea/state_32_iv_0[0] .F1 C0 .ֵ ֵ cpu0/N_165 .zF0 A0 A0 B1 @B0 $D0 D1 ҲBD0 .z_ _%v %vj{ j{Juk Juk _ _ _, _͊m ͊m"d "d _ ͊ ͊Ѱ ѰҞB ,@ $ ҞBҲB cpu0/dec_ea/k_eahi_11_iv_0_5_796_i_0 F0 :C1 : :: cpu0/N_1938_i F1 DI1 cpu0/N_2103_1 f\F0 $@D1 A1 f\ @ @$@ cpu0/dec_ea/k_ealo_9_5_614_a4_0 JlF1 $:C1 Jl<9 <9A\ A\ : :$: cpu0/k_ealo_9_5_614 fF1 $DI1 f $ cpu0/N_878 P ?F1 ҲuB0 [A0 zC1 z0A0 ? Ҟu & &'< '< '
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B BE [\ E [\E L E LH PX E [\u A u AE ?l E ?lH BB B * < * < P A P A b b ]y ]y f= ]y fU H PX\ PX H BB\ BB f= f= fU fU cpu0/regs/ea/ea_reg_post_o_cry_8 2_ɂFCO 1_ɎFCI _ɂ_Ɏ cpu0/regs/ea_reg_post[9] 6 1ɗF0 q\ OC1 y B P^B1 K BD0 K B-D1 ɗ; ;c c4 C 4 CW A^ W A^H O cE EH H C C . C .- W A^H P| H P| L L . P^ H O\ O . P^ B P^ . B .- B- cpu0/regs/ea_reg_post[10] ; 1ɣF1 r 54C1 z Iz BB1 L XGC0 L X_C1 ɣ; ;4$ 4$o 'r o 'r
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f U U ;& ;&C Cxϧ xϧҞ֓ xϧҞ ;& ; ;"ϧ "ϧ . Ҟ֓Ҳ֓ ҞҲ . B cpu0/dec_o_dest_reg_addr[2] ` Q0 Ҳ֍B1 U ֍B1 ҲוD1
` ` pљ pљ ω ω ֍ ɡ ɡқ қҞ֍ қҞו Ҟ֍Ҳ֍ ֍ ֍ ҞוҲו cpu0/dec_o_dest_reg_addr[3] ] f Q0 ҲևA1 T@ hD0 U oA0 W ,^C0 Ҳ׃A1 r IzB1 f " "] ] N Nɕ[ ɕ[Ҟև ] , h NR R #A #A &Y &Y ,J ɕ[̭Ӈ ̭ӇҞ׃ ɕ[ܺk ܺk H H 6Tq 6Tq 8q 8q o 6Tq 9Ҙ 9Ҙ :ק :ק ?%) ?%) If ҞևҲև , h@ h o o ,J ,^ Ҟ׃Ҳ׃ If Iz cpu0/N_77 r f *F1 {$A1 $ fC0 ҲC1
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st t 8 8 , r *X #q #q 5ϛ 5ϛ @ @ If , 5@ 5 , r@ r If Iz cpu0/regs/ea/ea_reg_post_o_cry_2 5 FCO 4 FCI cpu0/regs/ea_reg_post[3]
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,k ,k,Ҙ ,Ҙ,{ ,O@O ,@ !$! ,{@{ , @ cpu0/regs/hflag_9 z G wOFX0 G BDI0 w . B . cpu0/regs_o_CCR[5] ; G Q0 G BC1 BB0 $B0 \B0 $A0 @ D1 Ҳ CA1 i$ ] C1 ! 7 7 = = . v~ v~ } } } v~ , B B> ; > ; Ҟ C B) [\ ) [\> UT > UT ^x ^x ]
. v~5 5$ $ H . B . B $ H\ $ , @ Ҟ CҲ C ] $ ] cpu0/regs/fflag_9 { : {OFX0 : BDI0 { ml . B ml . cpu0/regs/regs_o_CCR[6] | : Q0 : BC1 ,^oA0 $UA0 oA0 A0 s` s` = = . s` {w {w ' ' #G #G #Gm #Gm ,Jo #Gm \e \e o s` P Pvd vdsc sc vd\ \z] z]U . B ,Jo ,^o U$U o o cpu0/regs/eflag_11 } H F0 H DI0 cpu0/regs/eflag_RNO ~ gF0 H CE g L L } } cpu0/regs/cff_9 B , 6HOFX0 B ,^ 6~DI0 , 6H -* 5V ,J 6~ ,^ 6~ -* 5V ,J 6~ cpu0/regs/SU_s[0] G 5RF0 G 5DI0 5Rd 4 5 5 d 4 5 cpu0/regs/SU_s[1] G 5^F1 G 5DI1 5^p 4 5 5 p 4 5 cpu0/regs/SU_s[2] F 5F0 F 6 DI0 5 5& 6 6 5& 6 cpu0/regs/SU_s[3] F 5F1 F 6DI1 5 5& 6 6 5& 6 cpu0/regs/SU_s[4] E 6NF0 E 6~DI0 6N 5V 6~ 6~ 5V 6~ cpu0/regs/SU_s[5] E 6ZF1 E 6DI1 6Z 5V 6 6 5V 6 cpu0/regs/SU_s[6] D 4F0 D\ 5DI0 4 4 H 5\ 5 4H 5 cpu0/regs/SU_s[7] D 4F1 D\ 5
|
t F1 !\eD1 "\C1 y y o oE EHe yu
P u
PH He\e H\ cpu0/dec_regs/un1_postbyte0_3_4
|
DI1 4 4 H 5
|
u 'F1 !\;A0 "\B0 ' ' ' - x - xH - xH; H;\; H\ cpu0/dec_regs/N_408
|
\ 5
|
w F0 #Ҳ A0 Ҳ A1 f f t t Ҟ t Ҟ Ҟ Ҳ Ҟ Ҳ cpu0/un1_state_86_1_a3_0 > fF1 $,D0 f
, ,$, cpu0/dec_regs/N_541
|
4H 5
|
sF1 B1 s@ @9 9 cpu0/dec_regs/un1_state_50_4
|
cpu0/regs/SU_s[8] C 5RF0 C\ 5DI0 5R 4 H 5\ 5 4H 5 cpu0/regs/SU_s[9] C 5^F1 C\ 5DI1 5^ 4 H 5\ 5 4H 5 cpu0/regs/SU_s[10] B 5F0 B\ 6 DI0 5 5& H 6 \ 6 5&H 6 cpu0/regs/SU_s[11] B 5F1 B\ 6DI1 5 5& H 6\ 6 5&H 6 cpu0/regs/SU_s[12] A 6NF0 A\ 6~DI0 6N. 5V H 6~\ 6~ . 5VH 6~ cpu0/regs/SU_s[13] A 6ZF1 A\ 6DI1 6Z: 5V H 6\ 6 : 5VH 6 cpu0/regs/SU_s[14] @ 4F0 @ B 5DI0 4 p 4 . 5 B 5 p 4 . 5 cpu0/regs/SU_s[15] @ 4F1 @ B 5
|
F1 ҲeD1 Ӑ Ӑ̸I ̸IɭU ɭUҞe ҞeҲe cpu0/dec_regs/N_930
|
DI1 4 v 4 . 5
|
.F0 ^D1 . ^ ^^ cpu0/N_991_2 Z YF1
|
B 5
|
@D1 ?^D1 ҲB0 A0 Y& &*ܵ *ܵY Y, Yͮ{ ͮ{{ { ^ &Ҟ ,@ ^^ ҞҲ cpu0/dec_regs/state_cnst_i_0[5]
|
v 4 . 5
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?F1 zHA1 8 8A: A: fH fHzH cpu0/N_1552 W
|
cpu0/regs/SS_s[0] P (8F0 P (hDI0 (8d ' (h (h d ' (h cpu0/regs/SS_s[1] P (DF1 P (nDI1 (Dp ' (n (n p ' (n cpu0/regs/SS_s[2] O (F0 O (DI0 ( ( ( ( ( ( cpu0/regs/SS_s[3] O (F1 O (DI1 ( ( ( ( ( ( cpu0/regs/SS_s[4] N )4F0 N )dDI0 )4 (< )d )d (< )d cpu0/regs/SS_s[5] N )@F1 N )jDI1 )@ (< )j )j (< )j cpu0/regs/SS_s[6] M 'F0 M\ 'DI0 ' ' H '\ ' 'H ' cpu0/regs/SS_s[7] M 'F1 M\ 'DI1 ' ' H '\ ' 'H ' cpu0/regs/SS_s[8] L (8F0 L\ (hDI0 (8 ' H (h\ (h 'H (h cpu0/regs/SS_s[9] L (DF1 L\ (nDI1 (D ' H (n\ (n 'H (n cpu0/regs/SS_s[10] K (F0 K\ (DI0 ( ( H (\ ( ( H ( cpu0/regs/SS_s[11] K (F1 K\ (DI1 ( ( H (\ ( ( H ( cpu0/regs/SS_s[12] J )4F0 J\ )dDI0 )4. (< H )d\ )d . ( CE ? ,^׳CE @ IzCE A :CE L IzCE M bCE N ,^ CE O fCE P ,^CE Q CE R ,^CE S :CE T :CE U :|CE V IzCE 7 0 0 0ѭ ,J׳ ,J׳ ,^׳ 0y If If Iz 0y : : : 0 If If Iz 0 b b b 0ē ,J ,J ,^ 0 f f f 0 ,J ,J ,^ 0 0 ,J ,J ,^ 0y : : : 0y : : : 0 :| :| :| 0 If If Iz # ( ( 0 !u (қ (қ 0ѭ !u (g (g 0y # ( ( 0 !u (Ł (Ł 0ē 8Z # 8 !u
|
JyF0 ҲD1 $M0 $A1 B1 ҲLA1 ҲD1 A1 C0 D1 Jy $ 4+ 4+P+ P+Ҟ 4+ 4+U U 4+s s P+ɏ ɏҞL P+Ҟ d d *% *%d d *% ҞҲ $ ҞLҲL ҞҲ cpu0/dec_regs/un1_dest_reg44_1_i_0
|
8Z
|
(F0 Ҳ )C1 (f ( f ( Ҟ ) Ҟ )Ҳ ) cpu0/dec_regs/un1_state_40
|
8 G
|
F1 ҲB0 QҲA0 ҲMD0
|
+ G [ j + 2 P [ j 8 q} 2 P _ x 8 q} \A _ x X \A XJ . X PAR_CLOCKSIGNAL 2 sclk_id cpu0/regs/PC_9[1] M VOFX0 M DI0 V ~ ~ cpu0/regs/PC_9[2] N ,OFX0 N ,^IDI0 , , ,JI ,^I , ,JI cpu0/regs/PC_9[3] = OFX0 =
|
Ӑ ӐѤd ѤdҞ ӐѰd ѰdҞM Ӑ} }Ҟ ҞҲ ҞҲ ҞMҲM cpu0/dec_regs/N_413
|
DI0
|
Af (8F0 Ҳ )A1 A$ (B1 $ )B1 Ҳ `B0 f (8ĺ ' ĺ '
%D
%D ( ĺ '1 F 1 F Ҟ ` ĺ '] % ] %Ҟ ) ĺ '
%8
%8 ) Ҟ )Ҳ ) ($ ( )$ ) Ҟ `Ҳ ` cpu0/un1_state_39 {F0 JҲA1 B1
|
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{|0ֵ |0ֵq q ,k ,kҞ |0ֵ_ _؉ ؉ ҞҲ cpu0/dec_regs/k_write_exg9_0_0
|
|
&F1 ҲC1 ҲA1 &Ӑ " Ӑ " o oK KҞ KҞ ҞҲ ҞҲ cpu0/dec_regs/k_write_exg9
|
cpu0/regs/PC_9[4] O ZOFX0 O DI0 Z K K cpu0/regs/PC_9[5] > OFX0 > DI0
|
F1 Ҳ B0 r rɛ ɛҞ Ҟ Ҳ cpu0/un1_state_56 N UF1 UҲ7A0 ^ҲC1 rQ rQtU tUҞ7 rQ D DҞ Ҟ7Ҳ7 ҞҲ cpu0/N_977_2 ` fhF1 L{^7A0 M$BD0 M$ZD1 RB0 C0 D0 fh ] ]e~ e~vC vC{J7 B Z e~vy vy {J7{^7 B$B Z$Z cpu0/un1_state_29 Y zF0 A1 C0 z_ _ _ cpu0/N_1894_1 o {F0 BaC0 ByC1 aC0 lD0 {^oB1 {|k |k d da dy a |kq q l |kzo zo{Jo aa yy aa ll {Jo{^o cpu0/N_1745_2 K mʓF0 B[B0 Ҳ4A0
lsB1 lC1 mʓmɛ mɛvE vEu u[ uX Xɳ ɳɃl ɃlҞ4 mɛl mɛk~ k~ls [[ Ҟ4Ҳ4 lsls ll cpu0/dec_regs/N_880
|
-
|
F1 AB0 D1 8 8 A 8 AA cpu0/dec_regs/N_1032
|
- cpu0/regs/PC_9[6] P ,OFX0 P ,^$DI0 , -* ,J$ ,^$ -* ,J$ cpu0/regs/PC_9[7] Q OFX0 Q (DI0
|
F0 zZD1 L L/ /2 2fZ fZzZ cpu0/un1_state_12 {ʟF1 {^B0 cD0 {ʟ|<ɛ |<ɛzP~ zP~{J |<ɛ9 9c {J{^ cc cpu0/un1_state_16 \ F0 ҲXC1 H HҞX ҞXҲX cpu0/dec_regs/state57_1[0]
|
G ( (
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u *F1 C0 GD1 *8 8 o oK K KG GG cpu0/dec_regs/N_1952_tz
|
G ( cpu0/regs/PC_9[8] ? ,קOFX0 ? ,^DI0 ,ק -*ֵ ,J ,^ -*ֵ ,J cpu0/regs/PC_9[9] R ,OFX0 R ,^(DI0 , ,G ,J( ,^( ,G ,J( cpu0/regs/PC_9[10] @ IsOFX0 @ IzDI0 Is JF If Iz JF If cpu0/regs/PC_9[11] S ;.sOFX0 S :DI0 ;.s ; : : ; : cpu0/regs/PC_9[12] A ;.wOFX0 A :DI0 ;.w ;& : : ;& : cpu0/regs/PC_9[13] T ;.OFX0 T :+DI0 ;. ;Q :+ :+ ;Q :+ cpu0/regs/PC_9[14] U ;.pOFX0 U :DI0 ;.p ; : : ; : cpu0/regs/PC_9[15] V ItOFX0 V IzDI0 It Ie If Iz Ie If cpu0/regs/IY_10[0] 2 F0 2 BDI0 ֵ . B ֵ . cpu0/regs/IY_1_sqmuxa_2_1_0_RNISJTR1 XJMF0 2 B׳CE 3OCE 4mCE 5׳CE 6 SCE 7 IzmCE 8 BCE 9 IzַCE ! XJM X62 .׳ B׳ OO mm ׳׳ S S Ifm Izm . B Ifַ Izַ X62 \AI \AI _ _ 8 & 8 & U U .׳ UX{ X{ O ׳ U S U U U . X62 RD RD DRϡ DRϡ HrҘ HrҘ Ifַ UX Xm DRϡ 2 ) 2 ) D@ D@ H< H< Ifm cpu0/regs/IY_10[1] 2 F1 2 BDI1 ֵ . B ֵ . cpu0/regs/IY_10[2] 3IF0 3yDI0 I yy y cpu0/regs/IY_10[3] 3UF1 3DI1 U cpu0/regs/IY_10[4] 4gF0 4DI0 gL L cpu0/regs/IY_10[5] 4sF1 4DI1 s@ @ cpu0/regs/IY_10[6] 5F0 5DI0 ֵ ֵ cpu0/regs/IY_10[7] 5F1 5DI1 ֵ ֵ cpu0/regs/IY_10[8] 6 MF0 6 }DI0 M 2 } } 2 } cpu0/regs/IY_10[9] 6 YF1 6 DI1 Y & & cpu0/regs/IY_10[10] 7 IgF0 7 IzDI0 Ig IL If Iz IL If cpu0/regs/IY_10[11] 7 IsF1 7 IzDI1 Is I@ If Iz I@ If cpu0/regs/IY_10[12] 8 F0 8 BDI0 . B . cpu0/regs/IY_10[13] 8 F1 8 BDI1 . B . cpu0/regs/IY_10[14] 9 IֱF0 9 IzDI0 Iֱ JU If Iz JU If cpu0/regs/IY_10[15] 9 IֽF1 9 IzDI1 Iֽ J U If Iz J U If cpu0/regs/IX_10[0] * 3F0 * BcDI0 3 p .c Bc p .c cpu0/regs/IX_0_sqmuxa_1_1_RNIVGKH3 IʓF0 * B9CE +\CE ,\CE -\SCE . CE / IzCE 0 :mCE 1 Iz׳CE ! Iʓ JLɛ .9 B9 H\ H\ HS\S If Iz :m :m If׳ Iz׳ JLɛ S S :Ҙ :Ҙ .9 S'- '-W WH WHS JLɛ M M P$ P$ Dv Dv If Dv :m S 9 9 Se Se H0؉ H0؉ If׳ M )@ )@o o
|
JcF0 D1 Jc cpu0/dec_regs/N_376
|
,ܵ
|
Hf (F1 H$ (C0 f ( ( ( ( ($ ( cpu0/dec_regs/N_412
|
,ܵ '-W WH cpu0/regs/IX_10[1] * ?F1 * BiDI1 ? v .i Bi v .i cpu0/regs/IX_10[2] +F0 +\DI0 . H\ .H cpu0/regs/IX_10[3] +F1 +\DI1 : H\ :H cpu0/regs/IX_10[4] ,F0 ,\DI0 o H\ oH cpu0/regs/IX_10[5] ,F1 ,\DI1 o H\ oH cpu0/regs/IX_10[6] -MF0 -\}DI0 M2 H}\} 2H} cpu0/regs/IX_10[7] -YF1 -\DI1 Y& H\ &H cpu0/regs/IX_10[8] . F0 . DI0 cpu0/regs/IX_10[9] . F1 . DI1 cpu0/regs/IX_10[10] / IF0 / IzDI0 I J If Iz J If cpu0/regs/IX_10[11] / IF1 / IzDI1 I J If Iz J If cpu0/regs/IX_10[12]
0 ;.gF0 0 :DI0 ;.g ;L : : ;L : cpu0/regs/IX_10[13]
0 ;.sF1 0 :DI1 ;.s ; @ : : ; @ : cpu0/regs/IX_10[14]
1 IF0 1 IzDI0 I JLֵ If Iz JLֵ If cpu0/regs/IX_10[15]
1 IF1 1 IzDI1 I JXֵ If Iz JXֵ If cpu0/regs/DP_7[0]
; ,ɗF0 ; ,^DI0 ,ɗ ,; ,J ,^ ,; ,J cpu0/regs/DP_1_sqmuxa_1_1_0_RNIFF9C1
|
)4F0 @ )C1 Ҳ (tA0 )4 (< (<, ) (< % %Ҟ (t , )@ ) Ҟ (tҲ (t cpu0/dec_regs/N_76
|
IF0 ; ,^ɝCE <\CE I B5CE J BCE KCE I I ,Jɝ ,^ɝ H\ .5 B5 . B I 5 5 +V~ +V~ ,Jɝ 5 2 2 '6ϡ '6ϡ
|
'F0 Ҳ (B1 $ (B1 ' ' '] %z ] %z ( '̭ % ̭ %Ҟ ( Ҟ (Ҳ ( ($ ( cpu0/dec_regs/N_348
|
q
|
AF1 5:D1 6A1 A A A 4 4 2X 2X 5: 2X 6 5: 5: 6 6 cpu0/un1_state_50 FUF1 ҲQA0 FҲC0 @cD0 Ur rҞ r _ _ / /,c rɛm ɛmқƣ қƣҞQ ҞQҲQ ҞҲ ,c@c cpu0/dec_regs/N_1577
|
qK K{] {]E EH
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.F0 ZD1 . h< h
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q .Ҙ .Ҙ .5 '6ϡ # # m m :d :d . KK K6 6 cpu0/regs/DP_7[1]
I /F0 I B_DI0 / օ ._ B_ օ ._ cpu0/regs_o_dp[1] $ I 5Q0 \D1 ҲC1 \D1 ҲmA1
u$A0 j X B0 5 օ օ H ɛS ɛSқƩ қƩҞ H ɛSҞm * * bk bk u * NS NS O! O! O!* O!* W H\ ҞҲ H\ ҞmҲm u u$ W X cpu0/regs/DP_7[2]
; ,ɣF1 ; ,^DI1 ,ɣ - ; ,J ,^ - ; ,J cpu0/regs/DP_7[3]
I ;F1 I BeDI1 ; օ .e Be օ .e cpu0/regs_o_dp[3] & I AQ1 ,^KD1 A1 5A1 @-D1 fB1 ,^A1 A օ օ {) {) 'k 'k #Au #Au ,JK օ W W 5 օ ~ ~^j ^j_ _,- 9. 9. ] ] f 9. 3! 3! ' ' ,J ,JK ,^K 55 ,-@- f f ,J ,^ cpu0/regs/DP_7[4]
|
.F1 zNB1 . fN fNzN cpu0/dec_regs/state_7_sqmuxa_1_8
|
|
C F1 C0
C1 A0 C@GC0 $C1 B1 Ҳ lD0 @B0 A Aɡ ɡ Ҟ l 0 0ϛ ϛ ϛ
,G 0ͮϕ ͮϕ ) ),
,G@G $ Ҟ lҲ l ,@ cpu0/dec_regs/path_left_addr_cnst_i_0[2]
|
[K [K .? [KX X< <1 1Ҟ Xu1 u1H?
|
CF0 @ ZA0 L L , Z , Z@ Z cpu0/dec_regs/N_415
|
9ތ 9ތ ] ] pϛ pϛ tҘ tҘ u 9ތ 3 3 Dd Dd If X1 1<ܯ <ܯҞ+ .? B? ҞҲ H?\? Ҟ+Ҳ+ u u$ If Iz cpu0/regs/DP_7[6]
J F1 J BDI1 ! . B ! . cpu0/regs/DP_7[7]
KF0 K/DI0 d // d/ cpu0/regs_o_dp[7] % KQ0 ,^+C1 Ҳ
C1 ,^!B1 Ҳ֙D1 > XC1 fmA1 j j 60 60 #_ #_ ,J+ j <ϕ <ϕҞ
#_ ,G ,G ,J! <ϕz؉ z؉Ҟ֙ Bj Bj RM RM O!D O!D W RM ] ] `a `a fm ,J+ ,^+ Ҟ
Ҳ
,J! ,^! Ҟ֙Ҳ֙ W X fm fm cpu0/regs/ACCB_9[0]
& F0 & BDI0 . B . cpu0/regs/ACCB_0_sqmuxa_1_RNIIOBV
;.F0 & BCE '\CE (fCE )\|CE ;. ; . B H\ ff H|\| ; 4 4 '~ '~
|
f F1 ҲC1 $ nA1 f ] ]
t
tҞ n ҞҲ n$ n cpu0/un1_state_35_3 JF0 BsB1 D1 Jk ko os kD D g g ss cpu0/dec_regs/un1_state_76_1
|
b
|
.F0 ևA1 . @ϧ @ϧ؉ ؉և ևև cpu0/k_pp_regs_12_sqmuxa S m3F0 _{^KD1 m3l lb{ b{Ua) Ua)g gz& z&{JK {JK{^K cpu0/dec_regs/state_cnst_i_4[5]
|
b . . .
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F0 zTC1 L LfT fTzT cpu0/dec_regs/path_left_addr13
|
b f
|
> F1 A0 )|C0 (C0 y y y )| ( )| )| ( ( cpu0/dec_regs/un1_path_left_addr12
|
bc cE EH|
|
F0 fC0 C1 ( D1 ( f f f ( ( cpu0/next_state10 F1 A0 A1 {C0 9A1 \A0 C0 !zC0
B0 : : ܅ ܅ ܅ ܅m me e؉ ؉{ G G9 e eϕ ϕ e]u ]uf ϕ
{{ 99 fz
cpu0/un1_state_33 B .F0 D0 A0 A1 !zB1
. I Im m I ߲ ߲ %C %Cf fz cpu0/N_36
{JF1 ֍B1 :zB1 ; :| D1 < ,^D1 = :zC1 > ,^|C1 ? ,^{
|
bT TH cpu0/regs/ACCB_9[1]
& F1 & BDI1 . B . cpu0/regs/ACCB_9[2]
'F0 '\DI0 H\ H cpu0/regs/ACCB_9[3]
'F1 '\DI1 H\ H cpu0/regs/ACCB_9[4]
(`F0 (DI0 `E E cpu0/regs/ACCB_9[5]
(lF1 (DI1 l9 9 cpu0/regs/ACCB_9[6]
" )vF0 )\DI0 v H\ H cpu0/regs/ACCB_9[7]
$ )F1 )\DI1 H\ H cpu0/regs/ACCA_RNO[0]
& " zF0 " DI0 z _ _ cpu0/regs/un1_right_reg_4_RNIM2L32
' XJ}F0 " CE # CE $ CE % |CE XJ} X! | | X! )& )&
|
C1 @ :{|A1 A ,^B1 D$aC0 $qB0 "$]C0 ) Jh h ! ! a hAB ABn nL} L}֍ ABf fn ngL gL s| s|z n
h[7
h[7 1l 1l :| s| *uk *uk #Y #Y ,J 1l :z 1l 'Zs 'Zs ,J| 'Zs ,J{
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tO
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1l :{| #Y ,J nVσ Vσq ] ֍֍ zz :| :| ,J ,^ :z :z ,J| ,^| ,J{
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tO g g |
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,^{
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tO d d d cpu0/regs/ACCA_RNO[1]
) " F1 " DI1 S S cpu0/regs/ACCA_RNO[2]
+ # yF0 # DI0 y cpu0/regs/ACCA_RNO[3]
- # F1 # DI1 cpu0/regs/ACCA_RNO[4]
/ $ }F0 $ DI0 } f! f! cpu0/regs/ACCA_RNO[5]
1 $ F1 $ DI1 r! r! cpu0/regs/ACCA_RNO[6]
3 % vF0 % DI0 v cpu0/regs/ACCA_RNO[7]
5 % F1 % DI1 cpu0/regs/SU_16[0]
7 ;. 5OFX0 ` : 5D0 ;. 5 ; 5& ; 5& 9 7* 9 7* : 5 : 5 : 5 cpu0/regs/SU_205_i1_mux
8 ` ;. 5RF0 G 5C0 ;. 5R ; 4 5 5 ; 4 r / r / .< .< 5 cpu0/regs/SU_16[1]
: a 5^F1 a B 5C0 5^ 4 4 . 5 . 5 B 5 cpu0/regs/SU_206_i1_mux
; a 5RF0 G 5C1 5R 4 5 5 4| .* | .* 19 19 5 cpu0/regs/SU_16[2]
= b CtF1 b CC0 Ct Bp Bp C C C cpu0/regs/SU_207_i1_mux
> b ChF0 F 6C0 Ch Bp 6 6 Bp ? ? 4 4 .B .B 6 cpu0/regs/SU_16[3]
@ c &F1 c B bC0 & " " . b . b B b cpu0/regs/SU_208_i1_mux
A c F0 F 60C1 " 60 60 " ~ o ~ o D 5 D 54 .B 4 .B 60 cpu0/regs/SU_16[4]
B d 6ZF1 d@ 6C0 6Z 5V 5V, 6 , 6@ 6 cpu0/regs/SU_209_i1_mux
C d 6NF0 E 6C0 6N 5V 6 6 5Vl . l . 7* 7* 6 cpu0/regs/SU_16[5]
D e OF1 e OVD0 O N N LV LV OV OV OV cpu0/regs/SU_210_i1_mux
E e OF0 E 6C1 O N 6 6 N G G 3 3 6 cpu0/regs/SU_16[6]
G f 5^F1 f@ 5C0 5^ 4 4, 5 , 5@ 5 cpu0/regs/SU_211_i1_mux
H f 5RF0 D\ 5 C0 5R 4 H 5 \ 5 4y 2 y 2F .< F .
|
:{| :{| ,J ,^ a$a q$q ]$] cpu0/dec_regs/next_state_4_sqmuxa
|
:
|
f/F0 Ҳ'C1 ցD0 ҲA0 f/օ օ]) ])ɉQ ɉQҞ' օ M Mց ɉQҞ Ҟ'Ҳ' ցց ҞҲ cpu0/un1_state_35 [ {!F1 ֙D1 lB1 n{^%B1 {!| k | kud udϧ ϧ^w ^w؉ ؉֙ udrq rq{J% rqgܯ gܯc clӷ lӷl ֙֙ ll {J%{^% cpu0/un1_state_23_1_RNIAOS95 J?F1 iDI1 J?< ii < i cpu0/dec_regs/k_memlo_1_sqmuxa
|
: '< '< ( cpu0/regs/SS_16[2]
Q j BF1 j@ C2C0 B B@ B@, C2 , C2@ C2 cpu0/regs/SS_223_i1_mux
R j BF0 O (C0 B B@ ( ( B@y ? y ? 42 42 ( cpu0/regs/SS_16[3]
T k F1 k B0 y y cpu0/regs/SS_224_i1_mux
U k F0 O )C1 ) ) ' ' %8 %8 ) cpu0/regs/SS_16[4]
V l F1 l C0 cpu0/regs/SS_225_i1_mux
W l F0 N )|C0 )| )| )| cpu0/regs/SS_16[5]
X m BxF1 m B BC0 Bx B B . B . B B B cpu0/regs/SS_226_i1_mux
Y m BlF0 N )C1 Bl B ) ) B ~ : ~ : [ ' [ 'X ! X ! ) cpu0/regs/SS_16[6]
[ n *F1 n@ fC0 * , f , f@ f cpu0/regs/SS_227_i1_mux
\ n F0 M\ (C0 H (\ ( F F !. !.H ( cpu0/regs/SS_16[7]
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I@ I1 I1 C C sPuA sPuA l l u, l , , @ u, u$, cpu0/regs/N_432 XJOFX0 @B1 N u$&C0 XJ XB XB a a l+ l+ u& a ~ ~ G G , , @ u& u$& cpu0/datamux_o_alu_in_left_path_data[13] % VOFX0 @DI0 V , @ , cpu0/un1_regs_o_pc[9] XJzF0 z@D0 XJz XzN XzN RJr RJr P P ) )~% ~%, ,@ cpu0/k_eahi[3] Q1 # X B0 cD1 v v 9 9 SL SL W vu\ u\` `y y W X cpu0/regs/regs_o_dp[3] V # XJF1 C1 u$D1 @D1 u$1D1 # X"C0 %\"C0 XJ X X P P bXm bXm u1 bXm u X W" X RJ/ RJ/ )C )C3d 3dH" X K K |6 |6 z% z% z% ƣ ƣ ʍ ʍ , u u$ , @ u1 u$1 W" X" H"\" cpu0/k_eahi[5] rQ1 $ B0 2@8B1 rw3 w3yV yV w3; ;,8 ,8@8 cpu0/regs/regs_o_dp[5] = $ hF1 IzC1 :D1 ,^2A1 Iz C1 $ C0 %\:C1 h " \ " \ ,J2 " \ #4 #4 5 5 If 5 If {& {&X XH: " V " V 6 6 : If Iz : : ,J2 ,^2 If Iz H:\: cpu0/k_eahi[6] bQ0 0 ,^A1 1\D0 b Q Q
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A1 y B PdC1 z Iz BA1 { B xB1 |\ BTD1 }\ ~C1 ~ B iC1 B C>A1 5 , 4 , 4 : 6r : 6r , 4 5 .< 5 .< 9 19 9 19 : 6r , 4 " 2 " 2 / / A A C> /7 A 7 A͜ ;V ͜ ;V, CJ / ' ' $ $ ' AF ;V F ;V . B '< < , ~ AF Hp F Hp . Pd , 4 &j : &j : 6B ;2 6B ;2 If B F ;VZ >S Z >SH BT F Hp U [ U [ . i F ;V : >S : >S . C> 'F F H F 4 4 . x F H ~ F U 'r U 'r . )
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/j jc cH ,J ,^ H\ cpu0/regs/regs_o_dp[6] s / lF1 0 ,^ C1 IzA1 XD1 fC1 fA1 / BB0 l v9 v9 / / 9[ 9[ ]md ]md S S W / nr nr + + ,J 9[ 3 3 dH dH ]s/ ]s/ f ]s/ f v9 . S Hr Hr If ,J ,^ If Iz W X f f f f . B cpu0/k_eahi[0] Q0 % XD0 4\D0 K K S S W \ \r rH W X H\ cpu0/regs/regs_o_dp[0] ) % XJhF1 (D0 u$A1 u$D1 u$A1 @D1 % XC0 XJh X X N N b~ b~ u X RD/ RD/ )| )| < <( b~ l l u b~ t" t" u RD/ z< z< @ X W (( u u$ u u$ u u$ @ @ W X cpu0/N_2161 F1 gD0 D1 @C0 @
C1 A0 A1 }D0 B1 qM0 @D0 @M0 @SM0 @WM0 @ʷM0 @M0 WM0 Iz5A1 @C0 @AB0 @SA1 A0 A1 A0 A1 X[C1 H o q q , @ ,S @S ,W @W ,ʷ @ʷ , @ W W o ܝ ܝ յ յ g յ o Aյ Aյ ) ) , ) ,
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5F1 : 6B0 B 6C0 C,B0 ]A0 B \jC0 : BB0 B BHB1 C B A1 D@ VA0 E B CB1 F@ A1 G VA0 6A0 6A1 \C0 PA1 - 5 5& 5& . 6 5& { 2 { 2 6 5& H : H : . C 5& + & + & . { 2 A A C, A P H :| ;D | ;D BH H : U N U N . \j { 2 ' .$ ' .$ : 6 + & V A 'l ;J 'l ;J : B E E H , , V | ;D N N ] { 2 6 : 6 : 6 . 6 B 6 C, C, ] ] . \j B \j : B : B BH BH . B , V@ V . C B C , @ V V 6 6 6 6 H\ P P cpu0/regs/SU_3_sqmuxa
, 5^F1 : 5M0 a B 5B1 b CA1 c B nA1 d@ 6D1 e ObB1 f@ 5B1 g xB1 p B 6B1 q\ OD1 r 5.B1 s\ nA1 t\ PjD1 u 6*B1 v B OC1 w : BBA1 3 , 5^ - 4 : 5 : 5 - 4 . . . 5 . . . A^ A^ C . C '< C '< . n . . 6H . 6H 2 2 - -, 6 A^ Lb Lb Ob - 7* 7*, 5 . ] '< ] '< x . . 6 2K A: K A:H O . 5. ] 'S @ >S . B . B B B cpu0/regs/N_284
E CtF1 e OnD1 Ct Bp Bp N G N G H. H. On On On cpu0/regs/N_670
F1 4A1 cpu0/regs/N_634
[ )@F1 ,\%B1 )@ (< (< H - H - Y E Y E|ܣ |ܣH% H%\% cpu0/regs/N_249
F F0 n@ D1 n n ; ; , , @ cpu0/regs/N_285
F F1 f@ 5D1 t y t yL L # 3 # 3, 5 , 5@ 5 cpu0/regs/N_635
IF0 -\A0 I JL JL ܅ ܅H H\ cpu0/regs/N_671
Z F1 5D0 y y ;& ;& cpu0/regs/N_286
G F0 g D1 " " cpu0/regs/N_250
G &F1 o\ D1 & " " H H \ cpu0/regs/N_672
IֱF0 5D1 ֱdU dUӽ ӽ cpu0/regs/N_636
IֽF1 -\A1 ֽpU pU ܑ ܑH H\ cpu0/regs/left_1[8] BF1 ? ,^D0 ,^ID0 C2C0 J D0 J D1 CD0 B B@ B@ DD DD C B@ C2 B@ G G c c / / '+ '+ ,JI c c c '_ '_ ,J ,J ,^ ,JI ,^I C2 C2 C C cpu0/regs/right[8] V F1 . D0 6 C0 ? ,^B0 ,^[C1 C8D0 CC0 Te Te a a DP DP a 4 a 4 ;b ;b C a 1 1 W W n ; n ; C8 DP U U U Te s s ,J[ 1 & & #S #S ,J ,J ,^ ,J[ ,^[ C8 C8 C C cpu0/N_1282 XJֽF1 ? ,^A1 XJֽ XU XU M M 6xe 6xe ,J ,J ,^ cpu0/regs/left_1[9] ]F1 R ,^FD0 ,^D0 ]C0 K BC0 K B'C1 B kD0 ] \ \ h h b\ \ ] b\ [ [ )[ )[ Y Y .' Y . Y ,J )[ J J #G #G ,JF b\ . k ,JF ,^F ,J ,^ ] ] . B .' B' . k B k cpu0/regs/right[9] U}F0 . -D1 6 C1 R ,^4A0 ,^D1 ]D0 B jA0 },! ,! 5 5P UN P UNl UN l UN ] A A - ' ' ,J4 ' #A
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,J ,! TK TK D D (w (w = [ = [ . j - - ,J4 ,^4 ,J ,^ ] ] . j B j cpu0/N_1283 ;.RF1 R ,^XC1 ;.R ; ; 'Z 'Z #q #q &Y &Y ,JX ,JX ,^X cpu0/regs/left_1[10] I BF1 @ IzB0 ,^MD0 Iz C2C0 L X;A0 L XSA1 6C0 I B J: B@ J: B@ If C2 J: B@ < < 3 3 6 J: B@ B@ G B@ G S S N N WS N W; 3 l l ( ( ,JM B@ G @o @o @ow @ow If If Iz ,JM ,^M If C2 Iz C2 W; X; WS XS 6 6 cpu0/regs/right[10]
UF1 / Iz3D0 7 IzC0 @ IzD0 ,^YB1 Iz C8D0 6B0 8! 8!n
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@B0 &$@C0 f @ i i, ,@ @$@ cpu0/regs/ea/un1_k_p2_valid6_1_0 @ 'fvF0 &$FD0 fv F F$F cpu0/regs/ea/N_72 B .F0 -_C1 \A1 . __ .@ @ _ .T TH H\ cpu0/regs/ea/N_238 C OFX0 -YB1 \C1 % %d dY ds s QC QCH YY H\ cpu0/regs/ea/un1_eamem_addr63_3_1 D sF1 &\D0 &\D1 '\ID0 '\aD1 (\D1 )\MD0 *D0 *D1 +ID0 ,D1 -eD1 \D1 BD1 ' s@ H\ H\ HI\I Ha\a H\ HM\M II ee @6 6@ @P P+ @Pu Pu Pu~ ~ e K K ~ I +Ha +H +HM +HI +H +H +9 9H + . H\ . B cpu0/k_p2_valid6 7 'fF1 @D0 '$C0 f ] ]/ /, ,@ $ cpu0/regs/ea/k_p2_valid8_0 G f`F0 '$B0 f`RE RECV CV
$ cpu0/regs/ea/k_p2_valid8_4 H $fzF0 '$A0 fzR_ R_ $ cpu0/regs_o_dp[7] F0 C1 fA1 fC1 @uC1 mA1 B
C1 ֵ ֵ 9 9 ] ] f x x ] ] ] f 9 l l /K /K ,u /K W W m ֵ .
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cpu0/N_2040_i hF1 DI1 h cpu0/regs/ea/k_eahi_11_iv_0_0_901_i_0 P / `F0 C0 ` pE pE & & cpu0/N_2023_i \F0 DI0 \ cpu0/regs/ea/k_eahi_11_iv_0_1_880_i_0 S %F1 @D1 : : z z, ,@ cpu0/N_2006_i lF1 @DI1 lt9 ,@ t9, cpu0/regs/ea/k_eahi_11_iv_0_2_859_i_0 U lF1 @A0 l9 9/ /ܨ ܨ/ /, ,@ cpu0/N_1989_i `F0 @DI0 `nE ,@ nE, cpu0/regs/ea/k_eahi_11_iv_0_3_838_i_0 W %F0 DD1 . .~ ~D DD cpu0/N_1972_i F1 DI1 p p cpu0/regs_o_dp[2]
;.F0 ,D0 Iz8B1 :2A1 :@D1 :RB1 :[C1 ;. ; ; 3 3 ~ ~H H , 3 E< E< @Kl @Kl Ic Ic If8 @Kl 6z 6z :@ 3 1 1 : : :R ; :[ 3 1l 1l :2 ,, If8 Iz8 :2 :2 :@ :@ :R :R :[ :[ cpu0/N_1955_i F0 DI0 d d cpu0/N_1921_i F0
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5 5T 0: T 0: .0 .0 6 .0 6 . 6 . @Q @ @Q @ If C8 6 . 1 & 1 & 3 3 E< E< If3 .0 #k '` #k '` %N %N 5 5 If 3 1 1 E< E< If 8!f> f> O O ,JY If3 Iz3 If Iz If Iz ,JY ,^Y If C8 Iz C8 6 6 cpu0/regs/left_1[11] , F1 S :A0 Z ;A0 ,^ D0 M fD0 M fD1 \D0 , , y , y " ` " ` , y &Y &Y ,J ' ' D D b4 b4 f b4 f " ` l l 9 9 ;
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DI0
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H 9 '7 '7 : : : ; ; ,J ,^ f f f f H\ cpu0/regs/right[11] TF0 / IzKD1 7 IzD1 S :C0 ,^ C0 \A0 \A1 JQ JQD Dlb lb 1 1 a
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b ,J 1 H H 1 & & 6B 6B @o @o IfK 6B 1 1 D D HB HB If lb &C &C 5s 5s : IfK IzK If Iz : : ,J ,^ H\ H\ cpu0/N_1285 x ufYF1 S :A1 ufY uX& uX& n; n; anm anm D= D= : : : cpu0/regs/left_1[12] PF1 A :A0 CC0 PLC0 N f7A0 N fOA1 PB1 P OZ OZ PL OZ P OZ G J G J m )a m )a a a fO a f7 OZ )a )a K K C K 'C 'C : : : C C PL PL f7 f7 fO fO P P cpu0/regs/right[12] TF1 0 :A0 8 B#B0 A :B0 aD1 PRD0 PD1 VQ VQl l 5 5 N N n H4 n H4 P n H4 PR 9 9 1 1 : 7 7 .# l n+ n+ 5[ 5[ : n+ a : : .# B# : : a a PR PR P P cpu0/regs/N_1286 ;.!F1 A :D1 ;.! ;k ;k 19 19 : : : cpu0/regs/left_1[13] *F1 T :7A0 ,^D0 fC0 O IzD0 O IzD1 6D1 * r r 4 4 6 r f r G G @{
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If G Bj Bj 5{ 5{ #w #w ,J 5{ 2 2 :7 :7 :7 ,J ,^ f f If Iz If Iz 6 6 cpu0/regs/right[13] SyF0 0 :D1 8 B5A1 T :ID0 ,^A1 `B0 6C1 yh h
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cpu0/regs/ea/state_cnst_0_6[1] ` R\F0 DD1 \J JA A D DD cpu0/regs/ea/ea_reg[15] a } XJɑOFX0 . IzA0 |\aC0 XJɑ XB XB \A \A 8 @ 8 @X{ X{Ha \A _n$ _n$ 8 8 6f 6f If If Iz Ha\a cpu0/regs_o_pc[15] OFX0 I ;A0 fzhA0 D1 @aD1 |\gD0 |\D1 `k `k z] z] ; `k |x! |x! psj psj fzh z] }S }S z] C C U U ,a psj 8"u) 8"u) 1 1 ? ?Hg ?H ; ; fzh fzh ,a @a Hg\g H\ cpu0/regs/ea/N_87 c |F0 % B;A0 7] 7] .; .; B; cpu0/regs/ea/ea_reg[14] d ~ XJ֫OFX0 / :5A1 } IzA0 XJ֫ XB XB M M @ȿ @ȿ If M 60} 60} 1 1 :5 :5 :5 If Iz cpu0/regs/ea/N_86 f } IyF0 &\C1 Iy JL H\ JL 7 7Hd HdH cpu0/regs/ea/ea_reg[13] g ;.OFX0 / : A0 ~ 7A0 ;. ;Q ;Q '= '= 7 ;Q 4 4 1 1 1 1 : : : 7 7 cpu0/regs_o_pc[13] ;.sOFX0 X{B0 X*D1 IzC1 w C1 J u$D1 ~ CC0 ;.s ; ; 3 3 DfJ DfJ NyT NyT W{ NyT W* DfJ @]yT @]yT If 3 ' ' ; d d 3 3 u ' ' ' C W{ X{ W* X* If Iz u u$ C C cpu0/regs/ea/N_85 i ~ F0 &\C0 Q H\ Q
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X X ` 3 3 6 ' ' 1 1 :
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SZJ ZJE Eh hH cpu0/regs/ea/ea_reg[12] j ;.OFX0 0 :A1 BD0
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C C .5 1 1? 1? 1 1 :I hr r J7 J7 ,J : : .5 B5 :I :I ,J ,^ ` ` 6 6 cpu0/regs/N_1287 ! ;.F0 T :OA1 ;. ;k ;k 1] 1] 4S 4S :O :O :O cpu0/regs/left_1[14] $ \.F1 U :A0 ,^C0 B \dB0 P IzC0 P Iz+C1 B k D1 \. v [ v [ U h U h . k v [ . \d v [ 9 W 9 W 4 6 4 6 4 4 D@ D@ If+ D@ If 4 2 2 '6 '6 ,J 2 : : : ,J ,^ . \d B \d If Iz If+ Iz+ . k B k cpu0/regs/right[14] % SF1 1 IzB0 9 IzA0 U :D0 ,^D1 B \pD0 B kC1 t t r q r q 5 5 UB UB UB UB . \p r q 5 5
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h . k r8 r8 +m +m ! ! n n ,J n 6 6 : r8 9 8 9 8 S S @cm @cm If 9 8 Sg Sg @K% @K% If If Iz If Iz : : ,J ,^ . \p B \p . k B k cpu0/N_1288 ;.F1 U :C1 ;. ; ; : : : : : cpu0/regs/left_1[15] * ;. BxF1 V IzC0 6B0 : BC0 Q f{C0 Q f֓C1 CD1 ;. Bx ; B ; B 0 ? 0 ? ; ; C ; B : B ; B 3 M 3 M d d ] ] f֓ ] f{ d _ _ S S If 3 M 3 3 ' ' 6 If Iz 6 6 : B : B f{ f{ f֓ f֓ C C cpu0/regs/right[15] + RfF0 1 IzD1 9 Iz B1 V IzD0 ZD1 : BD0 CB1 fR Re e | | 4 4 C '$ '$ 2 | 2 | 1 4 1 4 : B G G @! @! If @! If e Ge Ge @ @ If e Z If Iz If Iz If Iz Z Z : B : B C C cpu0/N_1289 XJF1 V IzC1 XJ X X M@ M@ If If Iz cpu0/regs/N_673 0 J IF0 6 D0 I cpu0/regs/N_637 1 J UF1 . C0 U cpu0/regs/N_287 2 BF0 p B 6C1 B B@ B@ { ? { ? 3 3 . 6 . 6 B 6 cpu0/regs/N_251 4 ChF0 x B )C1 Ch Bp Bp : :
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;. ; ; 0 0 $ $ . ; 4 4 1 1 : : : . B cpu0/regs/ea/N_84 l vF0 '\[C1 v H[\[ W WQ] Q]H[ cpu0/regs/ea/ea_reg[11] m )OFX0 0 :A0 BFD0 ) ~օ ~օ '$ '$ 2 C 2 C : ~օ ~ ~
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. 7 ' 7 ' . ) . ) B ) cpu0/regs/N_288 5 ]F0 q\ OB1 ] \ \ Z Z N NH O H O\ O cpu0/regs/N_252 7 jF0 y B PjD1 j i i [8 [8 . Pj . Pj B Pj cpu0/regs/N_674 8 K F0 6 D1 {y {y cpu0/regs/N_638 9 K F1 . A1 {I {I cpu0/regs/N_253 : I BF0 z Iz BC1 I B J. B@ J. B@ If B If B Iz B cpu0/regs/N_289 < 6NF0 r 5:D1 6N 5V 5V 19 19 5: 5: 5: cpu0/regs/N_675 = L XJF0 7 IzD0 XJ X X MG MG @
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If If Iz cpu0/regs/N_639 > L XJ F1 / Iz!A0 XJ X X MA MA @W} @W} If! If! Iz! cpu0/regs/N_254 ? , F0 { B ~C1 , , , . ~ . ~ B ~ cpu0/regs/N_290 A }F0 s\ D1 } b b o X o XH H \ cpu0/regs/N_676 B M fF0 7 IzC1 f ff ff ]U ]U R R If If Iz cpu0/regs/N_640 C M fF1 / IzEC1 f fZ fZ ]1 ]1 S S IfE IfE IzE cpu0/regs/N_255 D PF0 |\ BNC1 P OZ OZ G G
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.F : : .F BF cpu0/regs_o_pc[11] XJOFX0 X{jB0 A1 @D1 v B B1 K @A0 B@C0 XJ Xk Xk RD RD Q Q Oy Oy W{j Oy D D '~ '~
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;\H BN H BN\ BN cpu0/regs/N_291 F PF1 t\ PdC1 P O O { L { LX Hj X HjH Pd H Pd\ Pd cpu0/regs/N_677 G N fF0 8 B)C0 f gh gh _2 _2 8( 8(
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- .) .) B) cpu0/regs/N_641 H N fF1 0 :B0 f gt gt 8(T 8(T 1Y 1Y : : : cpu0/regs/N_256 I F0 }\ D1 f f
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b . D rm rm = = .@ Xk R R H H z/ z/ z/ E E , E ;M ;M , W{j X{j , @ . B , @ .@ B@ cpu0/regs/ea/N_83 o F0 '\CC0 HC\C : :K1 K1HC cpu0/regs/ea/ea_reg[10] p OFX0 1 :9A1 BXC1 { { O O .X 'lܩ 'lܩ 1 1 : : :9 :9 :9 .X BX cpu0/regs_o_pc[10] ufʍOFX0 XzA1 A1 A1 i D0 { A1 BLA1 ufʍ uɛ uɛ m m FM FM
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b Z Z H H \ cpu0/regs/N_292 K 6ZF1 u 66D1 6Z 5V 5V 66 66 66 cpu0/regs/N_678 L O IF0 8 BGD1 I If If " " gU gU .G .G BG cpu0/regs/N_642 M O IF1 0 :B1 I IZ IZ ?%A ?%A 1} 1} : : : cpu0/regs/N_293 N \"F0 v B OB1 \" p \ p \ g N g N . O . O B O cpu0/regs/N_257 P jF1 ~ B iD1 j i i @ e @ e . i . i B i cpu0/regs/N_643 Q P IF0 1 IzA0 I Jo Jo @ @ If If Iz cpu0/regs/N_679 R P IF1 9 IzC0 I J o J o @{յ @{յ If If Iz cpu0/regs/N_294 S ;. BlF0 w : BTD1 ;. Bl ; B ; B : ?r : ?r : BT : BT : BT cpu0/regs/N_258 U CtF1 B CJC1 Ct Bp Bp { ? { ? . CJ . CJ B CJ cpu0/regs/N_680 V Q f3F0 9 IzC1 f3 f f Rϡ Rϡ If If Iz cpu0/regs/N_644 W Q f?F1 1 Iz
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cpu0/regs/ACCA_9_iv_159_0_0 X F0 % C1 cpu0/regs/un1_write_reg_addr_2 Y
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xCE xCE z _ d x d x _ p p d p d cpu0/regs/state_cnst_0_a2_i_1[2] ,F1 aD1 , ! ! , , a a a cpu0/k_p2_valid_3 yF0 DI0 y cpu0/regs/IY_1_sqmuxa_2_1_0 XJF0 XD0 XJ X X W߲ W߲ W W X cpu0/regs/un1_right_reg_4 Q UF1 XA0 U = = om om Rm Rm W d W d W W X cpu0/regs/ACCB46 ;. F1 Z _C1 :AB0
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b N N PF PF PF cpu0/alu/alu16/a16/N_2321 = p , (DF1 PRD0 , (D - ' - ' %6 O %6 O HR HR0 H" 0 H" PR PR PR cpu0/alu/alu16/arith_q[10] PF0 PdC1 P OZ OZ Pd Pd Pd cpu0/alu/alu16/a16/N_2308 ? x j8F0 ,^ ]B0 j8 i i b b & b & b #S [ #S [ ,J ] ,J ] ,^ ] cpu0/alu/alu16/a16/N_2324 @ o , (F0 ,^ ]D0 , ( - ( - ( #M 4 #M 4 #} N #} N ,J ] ,J ] ,^ ] cpu0/alu/alu16/arith_q[11] , ]F0 ,^ ]C1 , ] -0 \ -0 \ ,J ] ,J ] ,^ ] cpu0/alu/alu16/a16/N_2323 B x jDF1 B jtA0 jD i i bt bt . jt . jt B jt cpu0/alu/alu16/a16/N_2325 C o , (F1 B jD0 , ( - ( - ( #A 3 #A 3 % i % i bb bb . j . j B j cpu0/alu/alu16/arith_q[12] j8F0 B jC1 j8 i i . j . j B j cpu0/alu/alu16/a16/N_2309 E w jF0 \A0 j i ij C j C H H\ cpu0/alu/alu16/a16/N_2326 F n , )4F0 \D0 , )4 -0 (< -0 (< " %z " %z l" l" H H\ cpu0/alu/alu16/arith_q[13] F0 \D1 f fW WH H\ cpu0/alu/alu16/a16/N_2310 H w jF1 \ ]B0 j i i g2 g2Q [ Q [H ] H ]\ ] cpu0/alu/alu16/a16/N_2322 I n , )@F1 \ ]C0 , )@ -< (< -< (< $ O $ O q) q)- h. - h.H ] H ]\ ] cpu0/alu/alu16/arith_q[14] ]F0 \ ]C1 ]. \ . \H ] H ]\ ] cpu0/alu/alu16/arith_q[15] , ChF0 ,^ CC1 , Ch -0 Bp -0 Bp ,J C ,J C ,^ C cpu0/alu/alu16/a16/N_2389 L v iHF1 ,^ \^A0 iH i i g2 g2 7 [ 7 [ & Uf & Uf ,J \^ ,J \^ ,^ \^ cpu0/alu/alu16/a16/N_2390 M m ;. 'F1 ,^ \pD0 ;. ' ; ' ; ' 3 O 3 O '~ H^ '~ H^ #e [ #e [ ,J \p ,J \p ,^ \p cpu0/alu/alu16/arith_c m , \"F0 ,^ \vA1 , \" , \ , \ ,J \v ,J \v ,^ \v cpu0/alu/alu16/a16/un8_q_out[1] O b 5RF0 ]$ CC0 5R, 4 , 4 : : ;b ;b C C$ C cpu0/alu/rb_in[1] X J 0Q1 b 5A0 k iB0 }@ iB0 \B0 \D1 `B0 D1 ;A0 D1 (zB0 Iz iB0 ,^ iB0 z PdC1 \ OJB0 @ ]`B0 z (B1 5C0 C&A0 C>A1 ]$ CB0 ]$ CB1 $ ) D1 (D0 ( D1 5"D0 5:D1 S J 0 \ \ ( A A 'N 'N 2d 2d 5 A n B n BV b V b d{ d{ 6 b 6 b If i \ !. \ !.R * R * (z \ !. * * ) n BV ;> V ;> C B B b b i b b b, i b d{ d{ ' b ' b ,J i n B dc dc [ [ \ [ Y Y \ `
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Pu #e #57 #57 ,Gӽ ,Gӽ ,J ,J ,^ Ho\o ,JU ,^U , \@ \ ,J ,^ .w Bw cpu0/un1_k_pp_active_reg ^
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,g " / 6 σ 6 σ Ifq { { .u { {} }H " / # # ,J7 # &YG &YG ,J[ .u Bu ,J ,^ HQ\Q H\ ,J7 ,^7 ,J[ ,^[ u u Ifq Izq cpu0/regs/IX_1_sqmuxa_2 U 3F0 & ,^D0 ( BB0 ; BqB0 3 P P
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A1 z )D0 z )D1 M J 49 4 ]l ]l 9 4R .B R .B ' 'f ) 9 4A 2 A 2 6* 9 4A 2 A 2 ' ' % % ) A 2f 0 f 0Y ' Y ', ( A 2n \ n \ u u j n \f Wa f WaS h S h, j f Wa Ur Ur #Y h #Y h ,J j n \ U Up W p W 5 U 5 U @ i @ i If j n \L Ul L Ul U< U< ]l U< ^x ^x ]x A 2( / ( / & & & * * & x x< < < Uܺ UZ ܺ UZ \^ Y ', 'f 'f (z R .B 6 R .B A Af C Y ', )
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ϡ 4Ҙ 4Ҙ .q ,J ,^ . B .q Bq cpu0/datamux_o_alu_in_left_path_addr[2] g V I F1 IzYB1 Iz.A1 : B1 u$A1 fHA1 A1 A1 u$uC1 X B1 C1 fוD1 f A1 B1 B1 f B1 IzC1 V IzGC0 l u$B1 m ^D1 > I J J IfG J Bj Bj @D @D If Bj S:5 S:5 ] ] fH Bj Bj Bj S: S: W Bj 60 60 : Bj RM RM p p z z ^ Bj sJ$ sJ$ l% l% u S: f z z sJ$ n n ~ ~ S:5 ]o ]o SLI SLI IfY @D Ic Ic If. p l' l' uu ]o ]a ]a fו ]a f ]o pVi pVi p z' z' Bj Rϛ Rϛ pk pk u IfY IzY If. Iz. : : u u$ fH fH uu u$u W X fו fו f f f f If Iz IfG IzG u u$ ^ ^ cpu0/N_393
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'f ) UѪ X Ѫ XҞ \ 6* 6* j j , j@ j ]x ]x ) ) If j Iz j ,J j ,^ j \^ \^ , @ Ҟ \Ҳ \ f z f (zz (z 6 6 f Cz C , (@ ( , )
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V IF0 u$:C1 IzD0 IzD0 Iz A0 u$ B0 f"C0 u$D0 fD0 l u$A0 # I J J sJ sJ n n l=D l=D u J Mw Mw P P E E @]' @]' If P P P D D If sJ l% l% u
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u P b4r b4r f b4r kd kd u: D @i @i Ic Ic If l=D a a f" b4r u u: u$: If Iz If Iz If Iz u u$ f" f" u u$ f f u u$ cpu0/datamux_o_dest_reg_addr[1] c ; ;F1 % BoA0 & ,^ B1 ( BD0 * D1 5\cD0 6\A0 J ,^ID0 J ,^aD1 ; BkA0 \ D1 r IzwC0 ' ; օ օ ؉ ؉ .o օ . օe eES ESEƩ EƩHc eH ؉ .k օ Jk nE nE nE #; #; ,JI #; ,Ja ES
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7 @d @d .s .s { { Jk +PҘ +PҘ ,J Jk 5ϛ 5ϛ Ifw .o Bo ,J ,^ . B Hc\c H\ ,JI ,^I ,Ja ,^a .k Bk Ifw Izw cpu0/k_write_tfr
Q0 * C1 5\{D1 B XAB0 B X_C1 C u$A0 C u$A1 D : B0 D : B1 E f `B0 E f xB1 F X B0 F X A1 G Iz C0 G Iz A1 H ,^ bC0 H ,^ nA1 I X (tA0 I X (A1 k BoB1 F - -ˊ ] ˊ ] V V O-
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* * ) cpu0/alu/alu16/a16/un8_q_out[7] \ _f 4F0 cҲ 5D0 f 4R 4 R 4] 2 ] 2Ҟ 5 Ҟ 5Ҳ 5 cpu0/alu/rb_in[7] b J 4Q1 _$ 5A0 h$ ixA0 z i~B0 z BHB1 z \^A0 ^D1 z A0 D1 A0 aD1 $ 'A0 X ixA0 : i~B0 \ ] C1 $ BB1 \ kC1 \ jA1 PA1 Ҳ k D1 Ҳ j D1 \ jD1 @ PFB0 `@A0 BYB1 cҲ 5B0 cҲ 5B1 ez CPD1 @ )D1 BB0 BB1 f J 4? 4 ^ ^ aa ? 4 : : B :\ ;b \ ;bI 4 I 4 2 2 5 \ ;bC N C N h h ix : =T =T^ j ^ j b b i~ =T * =- * =- O N O N N hd N hd W ix =T 4 4Ҟ 5 ? 4v .6 v .6 ' 'c c f v .6 ' ' 'c c a I 4 % % ' * =- P i P i D b D b : i~ =Tc N c NH ] c N3 h@ 3 h@H k 3 h@H j c N H^ H^ Km Km P bb bb b bbҞ k 3 h@H j H^, PF ܺ ܺ, 4Ҟ 5 4 !. !. * *, ) : B : ;D ;Df BH ;D N Nc Y c Yf \^ N Ux Ux X X ^ \ ;b DD DD B b bbҞ j ܺF F 4 4 .Y ;Dx >S x >Sf CP 5$ 5 ix$ ix i~ i~ f BHz BH f \^z \^ f z '$ ' W ix X ix : i~ : i~ H ] \ ] B$ B H k\ k H j\ j P P Ҟ k Ҳ k Ҟ j Ҳ j H j\ j , PF@ PF ,@ .Y BY Ҟ 5Ҳ 5 Ҟ 5Ҳ 5 f CPz CP , )@ ) B B B B cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO_1 ] c 5RF0 q ,^ (C0 5RH 4 ,J ( ,^ ( H 4 0 0 #w ' #w ' ,J ( cpu0/alu/alu16/a16/un8_q_out[8] ^ _f 4F1 @ )D0 f 4X 4 X 4f - f -P P , ) , )@ ) cpu0/alu/rb_in[8] d Q0 _$ 5.B1 h$ iB1 z iB1 k$ C1 Ҳ jC1 @ )|C0 l l]G ]GC
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W p W p R o R o N & N & W (t N & W ( %N %N #Yգ #Yգ } } ț ț }0M 0M- - H{ %N c c .o H{\{ WA XA W_ X_ u u$ u u$ : : : : f ` f ` f x f x W X W X If Iz If Iz ,J b ,^ b ,J n ,^ n W (t X (t W ( X ( .o Bo cpu0/k_write_dest fʙQ0 * B1 5\iA1 k B{D1 fʙɛ ɛf f ƣ ƣ E E .{ E o oHi Hi\i .{ B{ cpu0/regs/PC_1_sqmuxa_1 * ɣF1 & ,^A0 * A0 ɣ r; r; 'w 'w ,J r; Ʃ Ʃ ,J ,^ cpu0/regs/SU_1_sqmuxa_3_2 W ,F0 & ,^D1 , ,f ,f #U #U #SՑ #SՑ ,J ,J ,^ cpu0/regs/un1_right_reg_4
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\ k
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& %F1 j BC0 % v v =s =s . . B cpu0/datamux_o_dest_reg_addr[3] _ r I;F1 * D0 5\WB0 6\D0 J ,^OA1 \ B1 r Iz}D0 I; J:օ J:օ 0 0 w w w
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Ҟ 6Ҳ 6 cpu0/alu/alu16/a16/q_out_2_cry_11_0_RNO_0 l 5F0 o ,^ )C1 5f 5& ,J ) ,^ ) f 5&̾ : ̾ : = = #S 42 #S 42 ,J ) cpu0/alu/alu16/a16/un8_q_out[13] m \f 6NF0 $ )D0 f 6N 5V 5V & & ) )$ ) cpu0/alu/rb_in[13] n Q0 \$ 6A0 e$ jA0 w jB0 m$ D0 $ BA1 $ (B0 n n Q Q & & 2" 2" 6 Q i i b\ b\ e e j Q ;& ;& B & % % ( b\r b r b j 6$ 6 j$ j j j $ B$ B ($ ( cpu0/alu/alu16/a16/q_out_2_cry_13_0_RNO o f (F0 n ,^ )|C0 f ( ( ,J )| ,^ )| ( " " 3 3 ' . ' . #; & #; & ,J )| cpu0/alu/alu16/a16/un8_q_out[14] p \f 6ZF1 $ C&A0 f 6Z 5V 5V0 : 0 : C& C&$ C& cpu0/alu/rb_in[14] p Q0 \$ 6A1 e$ k
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W
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A1 w kB1 \ \A1 $ C8D0 $ CPD1 ӊ ӊ6 7 6 7 - - 7* 7* 6 - @ @ CP @ w w qA qA hv hv k hv UZ UZH \ @ C8 @ [ [ k
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WN~ N~HW
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6$ 6 k
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WK KEӽ EӽH w w 'C 'C ,JO J:օ HB؉ HB؉ If} HW\W H\ ,JO ,^O If} Iz} cpu0/regs/un1_write_reg_addr_1
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$ k
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J ,F1 ! A1 " ,^C0 " ,^B1 # ,^A0 # ,^D1 $ :D0 $ :D1 J ,^CC0 X iA1 , - Q - Q +U +U ,J - Q ,J - Q #G #G 6f 6f 1' 1' 'K 'K 1' : 1' : - Q ,JC 'K i 'K ,J - Q #AA #AA ,J ,J ,^ ,J ,^ ,J ,^ ,J ,^ : : : : ,JC ,^C i i cpu0/regs/SU_0 Q 5RF0 ? ,^ (B1 b ,^ xB1 5R f 4 f 4 " 2 " 2 # ' # ' ,J x f 4 '` '` 'l ! 'l ! ,J ( ,J ( ,^ ( ,J x ,^ x cpu0/k_inc_su Q0 < X )B1 D X%B1 :׃A1 : 5B0 : 5.B1 P (D0 P (C1 y +C1 & lk lk` `
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k k H \\ \ C8$ C8 CP$ CP cpu0/alu/alu16/a16/q_out_2_cry_13_0_RNO_0 r f BF0 n ,^ )C1 f B B@ ,J ) ,^ ) B@ = = ' ; ' ; #; 3 #; 3 ,J ) cpu0/alu/alu16/a16/un8_q_out[15] s [ 4F0 Ҳ 6D0 4 4 4̭ 2( ̭ 2(Ҟ 6 Ҟ 6Ҳ 6 cpu0/alu/alu16/a16/q_out_2_cry_15_0_RNO t 6NF0 m : (C0 6Nӄ 5V : ( : ( ӄ 5V 2 2
h 0
h 0 2 ' 2 ' : ( cpu0/alu/alu16/a16/rb_in_i[15] 6ZF1 [Ҳ 5B0 6ZӐ 5V Ӑ 5VѤ 19 Ѥ 19Ҟ 5 Ҟ 5Ҳ 5 cpu0/alu/alu16/a16/un8_q_out_cry_14 u \' 6FCO [ҵ 4FCI ' 6 6 Ҟ 4ҵ 4 \ 1Ҟ 4 6\ 1 cpu0/alu/alu16/a16/un8_q_out[16] w [ 4F1 m : (A1 4 4 4] 2 ] 2 ' ', ,
n
n 1 1 : ( : ( : ( cpu0/alu/alu16/a16/rb_in_i[13] mf F0 \$ 6B0 f ' ' 6 6$ 6 cpu0/alu/ra_in[13] mQ0 \$ 6C0 e$ jB0 n ,^ )pA0 w kD0 $ BA0 m F 6$ 6 k k F P P ~ (q ~ (q J J A A 6 J [n [n j ~ (q ' ' ,J )p ~ (q [& [&
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B
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bb
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B * = * = N 42 N 42 W ) * = N 3 N 3 E* E* 1 3 1 3 : 5 1 3 : 5. E* ( ( ( ( $ $ ( Q Q U U
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bb~ bb ~ bb k A B j$ j ,J )p ,^ )p B$ B cpu0/alu/alu16/a16/rb_in_i[14] f BF1 \$ 6B1 f B B@ B@
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4 6 6$ 6 cpu0/alu/ra_in[14] ,Q0 \$ 6C1 e$ kB1 n ,^ )A1 w k D1 \ \C0 , ,` 6$ 6 k k ,` &j &j O O
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hv k ,` &d &d #Y #Y ,J ) &j % 5 % 5 8 U` 8 U`4 U 4 U i i k 4 UH \ ` 5 ` 5 . . 19 19 6 k$ k ,J ) ,^ ) H \\ \ cpu0/alu/alu16/a16/un8_q_out_cry_12 x ]' 69FCO \' 6EFCI ' 69' 6E cpu0/alu/alu16/a16/rb_in_i[11] lf F0 ]$ 6B0 f ĺ ĺ + 'N + 'N 6 6$ 6 cpu0/alu/ra_in[11] ;.Q0 ]$ 6C0 f$ jzB0 o ,^ (A0 x jD0 \ jD0 ;. ; ` 6$ 6 j j ; ` 0G 0G #}
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A1 x jD1 \ jC0 60$ 60 j j T (k T (k
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+ * = %$ G %$ G #S #S 6Bw 6Bw :׃
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I
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B * dQ * dQ N [8 N [8 P )[ P )[ N N W W W% W ) X ) W% X% :׃ :׃ : 5 : 5 : 5. : 5. ( ( ( ( + + cpu0/regs/SU_4_sqmuxa P (DF1 ? ,^ 'B0 (D r ' r ' ' !
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P D ! D ! @ F @ F If D ! @ 4h @ 4h 6 .* 6 .* : 5 @ F 6 6 : ` D ! If ( Q
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Q0 ^$ 5C0 g$ iA0 p ,^ (tA0 y jD0 Ҳ jC0 ;. P
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P O O H( H( #) [ #) [ ,J i~ O N T N Tv W v W / h / h, ix , ix@ ix ,J i~ ,^ i~ cpu0/alu/alu16/mulu/pipe1_1_6_14 e BF0 z BNC1 B. B@ f BNz BN . B@ ? ?- 4 - 4R !( R !( 4 4f BN cpu0/alu/alu16/mulu/pipe1_1_6_cry_7_0_RNO e BF1 z B6C0 B: B@ f B6z B6 : B@0 DD 0 DDf B6 cpu0/alu/alu16/mulu/q_out_3[6] J )4F0 z B*A0 J )4 (< (< %z %zi 4 i 4 f B* f B*z B* cpu0/alu/alu16/mulu/pipe1_1_6_cry_5_RNO_0 . 6ZF1 CB1 . 6Z 5V 5V< - < -E @ E @ ; ; DD DD C C C cpu0/alu/alu16/mulu/pipe1_1_6_13 . 6NF0 CA1 . 6N 5V 5V @ @ ?r ?r C C C cpu0/alu/alu16/mulu/pipe1_1_6_10 ChF0 CA0 ChL Bp L Bp% ? % ? C C C cpu0/alu/alu16/mulu/pipe1_1_6_7 CtF1 CDB1 CtX Bp X Bp% ? % ? CD CD CD cpu0/alu/alu16/mulu/pipe1_1_6_4 J BF0 C,B0 J B B@ B@ ? ?0 ;8 0 ;8 C, C, C, cpu0/alu/alu16/mulu/pipe1_1_6_1 J BF1 BA1 J B B@ B@ ; ; B B B cpu0/alu/alu16/mulu/N_1213 F0 \
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O O O 4D O 4D W B W B X B cpu0/alu_o_CCR[0] f 'F0 f 'DI0 f ' f ' f ' f ' f ' f ' cpu0/alu_o_CCRf[0] f 'Q0 X OB0 X BD1 X C2C0 X CJC1 f ' f ' f ' \A %z \A %z N 4 N 4 W CJ N 4 W C2 N 4 W B N 4 O' N O' N W O W O X O W B X B W C2 X C2 W CJ X CJ cpu0/regs/SU_s[0] b > , (8F0 > ,^ (hDI0 , (8 , ' ,J (h ,^ (h , ' ,J (h cpu0/regs/SU_s[1] d > , (DF1 > ,^ (nDI1 , (D - ' ,J (n ,^ (n - ' ,J (n cpu0/regs/SU_s[2] g = , (F0 = ,^ (DI0 , ( - ( ,J ( ,^ ( - ( ,J ( cpu0/regs/SU_s[3] i = , (F1 = ,^ (DI1 , ( - ( ,J ( ,^ ( - ( ,J ( cpu0/regs/SU_s[4] k < , )4F0 < ,^ )dDI0 , )4 -0 (< ,J )d ,^ )d -0 (< ,J )d cpu0/regs/SU_s[5] l < , )@F1 < ,^ )jDI1 , )@ -< (< ,J )j ,^ )j -< (< ,J )j cpu0/regs/SU_s[6] n ; ;. 'F0 ; : 'DI0 ;. ' ; ' : ' : ' ; ' : ' cpu0/regs/SU_s[7] o ; ;. 'F1 ; : 'DI1 ;. ' ; ' : ' : ' ; ' : ' cpu0/regs/SU_s[8] q : ;. (8F0 : : (hDI0 ;. (8 ; ' : (h : (h ; ' : (h cpu0/regs/SU_s[9] s : ;. (DF1 : : (nDI1 ;. (D ; ' : (n : (n ; ' : (n cpu0/regs/SU_s[10] u 9 ;. (F0 9 : (DI0 ;. ( ; ( : ( : ( ; ( : ( cpu0/regs/SU_s[11] v 9 ;. (F1 9 : (DI1 ;. ( ; ( : ( : ( ; ( : ( cpu0/regs/SU_s[12] w 8 ;. )4F0 8 : )dDI0 ;. )4 ; (< : )d : )d ; (< : )d cpu0/regs/SU_s[13] y 8 ;. )@F1 8 : )jDI1 ;. )@ ; (< : )j : )j ; (< : )j cpu0/regs/SU_s[14] { 7 I 'F0 7 Iz 'DI0 I ' I ' If ' Iz ' I ' If ' cpu0/regs/SU_s[15] } 7 I 'F1 7 Iz 'DI1 I ' I ' If ' Iz ' I ' If ' cpu0/regs/SS_s[0] G XJ 5RF0 G X 5DI0 XJ 5R X 4 W 5 X 5 X 4 W 5 cpu0/regs/SS_s[1] G XJ 5^F1 G X 5DI1 XJ 5^ X 4 W 5 X 5 X 4 W 5 cpu0/regs/SS_s[2] F XJ 5F0 F X 6 DI0 XJ 5 X 5& W 6 X 6 X 5& W 6 cpu0/regs/SS_s[3] F XJ 5F1 F X 6DI1 XJ 5 X 5& W 6 X 6 X 5& W 6 cpu0/regs/SS_s[4] E XJ 6NF0 E X 6~DI0 XJ 6N X 5V W 6~ X 6~ X 5V W 6~ cpu0/regs/SS_s[5] E XJ 6ZF1 E X 6DI1 XJ 6Z X 5V W 6 X 6 X 5V W 6 cpu0/regs/SS_s[6] D f 4F0 D f 5DI0 f 4 f 4 f 5 f 5 f 4 f 5 cpu0/regs/SS_s[7] D f 4F1 D f 5
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cpu0/regs/SS_s[8] C f 5RF0 C f 5DI0 f 5R g, 4 f 5 f 5 g, 4 f 5 cpu0/regs/SS_s[9] C f 5^F1 C f 5DI1 f 5^ g8 4 f 5 f 5 g8 4 f 5 cpu0/regs/SS_s[10] B f 5F0 B f 6 DI0 f 5 gJ 5& f 6 f 6 gJ 5& f 6 cpu0/regs/SS_s[11] B f 5F1 B f 6DI1 f 5 gV 5& f 6 f 6 gV 5& f 6 cpu0/regs/SS_s[12] A f 6NF0 A f 6~DI0 f 6N gh 5V f 6~ f 6~ gh 5V f 6~ cpu0/regs/SS_s[13] A f 6ZF1 A f 6DI1 f 6Z gt 5V f 6 f 6 gt 5V f 6 cpu0/regs/SS_s[14] @ uf 4F0 @ u$ 5DI0 uf 4 uR 4 u 5 u$ 5 uR 4 u 5 cpu0/regs/SS_s[15] @ uf 4F1 @ u$ 5
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i g8 g8 2 C 2 C ;V ;V ,J BN ,J BN ,^ BN cpu0/alu/alu16/N_2295 4 AF1 ;Ҳ BD1 A A AҞ B Ҟ BҲ B cpu0/alu/alu16/N_97 5 iOFX0 ;Ҳ BC1 i i i b b ɳ N ɳ NҞ B Ҟ BҲ B cpu0/alu/alu16/N_2296 7 \.F1 Ҳ ]lD0 \. [ [̭ Y| ̭ Y|Ҟ ]l Ҟ ]lҲ ]l cpu0/alu/alu16/N_98 8 jOFX0 Ҳ ]ZA0 j~ i ~ i b b Ҟ ]Z Ҟ ]ZҲ ]Z cpu0/alu/alu16/N_2297 : PF1 OD1 P OZ OZ O O O cpu0/alu/alu16/N_99 ; P|OFX0 OC1 P| O O Km Km O O O cpu0/alu/alu16/N_2298 = , ]F1 ,^ 66D1 , ] -< \ -< \ & T & T #/ @ #/ @ ,J 66 ,J 66 ,^ 66 cpu0/alu/alu16/N_100 > iOFX0 ,^ 6$A1 i i i L C L C * * #q 'r #q 'r ,J 6$ ,J 6$ ,^ 6$ cpu0/alu/alu16/N_2446 @ jDF1 OD1 jD i i { g2 { g2 [ [ O O O cpu0/alu/alu16/N_101 A jOFX0 OA1 j( i ( i
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cpu0/regs/left_1[14] I XJ (8F0 $ :B0 I X (hDI0 X Iz 6rM0 D X CA0 D X CA1 IzM0 XJ (8 X ' W (h X (h If 6r Iz 6r If Iz X ' W (h X ' O 4h O 4h W C X ' RD RD DR DR @
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u: u: u$: cpu0/regs/left_1f_1[2] U I 4Q1 IzC0 I 4 I 4 I 4 B E B E @C @C If If Iz cpu0/regs/rightf_1[2] U I 4Q0 IzA0 I 4 I 4 I 4 C : C : B@ G B@ G @i @i If If Iz cpu0/k_new_pc[2] $ < ,@OFX0 < ,^vDI0 ,@ ,1 ,Jv ,^v ,1 ,Jv cpu0/regs/k_new_pcf[2] < ,LQ0 , RB1 ,L ,% ,% " " < < R R R cpu0/regs/left_1f_4[3] T XJQ1 :A0 XJ X X E E : : : cpu0/regs/rightf_4[3] T XJQ0 :C0 XJ X X D D 9 9 : : : cpu0/regs/k_new_pc[3] = ;.z&OFX0 = :z\DI0 ;.z& ;z :z\ :z\ ;z :z\ cpu0/regs/k_new_pcf[3] = ;.z2Q0 + BOA1 ;.z2 ; z ; z 3I 3I `j `j g g .O .O BO cpu0/regs/left_1f_4[4] K ;. 0Q1 :B1 ;. 0 ; ; 5. o 5. o 1s 1s : : : cpu0/regs/rightf_4[4] K ;. $Q0 :A1 ;. $ ; ; 1
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, 4 4 : : : cpu0/k_new_pc[4] " > ,{OFX0 > ,^{DI0 ,{ -*z ,J{ ,^{ -*z ,J{ cpu0/regs/k_new_pcf[4] > ,{Q0 * A1 ,{ -6z -6z $+ $+ \ \ cpu0/regs/left_1f_4[5] J I 5dQ1 IzC1 I 5d J" 4 J" 4 Bj 3 Bj 3 @ @ If If Iz cpu0/regs/rightf_4[5] J I 5XQ0 IzB1 I 5X J 4 J 4 @ '` @ '` @W @W If If Iz cpu0/regs/k_new_pcf[5] ? ,zQ0 ) ,^C1 ,z ,zN ,zN &d &d #q #q ,J ,J ,^ cpu0/regs/PC_pipe_5 + XJQ1 XD1 XJ X X R R O O W W X cpu0/regs/left_1f_4[6] I ;. 5dQ1 : nA1 ;. 5d ; 4 ; 4 1 '< 1 '< : n : n : n cpu0/regs/rightf_4[6] I ;. 5XQ0 : zC1 ;. 5X ; 4 ; 4 1 '` 1 '` 4 4 : z : z : z cpu0/k_new_pc[6] # @ ;.{"OFX0 @ :{XDI0 ;.{" ;z~ :{X :{X ;z~ :{X cpu0/regs/k_new_pcf[6] @ ;.{.Q0 ( Iz[C1 ;.{. ;z~ ;z~ 31 31 D] D] @o] @o] If[ If[ Iz[ cpu0/regs/left_1f_4[7] H I Q1 : A1 I J@ J@ 6x 6x : : : cpu0/regs/rightf_4[7] H I Q0 : B1 I J4 J4 6T 6T 9 9 : : : cpu0/regs/k_new_pc[7] A , X fC0 > X D1 uf uX u u$ If Iz u u$ uX n& n& lC | lC | u n& a a O 4 O 4 W f O 4 W W W n& Fޞ Fޞ ! ! y lC | u
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H: Hj Hj Q^ Q^, O , O@ O cpu0/alu/alu16/N_69 L f ] F0 \ \D0 $ BD0 \ kD0 \ iB0 PB0 Ҳ jB0 Ҳ jD0 \ jtA0 @ P@A0 @ CA0 \ OPC0 \D0 Ҳ PRD0 \pD0 $ B*A0 Ҳ ODA0 1 f ] \t \t Uf Uf U U{ i { iH i U$ ^x $ ^xH \ \t Nf Nf B { iH k U N N LP LP P Ufɡ h ɡ hҞ j ɡ hҞ j { iH jt N" H| " H|H OP $ ^xH ] H ] Y Y \ Nf HL HLz Q^ z Q^Ҟ PR \t] Z ] Z UB UB \p Nf B* HLҞ OD HL, P@ Nf ;2 ;2, C H \\ \ B$ B H k\ k H i\ i P P Ҟ jҲ j Ҟ jҲ j H jt\ jt , P@@ P@ , C@ C H OP\ OP \ \ Ҟ PRҲ PR \p \p B*$ B* Ҟ ODҲ OD cpu0/alu/alu16/N_87 P f \"F0 \ \M0 $ BM0 \ jM0 \ iM0 PM0 Ҳ jM0 Ҳ iM0 \ j\M0 @ PRD0 @ CD0 \ OVD0 \A0 Ҳ PFB0 \jC0 $ B6C0 Ҳ OJB0 3 f \"R \ H \\ \ B$ B H j\ j H i\ i P P Ҟ jҲ j Ҟ iҲ i H j\\ j\ R \x U x U$ Uf $ UfK h K hH j\ K hE f E fH j E fH i $ Uf ^x ^xH \ R \ Y Y N N2 ;J 2 ;J B 2 ;J ; ; N N P x U i iқ f қ fҞ j қ fҞ i $ Uf \ 2 ;Jɹ N ɹ NҞ PF $ Uf ^x ^x \j 2 ;J DD DD B6 N2 Hd 2 HdҞ OJ ; N N , PR ;, C N l H4 l H4H OV , PR@ PR , C@ C H OV\ OV \ \ Ҟ PFҲ PF \j \j B6$ B6 Ҟ OJҲ OJ cpu0/alu/alu16/N_33 h , \.F1 i ,^ `B0 , \. , [ , [ %u 6 %u 6 #} | #} | ,J ` ,J ` ,^ ` cpu0/alu/alu16/q_out_sn_i4_mux k f \.F1 $ \dB0 f \.X [ X [ \d \d$ \d cpu0/alu/alu16/q_out_sn_N_6 l f ]*F1 $ ]fC0 f ]* \t \t ]f ]f$ ]f cpu0/alu/N_143_1 r g \"F0 BB0 VA0
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$ ( Q0 :B0 f B0 X/D0 ,^D0 : B0 Iz3D0 XD0 ,^}D0 XD0 :B0 fD0 :D0 ,^D0 XD0 :A0 :D0 / 9 9 ]s} ]s} Ss Ss W ]s} S S If3 9 1 1 : S W S W/ {} {} ' ' : 1 : 1 : 1 2! 2! : ]s} f 9 ] ] f S W Ss 6s 6s #;I #;I ,J} ' 1 1 : n_ n_ ,J 6s ,J : : f f W/ X/ ,J ,^ : : If3 Iz3 W X ,J} ,^} W X : : f f : : ,J ,^ W X : : : : cpu0/regs/rightf[15]
% ( Q1 XA0 H H 9 9 R R O-o O-o W W X cpu0/regs/IX_0_sqmuxa_1_1_RNI2C2L3
& 8 F1 & ,^ַCE ' Iz9CE S Iz׳CE 7 IzַCE o BCE :OCE fCE XCE ,^׳CE :CE IzCE XmCE ,^5CE :CE fiCE :ʙCE ,^CE XiCE :SCE :CE T IzOCE : CE : CE IzCE :CE ` !ѿ + ؉ + ؉ ,Jַ ,Jַ ,^ַ [ѿ H<؉ H<؉ If9 If9 Iz9 H<؉ If׳ If׳ Iz׳ H<؉ Ifַ Ifַ Izַ !
. . B ! 4 4 :O :O :O [ ` ` f f f [ R R W W X !ѿ &YӁ &YӁ ,J׳ ,J׳ ,^׳ 4 : : : [ H0 H0 If If Iz [ V V Wm Wm Xm &YӁ ,J5 ,J5 ,^5 !
4 4 : : : [ ` ` fi fi fi !ĥ 4g 4g :ʙ :ʙ :ʙ ! + + ,J ,J ,^ R Wi Wi Xi ! 9 9 :S :S :S 9 : : : [ Cu Cu IfO IfO IzO ! , 4 4 : : : 4 : : : [
H< H< If If Iz !
9 9 : : : қ қ !ѿ M TWқ TWқ [ѿ !
ߵ ߵ ! M TWߵ TWߵ [ M TW TW [ Ł Ł !ĥ X X ! , M TW TW [
A A M A | X X A A | A + A = + = PAR_CLOCKSIGNAL 2 sclk_id cpu0/regs/ea_reg_postf_0[14]
' 7 IQ1 IzA1 I J"U J"U @u @u If If Iz cpu0/regs/ea_reg_postf_0[0]
( 7 IַQ0 XeD1 Iַ JU JU SϏ SϏ Oȿ Oȿ We We Xe cpu0/regs/left_1f_0[0]
) S IQ1 XSA1 I J^ֵ J^ֵ M) M) Nw Nw WS WS XS cpu0/regs/rightf_0[0]
* S I׳Q0 XMD0 I׳ JRֵ JRֵ C C Su Su O O WM WM XM cpu0/regs/ea_reg_postf_0[1]
+ ;.Q1 C1 ;. ;#T ;#T 'Z 'Z cpu0/regs/left_1f_0[1]
, ;.Q0 A1 ;. ; ` ; ` '6 '6 cpu0/regs/rightf_0[1]
- IQ1 B0 I IT IT ?%G ?%G ' ' cpu0/regs/left_1f_0[14]
. IQ0 Iz-D1 I I` I` @U @U If- If- Iz- cpu0/regs/ea_reg_postf_0[2]
/ ;. ,Q1 ,^ C1 ;. , ; " ; " 0 f 0 f ,J ,J ,^ cpu0/regs/left_1f_0[2]
0 ;. Q0 ,^ B1 ;. ; " ; " 0 ` 0 ` ,J ,J ,^ cpu0/regs/rightf_0[2]
1 ;. Q1 ,^ A0 ;. ; ; ' ' ,J ,J ,^ cpu0/regs/ea_reg_postf_0[3]
2 ;. Q0 IzA1 ;. ; ; 3 3 D D If If Iz cpu0/regs/left_1f_0[3]
3 o Q1 IzD1 yT yT ~P ~P 6 6 If If Iz cpu0/regs/rightf_0[3]
4 o Q0 IzC0 s` s` 9 9 R R O-U O-U DR DR If If Iz cpu0/regs/ea_reg_postf_0[4]
5 T I[Q1 ,^-D1 I[ J@ J@ ?%
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(2g (2g ,J- ,J- ,^- cpu0/regs/left_1f_0[4]
6 T IOQ0 ,^A1 IO J4 J4 6T܋ 6T܋ ,J ,J ,^ cpu0/regs/rightf_0[4]
7 ;.Q1 ,^D0 ;. ;o ;o 0
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,J ,J ,^ cpu0/regs/ea_reg_postf_0[5]
8 ;.Q0 :֙D1 ;. ;o ;o 1 1 :֙ :֙ :֙ cpu0/regs/left_1f_0[5]
9 ;.Q1 :֍B1 ;. ; ; 5.P 5.P 1? 1? :֍ :֍ :֍ cpu0/regs/rightf_0[5]
: ;.Q0 :ցD0 ;. ; ; 5(P 5(P 1 1 :ց :ց :ց cpu0/regs/rightf_0[14]
; fQ1 IzD0 f gz gz Sg Sg If If Iz cpu0/regs/ea_reg_postf_0[6]
< fQ0 X֍B1 f gn gn \A
\A
NI NI W֍ W֍ X֍ cpu0/regs/left_1f_0[6]
= XJQ1 X֙D1 XJ X X RD6 RD6 O յ O յ W֙ W֙ X֙ cpu0/regs/rightf_0[6]
> XJQ0 X{C0 XJ X X b4 b4 lc lc bFY bFY VҘ VҘ W{ W{ X{ cpu0/regs/ea_reg_postf_0[7]
? ,Q1 :A1 , -Bֵ -Bֵ 0/ 0/ : : : cpu0/regs/left_1f_0[7]
@ ,׳Q0 :C1 ,׳ -6ֵ -6ֵ 6_ 6_ 9؉ 9؉ : : : cpu0/regs/rightf_0[7]
A ;.Q1 :A0 ;. ; ; 1% 1% : : : cpu0/regs/ea_reg_postf_0[8]
B ;.Q0 IzC1 ;. ; ; ?%I ?%I If If Iz cpu0/regs/left_1f_0[8]
C IQ1 IzA1 I J" J" C6 C6 If If Iz cpu0/regs/rightf_0[8]
D IQ0 IzA0 I J J @ @ Cu Cu If If Iz cpu0/regs/ea_reg_postf_0[9]
E XJyQ1 XוD1 XJy X?: X?: M' M' @Wc @Wc S_ S_ Wו Wו Xו cpu0/regs/left_1f_0[9]
F XJmQ0 X׃A1 XJm X9F X9F O-; O-; W׃ W׃ X׃ cpu0/regs/rightf_0[9]
G ,AQ1 X}D0 ,A -$օ -$օ & & V4. V4. N7 N7 W} W} X} cpu0/regs/ea_reg_postf_0[15]
H ,5Q0 :A1 ,5 -օ -օ #Sw #Sw 6BC 6BC : : : cpu0/regs/ea_reg_postf_0[10]
I XJuQ1 5A1 XJu X X E E ' ' 5 5 5 cpu0/regs/left_1f_0[10]
J XJiQ0 GD1 XJi X X D D ' ' G G G cpu0/regs/rightf_0[10]
K fuQ1 A0 fu g\ g\ 8"d 8"d & & cpu0/regs/ea_reg_postf_0[11]
L fiQ0 -D1 fi gP gP jc jc F F - - - cpu0/regs/left_1f_0[11]
M ,Q1 A1 , -o -o ܗ ܗ cpu0/regs/rightf_0[11]
N ,Q0 A0 , ,o ,o " " cpu0/regs/left_1f_0[15]
O ;.[Q1 :D1 ;.[ ; ; 1m 1m 19 19 : : : cpu0/regs/ea_reg_postf_0[12]
P ;.OQ0 :iA1 ;.O ; ; 5( 5( 2 2 :i :i :i cpu0/regs/left_1f_0[12]
Q ;.ʥQ1 :{D1 ;.ʥ ;ɛ ;ɛ 9~ 9~ :{ :{ :{ cpu0/regs/rightf_0[12]
R ;.ʙQ0 :WB0 ;.ʙ ;ɛ ;ɛ 9~ 9~ :W :W :W cpu0/regs/IX_0_sqmuxa
S ' I3F0 & ,^C0 ' IzcDI0 I3 I Ifc Izc I Ifc I 5ϡ 5ϡ ,J ,J ,^ cpu0/regs/IX_0_sqmuxaf
T ' I9Q0 X_C1 D1 ,^ D1 IzC1 ,^!B1 :֓C1 X֓C1 :D1 :oB1 Iz'C1 !B1 Iz+C1 :C1 AC1 XC1 IzD1 2 I9 I I ?% ?% :֓ I C C B( B( 6 6 ,J ?% 1ȿ 1ȿ :o B( 6T 6T A I C C If+ 1ȿ : C J J k k C @] @] If I C C 6 ܣ 6 ܣ ,J! 6 ܣ ܣ ܣ ! C If C If' I ?% ?% : I Rϧ Rϧ W Rϧ O- O- W_ Rϧ W֓ W_ X_ ,J ,^ If Iz ,J! ,^! :֓ :֓ W֓ X֓ : : :o :o If' Iz' ! ! If+ Iz+ : : A A W X If Iz cpu0/regs/ea_reg_postf_0[13]
U ;._Q1 Iz1D1 ;._ ;# ;# ?%C ?%C If1 If1 Iz1 cpu0/regs/left_1f_0[13]
V ;.SQ0 Iz%B1 ;.S ; , ; , D@ D@ H6 H6 If% If% Iz% cpu0/regs/rightf_0[13]
W ' IEQ1 Iz
B0 IE I I @ @ If
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cpu0/regs/IX_0_sqmuxa_1_1
X & ,ֱF0 & ,^DI0 8 BYB1 ,ֱ ,U ,J ,^ ,U ,J ,U " " > >
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' '$ ' cpu0/alu/alu8/a8/un8_q_out_cry_6 } )FCO ' 'FCI ) ) '' ' $ ' ) $ cpu0/alu/alu8/a8/un8_q_out[8] f 'F1 @ (A1 f 'X ' X '] % ] %ܺ ܺ , ( , (@ ( cpu0/alu/alu8/a8/rb_in_i[5] &F1 )vB0 &X " X " y & y & )v )v )v cpu0/alu/alu8/a8/rb_in_i[6] J )@F1 )A1 J )@ (< (
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.Y .Y BY cpu0/regs/IX_0_sqmuxa_1_1f
Y & ,ַQ0 XGC0 D0 ,^ D0 IzB0 ,^ B0 :oA0 XցD0 :B0 :]C0 IzA0 D0 IzC0 :B0 /D0 XqB0 IzD0 6 ,ַ ,U ,U &j &j % = % = #; & #; & ,J ,U V.r V.r O! O! WG &j #)G #)G 6 ,U 5Ϗ 5Ϗ : 5Ϗ 9؉ 9؉ :o ,U &d &d ,J &j s s O! Dv{ Dv{ :] 5Ϗ @ @ If #)G / @ If @ If Dv{ 2 2 : V.r ph} ph} fק fק \A \A Wq a a 6 @K? @K? SS SS Wց @ If WG XG ,J ,^ If Iz ,J ,^ :o :o Wց Xց : : :] :] If Iz If Iz : : / / Wq Xq If Iz cpu0/regs/rightf_0[15]
Z & ,Q1 :D0 , -U -U 0) 0) 1w 1w : : : cpu0/regs/DP_1_sqmuxa_1_1_0_RNIIANF1
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% ?F1 % B9CE U 9CE 8 BCE XSCE :9CE X9CE :ַCE X5CE IzSCE ? v .9 B9 9 9 . B WS XS :9 :9 W9 X9 :ַ :ַ W5 X5 IfS IzS v =Ӎ =Ӎ .9 v {) {) 'k 'k Ddϛ Ddϛ W9 'k 9Ҙ 9Ҙ :9 9Ҙ :ַ Ddϛ W5 v ϛ ϛ 9 {) T2 T2
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cpu0/alu/alu8/a8/un8_q_out_cry_2 (FCO (FCI ( ( cpu0/alu/alu8/a8/rb_in_i[1] J 'F1 (tA0 J '< ' < 'A % A % (t (t (t cpu0/alu/alu8/a8/rb_in_i[2] (F1 (A1 (: ( : ( ( ( ( cpu0/alu/alu8/a8/un8_q_out_cry_0 (#FCO (/FCI (# (/ cpu0/alu/alu8/a8/rb_in_i[0] J (DF1 (B1 J (D ' 'A % A % ( ( ( cpu0/alu/alu8/a8/q_out_1_cry_6 I} k FCO X i3FCI I} k If k" W i0 X i3 M f` W i0 If k" M f` cpu0/alu/alu8/a8/q_out_1[7] XJ i
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+ + [K [K . Ddϛ O O WS O Dvܯ Dvܯ IfS cpu0/regs/rightf_1[4]
\ XJSQ0 \D0 XJS X9, X9, \AC \AC 8( 8( Em EmH H\ cpu0/regs/left_1f_2[5]
] U EQ1 $ A1 E 9 9 " " cpu0/regs/rightf_2[5]
^ U 9Q0 $ B1 9 cpu0/regs/left_1f_1[6]
_ 8 Q1 / BA1 2 2 [D [D + + . . B cpu0/regs/rightf_1[6]
` 8 Q0 / BB1 P P v v . . B cpu0/regs/left_1f_1[0]
a XJAQ1 % XA1 XJA Xօ Xօ NS NS N N O!* O!* W W X cpu0/regs/rightf_1[0]
b XJ5Q0 % XB1 XJ5 Xօ Xօ RD RD Q 9 Q 9 O O W W X cpu0/regs/left_1f_1[1]
c I_Q1 \2A1 I_ I I ޞ ޞ
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b ;. \"F0 @YB1
$ O2M1 @ \LM1 Ҳ M1 BM1 M1 : \M0 Ҳ PM0 @B0 + ;. \" ; \ O2$ O2 , \L@ \L Ҟ Ҳ B B : \ : \ Ҟ PҲ P ; \ 4 Yj 4 Yj : \ ; \ '6 U '6 U
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T TH2 H2\2 cpu0/regs/rightf_1[1]
d ISQ0 \DD1 IS I, I, ?% ?% 3 3 ' ' z zHD HD\D cpu0/regs/left_1f_2[2]
e ;.Q1 :=B0 ;. ;U ;U 4 4 1 1 := := := cpu0/regs/rightf_2[2]
f ;.ַQ0 :7A0 ;.ַ ;U ;U 0 0 $2 $2 6f 6f :7 :7 :7 cpu0/regs/left_1f_1[3]
g XJEQ1 # X4B1 XJE X? X? \A/ \A/ ] ] _ _ S( S( W4 W4 X4 cpu0/regs/rightf_1[3]
h XJ9Q0 # X.A1 XJ9 X9 X9 Q Q On On OgL OgL O O W. W. X. cpu0/regs/DP_1_sqmuxa
i % 3F0 % BևA1 % BcDI0 3 p .c Bc p .c p .և .և Bև cpu0/regs/DP_1_sqmuxaf
j % 9Q0 \>C1 # X:C1 $ C1 % XC1 / BC1 \C0 BB0 :CC0 9 s s g g 7C 7C gN gN . s 9 љ 9 љ 1 1 1 1 :C gN gN4 4H> 9 љ ]ȿ ]ȿ _
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S S W S W: s4ϡ 4ϡH s ={ ={ . H>\> W: X: W X . B H\ . B :C :C cpu0/regs/left_1f_1[4]
k ;.EQ1 \B0 ;.E ;# ;# `ф `фϏ ϏH H\ cpu0/regs/left_1f_1[7]
l ;.9Q0 BC0 ;.9 ; ; 5. 5. x x 7 7 . . B cpu0/regs/rightf_1[7]
m % EQ1 BA0 E y y =Ӂ =Ӂ . . B cpu0/regs/ACCB_0_sqmuxa_1_RNILJP21
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U` U U, \L '6 U N N B U͊ U ͊ U N Ṋ LP ̭ LPҞ P U Ws Ws 6 6 eo eo,Y N Hv Hv O2 Ws 6 6 | |Ҟ Ws N N 42 42 ; \ 4 b 4 b x d9 x d9 C C , ,Y@Y ,@ cpu0/alu/q8_out[7] F0 C1 @ BHB1 nf nfy} y} nfL L 5 5 N N , BH , BH@ BH cpu0/alu/alu8/N_143 " l \"F0 C0 Ҳ fC0 : \C0 Ҳ PB0 \" \ \s 6 s 6 0% 0%- ' - '\ \ 0%ɿ '` ɿ '`Ҟ f \ *r W *r W DR U DR U : \ \ Y Y N N` H^ ` H^Ҟ P Ҟ fҲ f : \ : \ Ҟ PҲ P cpu0/alu/alu8/datamux_o_dest_6[14] # ;.ֱF0 ,^A0 :C1 ;.ֱ ;U ;U 0 0 #}) #}) #M #M ,J ;U : ,J ,^ : : cpu0/alu/alu8/datamux_o_dest_6[2] & IF0 Iz[C1 I J.Q J.Q If[ If[ Iz[ cpu0/alu/alu8/v8_sn_N_13_mux ) b ;. \.F1 b : \dB0 \^A0 ;. \. ; [ ; [ : \d ; [ 'Z U 'Z U ^x ^x \^ : \d : \d \^ \^ cpu0/alu/alu8/N_115 + \"F0 @ ]D1 ]C1 \" \ \ Y| Y| ] \
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k F0 J ,^CE CE ,^ CE IziCE ,^CE :CE IzCE IzCE :CE . k ,J ,^ ,J ,^ Ifi Izi ,J ,^ : : If Iz If Iz : : k N N 8 8 & & & #M #M 6B 6B @o @o Cu Cu Ifi #M ,G 0 ,G 0 ,J 6B H6 H6 Ic
Ic
C C @1 @1 If @o @o @o Cu Cu If #M ,G ,G ,G
,G
0 0 r r 2 2 g g ,J @1 5ܯ 5ܯ ,J g 'H 'H : N 9H 9H 1/ 1/ 4Y 4Y : cpu0/regs/rightf_2[4]
o ,Q0 ,^XC1 , -6 -6 & & #_ț #_ț #_g #_g ,JX ,JX ,^X cpu0/regs/left_1f_3[5]
p IuQ1 ,^D0 Iu J@ J@ d d ' ' ,J ,J ,^ cpu0/regs/rightf_3[5]
q IiQ0 ,^A0 Ii J4 J4 ?%' ?%' 3ʺ 3ʺ ' ' ,J ,J ,^ cpu0/regs/left_1f_2[6]
r , Q1 ,^AB0 , -$ -$ & o & o #wK #wK ,JA ,JA ,^A cpu0/regs/rightf_2[6]
s , Q0 ,^;A0 , - - #S #S &Y &Y ,J; ,J; ,^; cpu0/regs/left_1f_2[0]
t Q1 ,^_C1 ' ' +J +J ,J_ ,J_ ,^_ cpu0/regs/rightf_2[0]
u Q0 ,^SA1 " } " } ,JS ,JS ,^S cpu0/regs/left_1f_2[1]
v ;.Q1 ,^B1 ;. ;! ;! 0 0 #k #k ,J ,J ,^ cpu0/regs/rightf_2[1]
w ;.Q0 ,^D1 ;. ;! ;! 0 0 #; #; ,J ,J ,^ cpu0/regs/left_1f_3[2]
x IQ1 IzZD1 I J^ J^ C C B B @< @< IfZ IfZ IzZ cpu0/regs/rightf_3[2]
y IQ0 IzTC1 I JR JR @WI @WI @W @W @W @W IfT IfT IzT cpu0/regs/left_1f_2[3]
z IQ1 b C0 I J"o J"o S:ܝ S:ܝ pm pm ߲ ߲ cpu0/regs/rightf_2[3]
{ IQ0 b
B0 I Jo Jo sJތ sJތ ܗ ܗ
cpu0/regs/un1_write_reg_addr_5
| J ,F0 J ,^+DI0 k BWB0 , -Q ,J+ ,^+ -Q ,J+ -Q &d &d o o .W .W BW cpu0/regs/un1_write_reg_addr_5f
} J ,Q0 b D0 0 ,^C1 ,^^D1 IzHA1 ,^MD0 ,^eD1 ,^C0 ,^C1 , -Q -Q #SC #SC ,J #SC ,J #SC ,J^ #SC #N #N ,J #SC 6B 6B IfH -Q % % #S #S ,Je #S ,JM % V4 V4 z z z z ,J ,^ ,J^ ,^^ IfH IzH ,JM ,^M ,Je ,^e ,J ,^ ,J ,^ cpu0/regs/left_1f_2[4]
~ ;.'Q1 ,^RB1 ;.' ;k ;k 3! 3! ( ( +P +P ,JR ,JR ,^R cpu0/regs/left_1f_2[7]
;.Q0 0 ,^A1 ;. ;k ;k 1] 1] '# '# #S #S ,J ,J ,^ cpu0/regs/rightf_2[7]
J ,
Q1 0 ,^D1 ,
-$Q -$Q & & #_ #_ ,J ,J ,^ cpu0/regs/ACCA_RNO[0]
! ʓF0 ! DI0 ʓ ɛ ɛ cpu0/regs/ACCB22_RNIDCT43
j ʓF0 ! ʙCE " ,^CE # ,^ɝCE $ :ɝCE ʓ ɛ ʙ ʙ ,J ,^ ,Jɝ ,^ɝ :ɝ :ɝ ɛ| |Q Q. . 8W 8W ~ ~ ʙ ɛ #/? #/? #/ #/ ,GƩ ,GƩ ,Jɝ . #S] #S] &YY &YY ,J #S] &Y- &Y- ,GW ,GW 0 0 1 1 :Ʃ :Ʃ :ɝ cpu0/regs/N_830
! ʟF1 ! DI1 ʟ ɛ ɛ cpu0/regs/N_847
" ,yF0 " ,^DI0 ,y -0 ,J ,^ -0 ,J cpu0/regs/N_864
" ,F1 " ,^DI1 , -< ,J ,^ -< ,J cpu0/regs/N_881
# ,ɗF0 # ,^DI0 ,ɗ ,; ,J ,^ ,; ,J cpu0/regs/N_898_0
# ,ɣF1 # ,^DI1 ,ɣ - ; ,J ,^ - ; ,J cpu0/regs/N_915
$ ;.ɗF0 $ :DI0 ;.ɗ ;; : : ;; : cpu0/regs/N_932
$ ;.ɣF1 $ :DI1 ;.ɣ ;; : : ;; : cpu0/regs/SU_16[0]
XJOFX0 < X )D0 XJ X X R R O X O X W ) W ) X ) cpu0/regs/SU_207_i1_mux
< XJ )4F0 > ,^ (C0 XJ )4 X (< ,J ( ,^ ( X (< M % M % 5 ! 5 ! ,J ( cpu0/regs/SU_16[1]
= , F1 = ,^ B0 , , y , y ,J ,J ,^ cpu0/regs/SU_208_i1_mux
= , F0 > ,^ (C1 , , ,J ( ,^ ( , &j &j ,J ( cpu0/regs/SU_16[2]
> F1 > D0 y y cpu0/regs/SU_209_i1_mux
> F0 = ,^ (C0 ,J ( ,^ ( ' ' + * + * ,J ( cpu0/regs/SU_16[3]
? uf &F1 ? u$ bC0 uf & v " v " u b u b u$ b cpu0/regs/SU_210_i1_mux
? uf F0 = ,^ )C1 uf u " ,J ) ,^ ) u " y] y] U8 U8 #q 'r #q 'r &Y % &Y % ,J ) cpu0/regs/SU_16[4]
@ *F1 @ fC0 * r r f f f cpu0/regs/SU_211_i1_mux
@ F0 < ,^ )|C0 f ,J )| ,^ )| f o o ' ' #5 #5 ,J )| cpu0/regs/SU_16[5]
A , CtF1 A ,^ CC0 , Ct -< Bp -< Bp ,J C ,J C ,^ C cpu0/regs/SU_212_i1_mux
A , ChF0 < ,^ )C1 , Ch -0 Bp ,J ) ,^ ) -0 Bp #; 3 #; 3 ,J ) cpu0/regs/SU_16[6]
B XJ 'F1 B X (D0 XJ ' X< ' X< ' R % R % W ( W ( X ( cpu0/regs/SU_213_i1_mux
B XJ 'F0 ; : (C0 XJ ' X6 ' : ( : ( X6 ' DR !( DR !( : ( cpu0/regs/SU_16[7]
C 'F1 C (D0 ' ' ' % % ( ( ( cpu0/regs/SU_214_i1_mux
C 'F0 ; : (C1 ' ' : ( : ( ' '$ !. '$ !. : ( cpu0/regs/SS_16[0]
XJCOFX0 D XD0 XJC X X V V W W X cpu0/regs/SS_223_i1_mux
D XJF0 G X 5C0 XJ Xo W 5 X 5 Xo R6 R6 Q
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U6 U` 6 U`> X > X, ] , ]@ ] ] ] cpu0/alu/alu8/N_1440 . ( ;. PF1 @ 5B0 ;. P ; O ; O ~ I ~ I @ @, 5 , 5@ 5 cpu0/alu/alu8/daa8l_r 4 if \F1
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o O 4z O 4z W 5 cpu0/regs/SS_16[1]
E XJF1 E X-C0 XJ X X W- W- X- cpu0/regs/SS_224_i1_mux
E XJF0 G X 5C1 XJ X W 5 X 5 X P ] P ] O 4V O 4V W 5 cpu0/regs/SS_16[2]
F XJ &F1 F X bC0 XJ & X " X " W b W b X b cpu0/regs/SS_225_i1_mux
F XJ F0 F X 6C0 XJ X " W 6 X 6 X " R R O 4 O 4 R 2 R 2 W 6 cpu0/regs/SS_16[3]
G uf F1 G u$ C0 uf u u u u u$ cpu0/regs/SS_226_i1_mux
G uf F0 F X 60C1 uf u W 60 X 60 u a a N ' N ' W 60 cpu0/regs/SS_16[4]
H I F1 H Iz C0 I J: J: If If Iz cpu0/regs/SS_227_i1_mux
H I F0 E X 6C0 I J. W 6 X 6 J. M M N & N & W 6 cpu0/regs/SS_16[5]
I ;. 5^F1 I : 5C0 ;. 5^ ; 4 ; 4 : 5 : 5 : 5 cpu0/regs/SS_228_i1_mux
I ;. 5RF0 E X 6C1 ;. 5R ; 4 W 6 X 6 ; 4 D .0 D .0 V 7* V 7* W 6 cpu0/regs/SS_16[6]
J I 5^F1 J Iz 5C0 I 5^ J 4 J 4 If 5 If 5 Iz 5 cpu0/regs/SS_229_i1_mux
J I 5RF0 D f 5 C0 I 5R J 4 f 5 f 5 J 4 M 2 M 2 a .< a .< f 5 cpu0/regs/SS_16[7]
K ;. *F1 K : fC0 ;. * ; ; : f : f : f cpu0/regs/SS_230_i1_mux
K ;. F0 D f 54C1 ;. ; f 54 f 54 ; d d ] 'r ] 'r f 54 cpu0/regs/SU_16[8]
L XJ F1 L X B0 XJ X< y X< y W W X cpu0/regs/SU_215_i1_mux
L XJ F0 : : (C0 XJ X6 : ( : ( X6 M f M f 60 60 1 '* 1 '* : ( cpu0/regs/SU_16[9]
M I )@F1 M Iz )|C0 I )@ JX (< JX (< If )| If )| Iz )| cpu0/regs/SU_216_i1_mux
M I )4F0 : : (C1 I )4 JL (< : ( : ( JL (< 6 6 9 $ 9 $ : ( cpu0/regs/SU_16[10]
N ;. 6ZF1 N : 6C0 ;. 6Z ; 5V ; 5V : 6 : 6 : 6 cpu0/regs/SU_217_i1_mux
N ;. 6NF0 9 : (C0 ;. 6N ; 5V : ( : ( ; 5V ?% 2 ?% 2 @ ' @ ' 5 !( 5 !( : ( cpu0/regs/SU_16[11]
O f F1 O f D0 f f y f y ` ` f f f cpu0/regs/SU_218_i1_mux
O f F0 9 : )C1 f f : ) : ) f \A ` \A ` E E 1 & 1 & : ) cpu0/regs/SU_16[12]
P , 5^F1 P ,^ 5C0 , 5^ - 4 - 4 ,J 5 ,J 5 ,^ 5 cpu0/regs/SU_219_i1_mux
P , 5RF0 8 : )|C0 , 5R , 4 : )| : )| , 4 & - & - 6 6 9 * 9 * : )| cpu0/regs/SU_16[13]
Q ;. 5F1 Q : 6C0 ;. 5 ; 5& ; 5& : 6 : 6 : 6 cpu0/regs/SU_220_i1_mux
Q ;. 5F0 8 : )C1 ;. 5 ; 5& : ) : ) ; 5& 5. - 5. - : ) cpu0/regs/SU_16[14]
R I AF1 R Iz B X ZA0 ? Iz ZA0 @ Iz (zB0 A f B0 B ,^ 6A0 C ,^ 6B0 D X CB0 E Iz BB0 2 , * - - V. V. ph ph u V. O!
P O!
P WI - ,G * ,G * ,J ` ph u x - " ` " ` V. P B P B D ;8 D ;8 : B V. O 'r O 'r W ( - #Y '* #Y '* 6 !
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$ OC1 f \ \D \D% N % N O O$ O cpu0/regs_o_su_m_0[2] f ;. 4F1 Iz 5C1 ;. 4 ; 4 If 5 Iz 5 ; 4 Dd .< Dd .< If 5 cpu0/N_236 \ I CtF1 X 6C1 I Ct JX Bp W 6 X 6 JX Bp S ; S ; N 3 N 3 W 6 cpu0/N_250 1 I 'F1 X 6C0 I ' I ' W 6 X 6 I ' C C S S N & N & W 6 cpu0/alu/datamux_o_alu_in_left_path_data[2] w 4F0 @ 5DI0 4n 4 , 5@ 5 n 4, 5 cpu0/alu/alu8/q_out_sn_N_3 E g \.F1 PM0
$ ObB1 @ \vA1 Ҳ C1 BHB1 A1 ҲD1 \. [ P P [ N [ Z Z, UZ , UZ, \v N _ _ Ҟ Z W
W
M M BH N 4 4 j j N L L P L P| P| L L Ob L )[ )[t tҞ Ob$ Ob , \v@ \v Ҟ Ҳ BH BH ҞҲ cpu0/alu/alu8/N_108 F P|OFX0 @ ]rA1 P|b O b O M M͜ Hp ͜ HpS [ S [, ]r , ]r@ ]r cpu0/alu/alu8/vneg8_r_5 G OF0 PD1 O, O* , O* L L P P P cpu0/alu/alu8/neg8_w[7] H OF0 hҲ C,B0 PC1 ҲC1 O N N )y )y2 ! 2 !ɹ 4h ɹ 4hҞ C, N Lb Lb P )y Ҟ Ҟ C,Ҳ C, P P ҞҲ cpu0/alu/alu8/neg8_w[3] I J PF0 PA1 Ҳ B1 d$ PdC1 J P OZ OZ HL HL Q^ Q^ Pd HL P OZ )a )a ɉ ɉ Ҟ P P Ҟ Ҳ Pd$ Pd cpu0/alu/alu8/neg8_w[2] J J OF1 PB1 @ \|B1 d$ P^B1
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J O O* O* HX HX P HX P^ HXt H( t H( [ [, \| P P , \|@ \| P^$ P^ cpu0/alu/alu8/CCRo14_1 L h BxF1 PC0 Bx8 B 8 B G G P P P cpu0/alu/alu8/k_cpu_addr_28_iv_1[0] M IMF0 u$A0 IM I2 I2 R R pzܑ pzܑ u u u$ cpu0/alu/alu8/un1_k_cpu_addr_1_m[0] O XJ (F0 u$D0 XJ ( X ( X ( P( P( b4_ b4_ ]mQ ]mQ py py u u u$ cpu0/k_cpu_addr_28[0] k ufF0 u$DI0 uf uo u u$ uo u cpu0/un1_k_cpu_addr_1_axb_0 2 I *F1 X )D0 I * J J C o C o S S N N W ) W ) X ) cpu0/alu/alu8/k_cpu_addr_28_iv_1[2] R I F0 X C0 I I I R R W W X cpu0/alu/alu8/un1_k_cpu_addr_1_m[2] S f 6NF0 X D0 f 6N gh 5V gh 5V \A 2 \A 2 O '` O '` W W X cpu0/k_cpu_addr_28[2] n XJ F0 X DI0 XJ X6 W X X6 W cpu0/alu/alu8/k_cpu_addr_28_iv_1[13] V ;.MF0 f )
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If (z ph f #Y '* ,J 6 #Y '* ,J 6 O 'r O A O A R ?6 R ?6 W C D ;8 If B 6 !
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@{ " @{ " If V " ` G G b" b" W Z V. p p S S If Z WI XI ,J ` ,^ ` u u$ u x u$ x : B : B W ( X ( If V Iz V W Z X Z If Z Iz Z If (z Iz (z f f ,J 6 ,^ 6 ,J 6 ,^ 6 W C X C If B Iz B cpu0/regs/SU_3_sqmuxa
;. 4F0 X M0 = ,^ C1 > B1 ? u$ D1 @ xB1 A ,^ CA1 B X (C1 C (A1 L X C1 M Iz )D1 N : 6B1 O f C1 P ,^ 5B1 Q : 6$A1 R Iz BNC1 S Iz CJC1 8 ;. 4 ; 4 W X ; 4 5( - 5( - 2 j 2 j Dd Dd O!K O!K W W W 2 j 'Z 'Z #q X #q X ,J ; 4 ` 0% ` 0% O '` O '` Dd a a l7 X l7 X u x #q X #q 4 #q 4 &Y ?< &Y ?< ,J C Dd @ X @ X R !" R !" W ( l7 X a a W @ X If ) ; 4 4 2 4 2 : 6 a f #q 4 ,J 5 ; 4 4 2( 4 2( : 6$ #q 4 5 ;V 5 ;V If BN 5 ;V If CJ ; 4 0 2 0 2 \ . \ . & & ( ,J ,^ u u$ x x ,J C ,^ C W ( X ( ( ( W X If ) Iz ) : 6 : 6 f f ,J 5 ,^ 5 : 6$ : 6$ If BN Iz BN If CJ Iz CJ cpu0/regs/SS_3_sqmuxa
c XJF1 XB0 c XC0 8 u$ D0 9 u$ fC0 : B1 ; : BB1 < X )
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f )
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A1 = Iz zC1 > X rA1 ? Iz xB1 @ Iz (A1 A f A1 B ,^ 6A1 C ,^ 6$A1 D X CC1 E Iz BA1 3 XJ X X P 7 P 7 N & N & W r N & EN EN H6 H6 If x N & W %D W %D W )
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EN @E & @E & If ( N & bX bX t t u f bX u EN ' ' P 7 E . E . ' . ' . ,J 6$ ' . ,J 6 E . 1 A 1 A 4 ?B 4 ?B : B bX e e f X W X W P 7 N @ N @ W C 1 A D ;& D ;& If B E . @c & @c & Ic 0 Ic 0 If z W X W X u u$ u f u$ f : B : B W )
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cpu0/alu/alu8/un1_k_cpu_addr_1_m[13] X f 5RF0 f )B1 f 5R g, 4 g, 4 ] '` ] '` f ) f ) f ) cpu0/k_cpu_addr_28[13] y f (F1 f (DI1 f ( gV ( f ( f ( gV ( f ( cpu0/alu/alu8/k_cpu_addr_28_iv_1[7] Z XJcF0 X )C1 XJc X X P W P W N 3 N 3 W ) W ) X ) cpu0/alu/alu8/un1_k_cpu_addr_1_m[7] \ XJ 'F0 X )D1 XJ ' X6 ' X6 ' R % R % W ) W ) X ) cpu0/k_cpu_addr_28[7] s XJ )@F1 X )jDI1 XJ )@ X (< W )j X )j X (< W )j cpu0/alu/alu8/k_cpu_addr_28_iv_1[6] ^ ;.F0 X )|C0 ;. ; ; 4P 4P 3 ( 3 ( D@ !. D@ !. W )| W )| X )| cpu0/alu/alu8/un1_k_cpu_addr_1_m[6] ` f (8F0 X )D0 f (8 g, ' g, ' S( ! S( ! W $ W $ W ) W ) X ) cpu0/k_cpu_addr_28[6] r XJ )4F0 X )dDI0 XJ )4 X (< W )d X )d X (< W )d cpu0/un1_k_cpu_addr_1_cry_13_0_S0 XJ 6NF0 f 5D0 XJ 6N X 5V X 5V b4 . b4 . f 5 f 5 f 5 cpu0/un1_k_cpu_addr_1_cry_7_0_S0 XJ 4F0 X (D0 XJ 4 X6 4 X6 4 RD - RD - W ( W ( X ( cpu0/un1_k_cpu_addr_1_cry_5_0_S1 I 6ZF1 f (D0 I 6Z JX 5V JX 5V @K & @K & S S f ( f ( f ( cpu0/un1_k_cpu_addr_1_cry_1_0_S1 I 5^F1 f 6D0 I 5^ J 4 J 4 M 2 M 2 bX - bX - f 6 f 6 f 6 cpu0/alu/alu8/k_cpu_addr_28_iv_0[0] h IYF1 IzB0 IY I& I& If If Iz cpu0/alu/alu8/k_cpu_addr_28_iv_0[2] i ;.oF1 Iz D0 ;.o ; ; ?%c ?%c @ @ @ 4 @ 4 If If Iz cpu0/alu/alu8/k_cpu_addr_28_iv_0[6] k ;.F1 :)C0 ;. ;ֵ ;ֵ 1- 1- :) :) :) cpu0/alu/alu8/k_cpu_addr_28_iv_0[7] m XJ?F1 XD0 XJ? X< X< R R NG NG W W X cpu0/alu/alu8/k_cpu_addr_28_iv_0[13] o ;.F1 :D0 ;. ;o ;o : : : cpu0/alu/alu8/N_1417 y > CtF1 \ PA1 Ct: Bp : Bp' M ' MW LV W LVH P H P\ P cpu0/alu/alu8/CCRo_sn_N_2 l \.F1 @ BM0 @#M0 @ ]BM0 B \M0 @ M0 \. [ , B@ B ,#@# , ]B@ ]B . \ B \ , @ [ Z Z| V | V M M) ?r ) ?r, B M A A# #; ;,# [
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If z Iz z W r X r If x Iz x If ( Iz ( f f ,J 6 ,^ 6 ,J 6$ ,^ 6$ W C X C If B Iz B cpu0/regs/SS_4_sqmuxa
;.;F1 XmM0 E X?B1 F X tB1 G u$ C1 H Iz B1 I : 5B1 J Iz 5C1 K : D1 T XD1 U Iz 54C1 V Iz )
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, U 4 X 4 X . \ ## # ; ; , # O O5 h 5 h, ]B cpu0/alu/alu8/N_1260 IF1 IzB1 I J:Q J:Q C C If If Iz cpu0/alu/alu8/N_1272 ;.ֽF1 :LA1 ;.ֽ ;U ;U 1ț 1ț 1 1 :L :L :L cpu0/alu/datamux_o_alu_in_left_path_data[14] ,{OFX0 ,^DI0 ,{ ,l ,J ,^ ,l ,J cpu0/k_eahi[6] R uf Q0 u$ B0 :D1 uf uU uU y] y] |$ |$ ph ph u y] U8@ U8@ 5 5 1 1 4{ 4{ : u u$ : : cpu0/alu/q8_out[5] BOFX1 i ,^ ~C1 ,^ BD1 B 7 Aa 7 Aa " ? " ? ,J B 7 Aa _ _ '$ '$ ,J ~ ,J ~ ,^ ~ ,J B ,^ B cpu0/alu/q8_out[6] OFX1 i ,^ rA1 ,^ A1 l l & & ,J & ,J r ,J r ,^ r ,J ,^ cpu0/alu/alu8/CCRo_4_3[2] i , *F1 @ BTD1 , * - - & o & o %` 5 %` 5 U U^ Ws ^ WsM N M N, BT , BT@ BT cpu0/alu/alu8/N_114 a ]F0 @ ]~C1 ] \ \, ]~ , ]~@ ]~ cpu0/alu/alu8/N_167 BfOFX0 BFXA Bf
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A1 W f tB1 X Iz 6C1 Y ,^ 54C1 Z X BNC1 [ u$ BD1 : ;.; ;օ Wm Xm ;օ 5( 5( 36 36 2 ' 2 ' : 5 2 ' D@ .H D@ .H If 5 D@ .H If 54 36 D@ D@ @ ' @ ' If )
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A B B
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D@ .H If 6 @ ' 5 .B 5 .B ,J 54 D@ .H O' A O' A W BN 5( d d ~ ~ lC lC anܻ anܻ W ߲ W ߲ Wm anܻ O'C O'C W? D@ V V W t D@ a\ a\ u 36 D D If O' A DR Hv DR Hv 2 A 2 A 1 ' 1 ' : D O
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, R R W a\ eR eR f t D@ .H a . a . l A: l A: u B W? X? W t X t u u$ If Iz : 5 : 5 If 5 Iz 5 : : W X If 54 Iz 54 If )
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A B cpu0/alu/alu8/N_158 AOFX0 B FXB A A B B A B cpu0/alu/alu8/N_168 OFX0 FXA b " b " cpu0/alu/alu8/N_159 OFX0 FXB D D cpu0/alu/alu8/N_163
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Iz )
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f OOFX0
$ O FXA f O^ N O $ O ^ N O cpu0/alu/alu8/N_154
f OOFX0
$ O&FXB f OO N O&$ O& O N O& cpu0/alu/q8_out[1]
f O OFX1 hҲ CDB1 B OhC1 f O ċ N{ ċ N{ Jn Jn
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f t f t If 6 Iz 6 ,J 54 ,^ 54 W BN X BN u B u$ B cpu0/regs/N_280
b , F0 = ,^ D1 , , , ,G $ ,G $ ,J ,J ,^ cpu0/regs/N_244
c XJF0 E XEC1 XJ X X R6 R6 WE WE XE cpu0/regs/N_245
8 uf F0 F X zC1 uf uR uR an an W z W z X z cpu0/regs/N_281
8 uf F1 > D1 uf uX y uX y y] y] UD s UD s cpu0/regs/N_246
9 uf F0 G u$ D1 uf u u u
0 u
0 u u u$ cpu0/regs/N_282
9 uf *F1 ? u$ zC1 uf * u u u z u z u$ z cpu0/regs/N_283
: F0 @ ~C1 ~ ~ ~ cpu0/regs/N_247
: F1 H Iz C1 " " 5 5 If If Iz cpu0/regs/N_284
; ;. BlF0 A ,^ CD1 ;. Bl ; B ; B 0 @ 0 @ ,J C ,J C ,^ C cpu0/regs/N_248
; ;. BxF1 I : 5C1 ;. Bx ; B ; B 5. : 5. : : 5 : 5 : 5 cpu0/regs/N_285
< XJ (F0 B X ( D1 XJ ( X ( X ( W ( W ( X ( cpu0/regs/N_249
< XJ (F1 J Iz 5D1 XJ ( X ( X ( R - R - E* - E* - If 5 If 5 Iz 5 cpu0/regs/N_286
= I F0 C ( D1 I JL " JL " C C 6 ! 6 ! ( ( ( cpu0/regs/N_250
= I &F1 K : rA1 I & JX " JX " ?% f ?% f : r : r : r cpu0/regs/ACCA_9_iv_5_39_1
X F0 ! B1 k k o o cpu0/regs/ACCA_9_iv_159_0_0
a }F0 $ :A1 } f! f! '] '] : : : cpu0/regs/ACCA_9_iv_4_59_1
\ yF0 " ,^D0 y " " ,J ,J ,^ cpu0/regs/ACCA_9_iv_3_79_1
] ,}F0 " ,^A1 ,} ,! ,! ,G ,G ,J ,J ,^ cpu0/regs/ACCA_9_iv_0_139_1
` ,F0 $ :A0 , -k -k 0 0 : : : cpu0/regs/ACCA_9_iv_2_99_1
^ ,F0 # ,^B0 , , , &Ym &Ym ,J ,J ,^ cpu0/regs/ACCA_9_iv_1_119_1
_ ,ʓF0 # ,^A1 ,ʓ -0ɛ -0ɛ +V~ +V~ ,J ,J ,^ cpu0/regs/N_287
> XJ F0 L X D1 XJ X X W $ W $ W W X cpu0/regs/N_251
> XJ *F1 T XB1 XJ * X X O
O
W W X cpu0/regs/N_288
? I F0 M Iz )A1 I J J @ 'N @ 'N If ) If ) Iz ) cpu0/regs/N_252
? I *F1 U Iz 5:D1 I * J J @u '* @u '* If 5: If 5: Iz 5: cpu0/regs/N_289
@ I (8F0 N : 6D1 I (8 J ' J ' C - C - 6 - 6 - : 6 : 6 : 6 cpu0/regs/N_253
@ I (DF1 V Iz ) D1 I (D J ' J ' If ) If ) Iz ) cpu0/regs/N_290
A f F0 O f D1 f gJ gJ f f f cpu0/regs/N_254 A f F1 W f D1 f gV gV e^ e^ f f f cpu0/regs/N_291 B , 6NF0 P ,^ 5D1 , 6N -0 5V -0 5V +\ 19 +\ 19 ,J 5 ,J 5 ,^ 5 cpu0/regs/N_255 B , 6ZF1 X Iz 6D1 , 6Z -< 5V -< 5V 6 - 6 - If 6 If 6 Iz 6 cpu0/regs/N_292 C , 5F0 Q : 60C1 , 5 - 5& - 5& 0 2 0 2 : 60 : 60 : 60 cpu0/regs/N_256 C , 5F1 Y ,^ 5:D1 , 5 - 5& - 5& +& 7* +& 7* ,J 5: ,J 5: ,^ 5: cpu0/regs/N_293 D XJ ChF0 R Iz BTD1 XJ Ch X Bp X Bp E* ; E* ; If BT If BT Iz BT cpu0/regs/N_257 D XJ CtF1 Z X BTD1 XJ Ct X Bp X Bp W >S W >S W BT W BT X BT cpu0/regs/N_294 E I BlF0 S Iz CPD1 I Bl J B J B Ic ?~ Ic ?~ If CP If CP Iz CP cpu0/regs/N_258 E I BxF1 [ u$ BC1 I Bx J B J B M ? M ? bX ; bX ; t >S t >S u B u B u$ B cpu0/regs/ACCA_9_iv_6_19_0 Y F0 ! B0 a a cpu0/regs/un1_write_reg_addr_2
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Hv
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Hv . Oh Jn A A` ;D ` ;DҞ CD Ҟ CDҲ CD . Oh B Oh cpu0/alu/alu8/N_164 \OFX0 @ \:FXA \z [ , \:@ \: z [, \: cpu0/alu/alu8/N_155 \ OFX0 @ \@FXB \ k \
, \@@ \@ k \
, \@ cpu0/alu/q8_out[2] \:OFX1 hҲ CPD1 \ ]~C1 \: [ [ U UH ]~ [ Y Yɏ N ɏ N Ҟ CP Ҟ CPҲ CP H ]~\ ]~ cpu0/alu/alu8/N_165 OFX0 Ҳ FXA m Ҟ Ҳ mҞ cpu0/alu/alu8/N_156 OFX0 Ҳ FXB Ҟ Ҳ Ҟ cpu0/alu/q8_out[3] OFX1 hҲ CJC1 B (A1 ̾ ̾ ܖ ܖ . ( ̾ ɕ 3 ɕ 3Ҟ CJ Ҟ CJҲ CJ . ( B ( cpu0/alu/alu8/N_2513 F1 C1 D1 tZ tZ
b
b
b cpu0/alu/alu8/N_161 ]*F1 M0 BM0 >M0
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\ F1 ! A0 X WB0 X {D1 \ D0 ] ,^B0 ^ ,^[B0 _ ,^A0 ` ,^cD0 a D0 " 1 " 1 ,J d d d g g W { g ~ ~ '_ '_ #;/ #;/ ,J[ #;/ &Yg &Yg ,J #;/ ,Jc W W { { ,J ,^ ,J[ ,^[ ,J ,^ ,Jc ,^c cpu0/regs/ACCA_9_iv_5_39_0_tz O ,F0 X QA0 , , , &j &j ? ? ~ ~ Q Q Q cpu0/regs/N_926 X !F1 X ]C0 Y UA0 Y mA1 \ B0 ] ,^A0 ^ ,^gD0 _ ,^B0 ` ,^QA0 a B0 j BA0 ! k k ] k o o U o m k " ? " ? ,Jg k 9 9 9 ' ' 1
1
'1 '1 ,J k 'Q 'Q +P~ +P~ ,J 'Q ,JQ '1 U U k
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$ OM0 @ \M0 Ҳ BM0 : \A0 Ҳ PC0 # ]* \t B B > > O$ O , \@ \ Ҟ BҲ B \t 6{ 6{v v m m > m $ $ \t { Z { Z Nf Nf ?6 ?6 B m O O H( H( Km Km O \t Y Y U< U< ^x ^x, \ m n n Ҟ B { Z ' UZ ' UZ : \ U<Ά U< Ά U<Ƀ M Ƀ MҞ P : \ : \ Ҟ PҲ P cpu0/alu/alu8/N_1358 UJF1 hD0 Jo o C C! ' ! ' h h h cpu0/alu/datamux_o_alu_in_right_path_data[2] Y J F0 JDI0 J " J J " J cpu0/alu/alu8/daa8h_r c 5F0 BD1 @B1
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K
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5 5& 5& - -k k, 5&L : L :
n =
n = ( ; ( ; B B B ,@ cpu0/alu/alu8/N_100 ]F1 B ]D1 ] \ \ U< U< . ] . ] B ] cpu0/alu/alu8/N_103 \.F1 B \A1 \. [ [ { Y { Y . \ . \ B \ cpu0/alu/alu8/c8_sn_N_20 \F0 B ] C1 \ f \D f \D h h
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K . ] ] U U m m ,J ,^ ,Jg ,^g ,J ,^ ,JQ ,^Q . B cpu0/regs/ACCA_9_iv_4_59_0_tz
O , F1 \ A0 , , , " " cpu0/regs/ACCA_9_iv_3_79_0_tz ] ,F1 ] ,^D0 , - ! - ! ,G} ,G} ,J ,J ,^ cpu0/regs/ACCA_9_iv_2_99_0_tz ^ ,%F1 ^ ,^UA0 ,% , , &Ya &Ya ,JU ,JU ,^U cpu0/regs/ACCA_9_iv_1_119_0_tz _ ,ʟF1 _ ,^C0 ,ʟ -<ɛ -<ɛ ,J ,J ,^ cpu0/regs/ACCA_9_iv_0_139_0_tz ` ,!F1 ` ,^]C0 ,! - k - k ,J] ,J] ,^] cpu0/regs/ACCA_9_iv_159_0_tz a F1 a A0 r! r! cpu0/regs/N_1743 :ɣF1 ]zgD0 ɣ ; ;fg fgzg cpu0/next_push_state[2] Q1 ]zaC0 #zוD1
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b b
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"o "oj ju uE Eum umfa EE Efו faza fוzו cpu0/regs/state_32_0_iv_0_568_i_0
m%F1 ]z[B0 m%m mg g Q Q f[ f[z[ cpu0/N_1742_i ]F0 ]zIDI0 fIzI fI cpu0/regs/cff_0_sqmuxa 6F1 d{C0 :ֵ :ֵ { {{ cpu0/regs/cff_1_sqmuxa_2 ~F0 dցD0 A1 ց
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b b O [ O [ . ] . ] B ] cpu0/alu/alu8/c8_sn_N_21 ]F0 B \B1 ] \ \ . \ . \ B \ cpu0/alu/alu8/N_2509 CtF1 @ ]D1 Ҳ rA1
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CtӐ Bp Ӑ Bp ? ?G N G N) Y ) Y, ] Ӑ Bp : :Ƀ & Ƀ &Ҟ r , ]@ ] Ҟ rҲ r cpu0/un1_regs_o_su_iv_0[15] f 5F1 f 5B0 f 5 gV 5& gV 5& eR 7* eR 7* f 5 f 5 f 5 cpu0/alu/alu8/N_112 a ]F1 a@ ]B0 ] \ \2 X 2 X, ] , ]@ ] cpu0/alu/alu8/N_126 , \OFX0 : ]D1 , \ , [ , [ 0 Z 0 Z : ] : ] : ] cpu0/alu/alu8/N_135 _ ;. ]F1 : ] C1 ;. ] ; \ ; \ 9 X 9 X : ] : ] : ] cpu0/alu/alu8/neg8_w[1] J OF0
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lD1 mmֵ mֵg g l ll cpu0/N_952 { JNF1 C0 JN cpu0/regs/N_629 XJ F1 XAB0 XJ X< X< WA WA XA cpu0/regs/N_677 ;.UF1 :C0 ;.U ; ; : : : cpu0/regs/N_672 fF1 fC0 f gt gt f f f cpu0/regs/N_671 XJF1 X)C0 XJ X X W) W) X) cpu0/regs/N_670 ,F1 ,^C0 , -<ֵ -<ֵ ,J ,J ,^ cpu0/regs/N_669 ;.F1 :C0 ;. ; ; : : : cpu0/regs/N_668 IF1 Iz-C0 I J J If- If- Iz- cpu0/regs/N_667 XJsF1 XB0 XJs X<@ X<@ W W X cpu0/regs/N_666 ,;F1 ,^wC0 ,; - օ - օ ,Jw ,Jw ,^w cpu0/PC_pipe_15 XJ+Q1 B1 XJ+ X? X? z z cpu0/PC_pipe_1_1 XJTQ1 D1 XJT X X P P zK zK cpu0/regs/N_665 XJYF1 XB0 XJY X<& X<& W W X cpu0/regs/N_630 F1 C0 cpu0/regs/N_631 , F1 ,^ C0 , - - ,J ,J ,^ cpu0/regs/N_632 IoF1 IzD0 Io J: J: HB HB If If Iz cpu0/regs/N_633 ,F1 ,^C0 , -< -< ,J ,J ,^ cpu0/regs/N_634
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% .a .a Ba cpu0/regs/N_210 IF0 , XC1 I If If CP CP B B 5 5 X X X cpu0/regs/N_209 ;. F0 - BD1 ;. ; " ; " ~ s ~ s +9 +9 . . B cpu0/regs/N_208 ;. F0 .\ZD1 ;. ; ; x x ! ! HZ HZ\Z cpu0/regs/N_673 ;.F1 :C0 ;. ; ; : : : cpu0/regs/N_716 &F1 bC0 & " " b b b cpu0/regs/N_643 IF1 IzC0 I JX JX If If Iz cpu0/regs/N_706 4F0 8 66D1 4 4 4 2. 2. 66 66 66 cpu0/regs/N_679 foF1 fC0 fo gV gV f f f cpu0/regs/N_640 $ F1 C0 cpu0/regs/N_676 ' ;.ʟF1 :C0 ;.ʟ ;ɛ ;ɛ : : : cpu0/regs/N_642 , IF1 IzA0 I J o J o Ic Ic If If Iz cpu0/N_711 s ;. BF0 : BTD1 : C>A1 ;. B ; B@ ; B@ : BT ; B@ 9 DD 9 DD : C> : BT : BT : C> : C> cpu0/regs/N_678 . ,F1 ,^C0 , - o - o ,J ,J ,^ cpu0/PC_pipe z ʙQ0 iA1 ʙ 4ɛ 4ɛ K K i i i cpu0/PC_pipe_1_0 y XJHQ0 {D1 XJH X X R/ R/ P P z z { { { cpu0/regs/N_644 3 ;.F1 :C0 ;. ;! ;! : : : cpu0/eflag_11_m0 b cɗF0 AC1 BA0
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;b C2 C2 C2 cpu0/regs/N_675 = ;.YF1 :B0 ;.Y ; & ; & : : : cpu0/regs/N_638 @ XJ;F1 XwC0 XJ; Xօ Xօ Ww Ww Xw cpu0/regs/N_726 A 4F1 , 6D1 4 4 4 2( 2( 6 6 6 cpu0/regs/N_674 B ;.F1 :C0 ;. ;o ;o : : : cpu0/regs/N_637 H IYF1 IzB0 IY I& I& If If Iz cpu0/N_701 p XJ BlF0 X OC0 X BC1 X C,B0 X CDB1 XJ Bl X B X B W B X B O N O N W O X B W ?r W ?r W C, X B W CD W O X O W B X B W C, X C, W CD X CD cpu0/k_write_post_incdec 9Q0 ' IzoA0 ) ,^D0 q IzUB1 :wC0 9 ] ]r r 'Hϛ 'Hϛ Dk Dk Ifo 'Hϛ :w ˴P ˴Pp # p # %u@ %u@ #e #e ,J p # s@ s@ *r *r D D IfU Ifo Izo ,J ,^ IfU IzU :w :w cpu0/next_mem_state[4]
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