#-- Lattice Semiconductor Corporation Ltd.
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#-- Lattice Semiconductor Corporation Ltd.
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#-- Synplify OEM project file
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#-- Synplify OEM project file
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#device options
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#device options
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set_option -technology MACHXO2
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set_option -technology MACHXO2
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set_option -part LCMXO2_7000HE
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set_option -part LCMXO2_7000HE
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set_option -package TG144C
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set_option -package TG144C
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set_option -speed_grade -4
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set_option -speed_grade -4
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#compilation/mapping options
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#compilation/mapping options
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set_option -symbolic_fsm_compiler true
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set_option -symbolic_fsm_compiler true
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set_option -resource_sharing true
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set_option -resource_sharing true
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#use verilog 2001 standard option
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#use verilog 2001 standard option
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set_option -vlog_std v2001
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set_option -vlog_std v2001
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#map options
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#map options
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set_option -frequency auto
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set_option -frequency auto
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set_option -maxfan 1000
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set_option -maxfan 1000
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set_option -auto_constrain_io 0
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set_option -auto_constrain_io 0
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set_option -disable_io_insertion false
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set_option -disable_io_insertion false
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set_option -retiming false; set_option -pipe true
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set_option -retiming false; set_option -pipe true
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set_option -force_gsr false
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set_option -force_gsr false
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set_option -compiler_compatible 0
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set_option -compiler_compatible 0
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set_option -dup false
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set_option -dup false
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set_option -frequency 1
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set_option -frequency 1
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set_option -default_enum_encoding default
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set_option -default_enum_encoding default
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#simulation options
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#simulation options
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#timing analysis options
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#timing analysis options
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#automatic place and route (vendor) options
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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set_option -write_apr_constraint 1
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#synplifyPro options
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#synplifyPro options
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set_option -fix_gated_and_generated_clocks 1
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set_option -fix_gated_and_generated_clocks 1
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set_option -update_models_cp 0
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set_option -update_models_cp 0
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set_option -resolve_multiple_driver 0
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set_option -resolve_multiple_driver 0
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#-- add_file options
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#-- add_file options
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set_option -include_path {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice}
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set_option -include_path {C:/02_Elektronik/020_V6809/trunk/syn/lattice}
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add_file -verilog {/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/defs.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/bios2k.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v}
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#-- top module name
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#-- top module name
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set_option -top_module CC3_top
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set_option -top_module CC3_top
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#-- set result format/file last
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#-- set result format/file last
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project -result_file {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi}
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project -result_file {C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809/P6809_P6809.edi}
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#-- error message log file
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#-- error message log file
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project -log_file {P6809_P6809.srf}
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project -log_file {P6809_P6809.srf}
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#-- set any command lines input by customer
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#-- set any command lines input by customer
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#-- run Synplify with 'arrange HDL file'
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#-- run Synplify with 'arrange HDL file'
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project -run
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project -run
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