URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [sim/] [rtl_sim/] [out/] [negcnt.out] - Diff between revs 185 and 186

Rev 185	Rev 186
`Loading snapshot worklib.oc8051_tb:v .................... Done`	`Loading snapshot worklib.oc8051_tb:v .................... Done`
`ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc`	`ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc`
`ncsim> run`	`ncsim> run`

`Warning! some objects excluded from $dumpvars due to -access -R`	`Warning! some objects excluded from $dumpvars due to -access -R`
`File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16`	`File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16`
`Scope: oc8051_tb`	`Scope: oc8051_tb`
`Time: 0 FS + 0`	`Time: 0 FS + 0`

`time 1 step 0: pass`	`time 1 step 0: pass`
`time 6496 step 1: pass`	`time 6496 step 1: pass`
`time 6646 step 2: pass`	`time 6646 step 2: pass`
`time 6796 step 3: pass`	`time 6796 step 3: pass`
`time 6946 step 4: pass`	`time 6946 step 4: pass`
`time 7096 step 5: pass`	`time 7096 step 5: pass`
`time 7246 step 6: pass`	`time 7246 step 6: pass`
`time 7396 step 7: pass`	`time 7396 step 7: pass`
`time 7546 step 8: pass`	`time 7546 step 8: pass`
`time 7696 step 9: pass`	`time 7696 step 9: pass`
`time 7846 step 10: pass`	`time 7846 step 10: pass`

`Done!`	`Done!`
`Simulation complete via $finish(1) at time 7846 NS + 2`	`Simulation complete via $finish(1) at time 7846 NS + 2`
`/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish;`	`/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish;`
`ncsim> exit`	`ncsim> exit`