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///
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///
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/// created by oc8051 rom maker
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/// created by oc8051 rom maker
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/// author: Simon Teran (simont@opencores.org)
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/// author: Simon Teran (simont@opencores.org)
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///
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///
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/// source file: D:\tmp\asm\xram.hex
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/// source file: D:\tmp\asm\xram.hex
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/// date: 10.7.02
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/// date: 10.7.02
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/// time: 10:36:12
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/// time: 10:36:12
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///
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///
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module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
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module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
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parameter INT_ROM_WID= 7;
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parameter INT_ROM_WID= 7;
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input rst, clk;
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input rst, clk;
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input [15:0] addr;
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input [15:0] addr;
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output ea_int;
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output ea_int;
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output [7:0] data1, data2, data3;
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output [7:0] data1, data2, data3;
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reg [7:0] data1, data2, data3;
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reg [7:0] data1, data2, data3;
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reg [7:0] buff [65535:0];
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reg [7:0] buff [65535:0];
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integer i;
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integer i;
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wire ea;
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wire ea;
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assign ea = | addr[15:INT_ROM_WID];
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assign ea = | addr[15:INT_ROM_WID];
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assign ea_int = ! ea;
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assign ea_int = ! ea;
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initial
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initial
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begin
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begin
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for (i=0; i<65536; i=i+1)
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for (i=0; i<65536; i=i+1)
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buff [i] = 8'h00;
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buff [i] = 8'h00;
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#2
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#2
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buff [16'h00_00] = 8'h02;
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buff [16'h00_00] = 8'h02;
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buff [16'h00_01] = 8'h00;
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buff [16'h00_01] = 8'h00;
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buff [16'h00_02] = 8'h35;
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buff [16'h00_02] = 8'h35;
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buff [16'h00_03] = 8'h90;
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buff [16'h00_03] = 8'h90;
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buff [16'h00_04] = 8'h00;
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buff [16'h00_04] = 8'h00;
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buff [16'h00_05] = 8'h00;
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buff [16'h00_05] = 8'h00;
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buff [16'h00_06] = 8'h74;
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buff [16'h00_06] = 8'h74;
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buff [16'h00_07] = 8'h01;
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buff [16'h00_07] = 8'h01;
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buff [16'h00_08] = 8'hF0;
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buff [16'h00_08] = 8'hF0;
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buff [16'h00_09] = 8'hFF;
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buff [16'h00_09] = 8'hFF;
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buff [16'h00_0a] = 8'h7E;
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buff [16'h00_0a] = 8'h7E;
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buff [16'h00_0b] = 8'h00;
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buff [16'h00_0b] = 8'h00;
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buff [16'h00_0c] = 8'h74;
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buff [16'h00_0c] = 8'h74;
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buff [16'h00_0d] = 8'hFF;
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buff [16'h00_0d] = 8'hFF;
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buff [16'h00_0e] = 8'h2F;
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buff [16'h00_0e] = 8'h2F;
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buff [16'h00_0f] = 8'hF5;
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buff [16'h00_0f] = 8'hF5;
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buff [16'h00_10] = 8'h82;
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buff [16'h00_10] = 8'h82;
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buff [16'h00_11] = 8'hEE;
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buff [16'h00_11] = 8'hEE;
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buff [16'h00_12] = 8'h34;
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buff [16'h00_12] = 8'h34;
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buff [16'h00_13] = 8'hFF;
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buff [16'h00_13] = 8'hFF;
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buff [16'h00_14] = 8'hF5;
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buff [16'h00_14] = 8'hF5;
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buff [16'h00_15] = 8'h83;
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buff [16'h00_15] = 8'h83;
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buff [16'h00_16] = 8'hE0;
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buff [16'h00_16] = 8'hE0;
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buff [16'h00_17] = 8'h04;
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buff [16'h00_17] = 8'h04;
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buff [16'h00_18] = 8'hFD;
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buff [16'h00_18] = 8'hFD;
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buff [16'h00_19] = 8'h74;
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buff [16'h00_19] = 8'h74;
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buff [16'h00_1a] = 8'h00;
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buff [16'h00_1a] = 8'h00;
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buff [16'h00_1b] = 8'h2F;
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buff [16'h00_1b] = 8'h2F;
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buff [16'h00_1c] = 8'hF5;
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buff [16'h00_1c] = 8'hF5;
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buff [16'h00_1d] = 8'h82;
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buff [16'h00_1d] = 8'h82;
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buff [16'h00_1e] = 8'hEE;
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buff [16'h00_1e] = 8'hEE;
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buff [16'h00_1f] = 8'h34;
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buff [16'h00_1f] = 8'h34;
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buff [16'h00_20] = 8'h00;
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buff [16'h00_20] = 8'h00;
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buff [16'h00_21] = 8'hF5;
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buff [16'h00_21] = 8'hF5;
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buff [16'h00_22] = 8'h83;
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buff [16'h00_22] = 8'h83;
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buff [16'h00_23] = 8'hED;
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buff [16'h00_23] = 8'hED;
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buff [16'h00_24] = 8'hF0;
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buff [16'h00_24] = 8'hF0;
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buff [16'h00_25] = 8'h0F;
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buff [16'h00_25] = 8'h0F;
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buff [16'h00_26] = 8'hBF;
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buff [16'h00_26] = 8'hBF;
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buff [16'h00_27] = 8'h00;
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buff [16'h00_27] = 8'h00;
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buff [16'h00_28] = 8'h01;
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buff [16'h00_28] = 8'h01;
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buff [16'h00_29] = 8'h0E;
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buff [16'h00_29] = 8'h0E;
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buff [16'h00_2a] = 8'hE4;
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buff [16'h00_2a] = 8'hE4;
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buff [16'h00_2b] = 8'hB5;
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buff [16'h00_2b] = 8'hB5;
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buff [16'h00_2c] = 8'h07;
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buff [16'h00_2c] = 8'h07;
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buff [16'h00_2d] = 8'hDE;
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buff [16'h00_2d] = 8'hDE;
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buff [16'h00_2e] = 8'hEE;
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buff [16'h00_2e] = 8'hEE;
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buff [16'h00_2f] = 8'hB4;
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buff [16'h00_2f] = 8'hB4;
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buff [16'h00_30] = 8'h08;
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buff [16'h00_30] = 8'h08;
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buff [16'h00_31] = 8'hDA;
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buff [16'h00_31] = 8'hDA;
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buff [16'h00_32] = 8'h80;
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buff [16'h00_32] = 8'h80;
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buff [16'h00_33] = 8'hFE;
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buff [16'h00_33] = 8'hFE;
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buff [16'h00_34] = 8'h22;
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buff [16'h00_34] = 8'h22;
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buff [16'h00_35] = 8'h78;
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buff [16'h00_35] = 8'h78;
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buff [16'h00_36] = 8'h7F;
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buff [16'h00_36] = 8'h7F;
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buff [16'h00_37] = 8'hE4;
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buff [16'h00_37] = 8'hE4;
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buff [16'h00_38] = 8'hF6;
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buff [16'h00_38] = 8'hF6;
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buff [16'h00_39] = 8'hD8;
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buff [16'h00_39] = 8'hD8;
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buff [16'h00_3a] = 8'hFD;
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buff [16'h00_3a] = 8'hFD;
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buff [16'h00_3b] = 8'h75;
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buff [16'h00_3b] = 8'h75;
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buff [16'h00_3c] = 8'h81;
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buff [16'h00_3c] = 8'h81;
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buff [16'h00_3d] = 8'h07;
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buff [16'h00_3d] = 8'h07;
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buff [16'h00_3e] = 8'h02;
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buff [16'h00_3e] = 8'h02;
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buff [16'h00_3f] = 8'h00;
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buff [16'h00_3f] = 8'h00;
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buff [16'h00_40] = 8'h03;
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buff [16'h00_40] = 8'h03;
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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data1 <= #1 buff [addr];
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data1 <= #1 buff [addr];
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data2 <= #1 buff [addr+1];
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data2 <= #1 buff [addr+1];
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data3 <= #1 buff [addr+2];
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data3 <= #1 buff [addr+2];
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end
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end
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endmodule
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endmodule
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