//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 cores acccumulator ////
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//// 8051 cores acccumulator ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// accumulaor register for 8051 core ////
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//// accumulaor register for 8051 core ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Nothing ////
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//// Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2003/06/03 17:16:16 simont
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// Revision 1.13 2003/06/03 17:16:16 simont
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// `ifdef added.
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// `ifdef added.
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//
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//
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// Revision 1.12 2003/04/09 16:24:03 simont
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// Revision 1.12 2003/04/09 16:24:03 simont
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// change wr_sft to 2 bit wire.
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// change wr_sft to 2 bit wire.
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//
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//
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// Revision 1.11 2003/04/09 15:49:42 simont
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// Revision 1.11 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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// Register oc8051_sfr dato output, add signal wait_data.
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//
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//
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// Revision 1.10 2003/04/07 14:58:02 simont
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// Revision 1.10 2003/04/07 14:58:02 simont
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// change sfr's interface.
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// change sfr's interface.
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//
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//
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// Revision 1.9 2003/01/13 14:14:40 simont
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// Revision 1.9 2003/01/13 14:14:40 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.8 2002/11/05 17:23:54 simont
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// Revision 1.8 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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// add module oc8051_sfr, 256 bytes internal ram
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//
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//
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// Revision 1.7 2002/09/30 17:33:59 simont
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// Revision 1.7 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_acc (clk, rst,
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module oc8051_acc (clk, rst,
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bit_in, data_in, data2_in,
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bit_in, data_in, data2_in,
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data_out,
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data_out,
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wr, wr_bit, wr_addr,
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wr, wr_bit, wr_addr,
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p, wr_sfr);
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p, wr_sfr);
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input clk, rst, wr, wr_bit, bit_in;
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input clk, rst, wr, wr_bit, bit_in;
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input [1:0] wr_sfr;
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input [1:0] wr_sfr;
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input [7:0] wr_addr, data_in, data2_in;
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input [7:0] wr_addr, data_in, data2_in;
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output p;
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output p;
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output [7:0] data_out;
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output [7:0] data_out;
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reg [7:0] data_out;
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reg [7:0] data_out;
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reg [7:0] acc;
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reg [7:0] acc;
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wire wr_acc, wr2_acc, wr_bit_acc;
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wire wr_acc, wr2_acc, wr_bit_acc;
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//
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//
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//calculates parity
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//calculates parity
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assign p = ^acc;
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assign p = ^acc;
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assign wr_acc = (wr_sfr==`OC8051_WRS_ACC1) | (wr & !wr_bit & (wr_addr==`OC8051_SFR_ACC));
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assign wr_acc = (wr_sfr==`OC8051_WRS_ACC1) | (wr & !wr_bit & (wr_addr==`OC8051_SFR_ACC));
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assign wr2_acc = (wr_sfr==`OC8051_WRS_ACC2);
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assign wr2_acc = (wr_sfr==`OC8051_WRS_ACC2);
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assign wr_bit_acc = (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_ACC));
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assign wr_bit_acc = (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_ACC));
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//
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//
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//writing to acc
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//writing to acc
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always @(wr_sfr or data2_in or wr2_acc or wr_acc or wr_bit_acc or wr_addr[2:0] or data_in or bit_in or data_out)
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always @(wr_sfr or data2_in or wr2_acc or wr_acc or wr_bit_acc or wr_addr[2:0] or data_in or bit_in or data_out)
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begin
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begin
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if (wr2_acc)
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if (wr2_acc)
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acc = data2_in;
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acc = data2_in;
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else if (wr_acc)
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else if (wr_acc)
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acc = data_in;
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acc = data_in;
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else if (wr_bit_acc)
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else if (wr_bit_acc)
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case (wr_addr[2:0]) /* synopsys full_case parallel_case */
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case (wr_addr[2:0]) /* synopsys full_case parallel_case */
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3'b000: acc = {data_out[7:1], bit_in};
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3'b000: acc = {data_out[7:1], bit_in};
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3'b001: acc = {data_out[7:2], bit_in, data_out[0]};
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3'b001: acc = {data_out[7:2], bit_in, data_out[0]};
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3'b010: acc = {data_out[7:3], bit_in, data_out[1:0]};
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3'b010: acc = {data_out[7:3], bit_in, data_out[1:0]};
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3'b011: acc = {data_out[7:4], bit_in, data_out[2:0]};
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3'b011: acc = {data_out[7:4], bit_in, data_out[2:0]};
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3'b100: acc = {data_out[7:5], bit_in, data_out[3:0]};
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3'b100: acc = {data_out[7:5], bit_in, data_out[3:0]};
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3'b101: acc = {data_out[7:6], bit_in, data_out[4:0]};
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3'b101: acc = {data_out[7:6], bit_in, data_out[4:0]};
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3'b110: acc = {data_out[7], bit_in, data_out[5:0]};
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3'b110: acc = {data_out[7], bit_in, data_out[5:0]};
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3'b111: acc = {bit_in, data_out[6:0]};
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3'b111: acc = {bit_in, data_out[6:0]};
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endcase
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endcase
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else
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else
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acc = data_out;
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acc = data_out;
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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data_out <= #1 `OC8051_RST_ACC;
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data_out <= #1 `OC8051_RST_ACC;
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else
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else
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data_out <= #1 acc;
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data_out <= #1 acc;
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end
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end
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`ifdef OC8051_SIMULATION
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`ifdef OC8051_SIMULATION
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always @(data_out)
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always @(data_out)
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if (data_out===8'hxx) begin
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if (data_out===8'hxx) begin
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$display("time ",$time, " faulire: invalid write to ACC (oc8051_acc)");
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$display("time ",$time, " faulire: invalid write to ACC (oc8051_acc)");
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#22
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#22
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$finish;
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$finish;
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end
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end
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`endif
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`endif
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endmodule
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endmodule
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